RISC-V Dependent Features
*************************

RISC-V Options
==============

The following table lists all available RISC-V specific options.

-fpic
-fPIC
     Generate position-independent code

-fno-pic
     Don't generate position-independent code (default)

-march=ISA
     Select the base isa, as specified by ISA.  For example -march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting --with-arch=ISA.

-misa-spec=ISAspec
     Select the default isa spec version.  If the version of ISA isn't set by -march, then assembler helps to set the version according to the default chosen spec.  If this option isn't set, then assembler will check the default configure setting --with-isa-spec=ISAspec.

-mpriv-spec=PRIVspec
     Select the privileged spec version.  We can decide whether the CSR is valid or not according to the chosen spec.  If this option and the privilege attributes aren't set, then assembler will check the default configure setting --with-priv-spec=PRIVspec.

-mabi=ABI
     Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none or "e" to indicate the soft-float calling convention ("e" indicates a soft-float RVE ABI).

-mrelax
     Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)

-mno-relax
     Don't do linker relaxations.

-march-attr
     Generate the default contents for the riscv elf attribute section if the .attribute directives are not set.  This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification.

-mno-arch-attr
     Don't generate the default riscv elf attribute section if the .attribute directives are not set.

-mcsr-check
     Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-dependent CSR are only valid when the specific ISA is set.  The read-only CSR can not be written by the CSR instructions.

-mno-csr-check
     Don't do CSR checking.

-mlittle-endian
     Generate code for a little endian machine.

-mbig-endian
     Generate code for a big endian machine.

RISC-V Directives
=================

The following table lists all available RISC-V specific directives.

.align SIZE-LOG-2
     Align to the given boundary, with the size given as log2 the number of bytes to align to.

.half VALUE
.word VALUE
.dword VALUE
     Emits a half-word, word, or double-word value at the current position.

.dtprelword VALUE
.dtpreldword VALUE
     Emits a DTP-relative word (or double-word) at the current position.  This is meant to be used by the compiler in shared libraries for DWARF debug info for thread local variables.

.uleb128 VALUE
.sleb128 VALUE
     Emits a signed or unsigned LEB128 value at the current position.  This only accepts constant expressions, because symbol addresses can change with relaxation, and we don't support relocations to modify LEB128 values at link time.

.option ARGUMENT
     Modifies RISC-V specific assembler options inline with the assembly code. This is used when particular instruction sequences must be assembled with a specific set of options.  For example, since we relax addressing sequences to shorter GP-relative sequences when possible the initial load of GP must not be relaxed and should be emitted as something like

          	.option push
          	.option norelax
          	la gp, __global_pointer$
          	.option pop

     in order to produce after linker relaxation the expected

          	auipc gp, %pcrel_hi(__global_pointer$)
          	addi gp, gp, %pcrel_lo(__global_pointer$)

     instead of just

          	addi gp, gp, 0

     It's not expected that options are changed in this manner during regular use, but there are a handful of esoteric cases like the one above where users need to disable particular features of the assembler for particular code sequences. The complete list of option arguments is shown below:

     push
     pop
          Pushes or pops the current option stack.  These should be used whenever changing an option in line with assembly code in order to ensure the user's command-line options are respected for the bulk of the file being assembled.

     rvc
     norvc
          Enables or disables the generation of compressed instructions.  Instructions are opportunistically compressed by the RISC-V assembler when possible, but sometimes this behavior is not desirable, especially when handling alignments.

     pic
     nopic
          Enables or disables position-independent code generation.  Unless you really know what you're doing, this should only be at the top of a file.

     relax
     norelax
          Enables or disables relaxation.  The RISC-V assembler and linker opportunistically relax some code sequences, but sometimes this behavior is not desirable.

     csr-check
     no-csr-check
          Enables or disables the CSR checking.

     arch, +EXTENSION[VERSION] [,...,+EXTENSION_N[VERSION_N]]
     arch, -EXTENSION [,...,-EXTENSION_N]
     arch, =ISA
          Enables or disables the extensions for specific code region.  For example, .option arch, +m2p0 means add m extension with version 2.0, and .option arch, -f, -d means remove extensions, f and d, from the architecture string.  Note that, .option arch, +c, -c have the same behavior as .option rvc, norvc.  However, they are also undesirable sometimes.  Besides, .option arch, -i is illegal, since we cannot remove the base i extension anytime.  If you want to reset the whole ISA string, you can also use .option arch, =rv32imac to overwrite the previous settings.

.insn TYPE, OPERAND [,...,OPERAND_N]
.insn INSN_LENGTH, VALUE
.insn VALUE
     This directive permits the numeric representation of an instructions and makes the assembler insert the operands according to one of the instruction formats for .insn (RISC-V-Formats). For example, the instruction add a0, a1, a2 could be written as .insn r 0x33, 0, 0, a0, a1, a2.  But in fact, the instruction formats are difficult to use for some users, so most of them are using .word to encode the instruction directly, rather than using .insn.  It is fine for now, but will be wrong when the mapping symbols are supported, since .word will not be shown as an instruction, it should be shown as data.  Therefore, we also support two more formats of the .insn, the instruction add a0, a1, a2 could also be written as .insn 0x4, 0xc58533 or .insn 0xc58533. When the INSN_LENGTH is set, then assembler will check if the VALUE is a valid INSN_LENGTH bytes instruction.

.attribute TAG, VALUE
     Set the object attribute TAG to VALUE.

     The TAG is either an attribute number, or one of the following: Tag_RISCV_arch, Tag_RISCV_stack_align, Tag_RISCV_unaligned_access, Tag_RISCV_priv_spec, Tag_RISCV_priv_spec_minor, Tag_RISCV_priv_spec_revision.

RISC-V Assembler Modifiers
==========================

The RISC-V assembler supports following modifiers for relocatable addresses used in RISC-V instruction operands.  However, we also support some pseudo instructions that are easier to use than these modifiers.

%lo(SYMBOL)
     The low 12 bits of absolute address for SYMBOL.

%hi(SYMBOL)
     The high 20 bits of absolute address for SYMBOL.  This is usually used with the %lo modifier to represent a 32-bit absolute address.

          	lui        a0, %hi(SYMBOL)     // R_RISCV_HI20
          	addi       a0, a0, %lo(SYMBOL) // R_RISCV_LO12_I

          	lui        a0, %hi(SYMBOL)     // R_RISCV_HI20
          	load/store a0, %lo(SYMBOL)(a0) // R_RISCV_LO12_I/S

%pcrel_lo(LABEL)
     The low 12 bits of relative address between pc and SYMBOL. The SYMBOL is related to the high part instruction which is marked by LABEL.

%pcrel_hi(SYMBOL)
     The high 20 bits of relative address between pc and SYMBOL. This is usually used with the %pcrel_lo modifier to represent a +/-2GB pc-relative range.

          LABEL:
          	auipc      a0, %pcrel_hi(SYMBOL)    // R_RISCV_PCREL_HI20
          	addi       a0, a0, %pcrel_lo(LABEL) // R_RISCV_PCREL_LO12_I

          LABEL:
          	auipc      a0, %pcrel_hi(SYMBOL)    // R_RISCV_PCREL_HI20
          	load/store a0, %pcrel_lo(LABEL)(a0) // R_RISCV_PCREL_LO12_I/S

     Or you can use the pseudo lla/lw/sw/... instruction to do this.

          	lla  a0, SYMBOL

%got_pcrel_hi(SYMBOL)
     The high 20 bits of relative address between pc and the GOT entry of SYMBOL.  This is usually used with the %pcrel_lo modifier to access the GOT entry.

          LABEL:
          	auipc      a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20
          	addi       a0, a0, %pcrel_lo(LABEL)  // R_RISCV_PCREL_LO12_I

          LABEL:
          	auipc      a0, %got_pcrel_hi(SYMBOL) // R_RISCV_GOT_HI20
          	load/store a0, %pcrel_lo(LABEL)(a0)  // R_RISCV_PCREL_LO12_I/S

     Also, the pseudo la instruction with PIC has similar behavior.

%tprel_add(SYMBOL)
     This is used purely to associate the R_RISCV_TPREL_ADD relocation for TLS relaxation.  This one is only valid as the fourth operand to the normally 3 operand add instruction.

%tprel_lo(SYMBOL)
     The low 12 bits of relative address between tp and SYMBOL.

%tprel_hi(SYMBOL)
     The high 20 bits of relative address between tp and SYMBOL.  This is usually used with the %tprel_lo and %tprel_add modifiers to access the thread local variable SYMBOL in TLS Local Exec.

          	lui        a5, %tprel_hi(SYMBOL)          // R_RISCV_TPREL_HI20
          	add        a5, a5, tp, %tprel_add(SYMBOL) // R_RISCV_TPREL_ADD
          	load/store t0, %tprel_lo(SYMBOL)(a5)      // R_RISCV_TPREL_LO12_I/S

%tls_ie_pcrel_hi(SYMBOL)
     The high 20 bits of relative address between pc and GOT entry.  It is usually used with the %pcrel_lo modifier to access the thread local variable SYMBOL in TLS Initial Exec.

          	la.tls.ie  a5, SYMBOL
          	add        a5, a5, tp
          	load/store t0, 0(a5)

     The pseudo la.tls.ie instruction can be expended to

          LABEL:
          	auipc a5, %tls_ie_pcrel_hi(SYMBOL) // R_RISCV_TLS_GOT_HI20
          	load  a5, %pcrel_lo(LABEL)(a5)     // R_RISCV_PCREL_LO12_I

%tls_gd_pcrel_hi(SYMBOL)
     The high 20 bits of relative address between pc and GOT entry.  It is usually used with the %pcrel_lo modifier to access the thread local variable SYMBOL in TLS Global Dynamic.

          	la.tls.gd  a0, SYMBOL
          	call       __tls_get_addr@plt
          	mv         a5, a0
          	load/store t0, 0(a5)

     The pseudo la.tls.gd instruction can be expended to

          LABEL:
          	auipc a0, %tls_gd_pcrel_hi(SYMBOL) // R_RISCV_TLS_GD_HI20
          	addi  a0, a0, %pcrel_lo(LABEL)     // R_RISCV_PCREL_LO12_I

RISC-V Floating Point
=====================

The RISC-V architecture uses IEEE floating-point numbers.

The RISC-V Zfa extension includes a load-immediate instruction for floating-point registers, which allows specifying the immediate (from a pool of 32 predefined values defined in the specification) as operand. E.g. to load the value 0.0625 as single-precision FP value into the FP register ft1 one of the following instructions can be used:

fli.s ft1, 0.0625 # dec floating-point literal fli.s ft1, 0x1p-4 # hex floating-point literal fli.s ft1, 0x0.8p-3 fli.s ft1, 0x1.0p-4 fli.s ft1, 0x2p-5 fli.s ft1, 0x4p-6 ...

As can be seen, many valid ways exist to express a floating-point value. This is realized by parsing the value operand using strtof() and comparing the parsed value against built-in float-constants that are written as hex floating-point literals.

This approach works on all machines that use IEEE 754. However, there is a chance that this fails on other machines with the following error message:

Error: improper fli value operand Error: illegal operands `fli.s ft1,0.0625

The error indicates that parsing 0x1p-4 and 0.0625 to single-precision floating point numbers will not result in two equal values on that machine.

If you encounter this problem, then please report it.

RISC-V Instruction Formats
==========================

The RISC-V Instruction Set Manual Volume I: User-Level ISA lists 15 instruction formats where some of the formats have multiple variants. For the .insn pseudo directive the assembler recognizes some of the formats. Typically, the most general variant of the instruction format is used by the .insn directive.

The following table lists the abbreviations used in the table of instruction formats:

     opcode   Unsigned immediate or opcode name for 7-bits opcode.
     opcode2   Unsigned immediate or opcode name for 2-bits opcode.
     func7   Unsigned immediate for 7-bits function code.
     func6   Unsigned immediate for 6-bits function code.
     func4   Unsigned immediate for 4-bits function code.
     func3   Unsigned immediate for 3-bits function code.
     func2   Unsigned immediate for 2-bits function code.
     rd   Destination register number for operand x, can be GPR or FPR.
     rd'   Destination register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     rs1   First source register number for operand x, can be GPR or FPR.
     rs1'   First source register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     rs2   Second source register number for operand x, can be GPR or FPR.
     rs2'   Second source register number for operand x,
     only accept s0-s1, a0-a5, fs0-fs1 and fa0-fa5.
     simm12   Sign-extended 12-bit immediate for operand x.
     simm20   Sign-extended 20-bit immediate for operand x.
     simm6   Sign-extended 6-bit immediate for operand x.
     uimm5   Unsigned 5-bit immediate for operand x.
     uimm6   Unsigned 6-bit immediate for operand x.
     uimm8   Unsigned 8-bit immediate for operand x.
     symbol   Symbol or label reference for operand x.

The following table lists all available opcode name:

C0

C1

C2
     Opcode space for compressed instructions.

LOAD
     Opcode space for load instructions.

LOAD_FP
     Opcode space for floating-point load instructions.

STORE
     Opcode space for store instructions.

STORE_FP
     Opcode space for floating-point store instructions.

AUIPC
     Opcode space for auipc instruction.

LUI
     Opcode space for lui instruction.

BRANCH
     Opcode space for branch instructions.

JAL
     Opcode space for jal instruction.

JALR
     Opcode space for jalr instruction.

OP
     Opcode space for ALU instructions.

OP_32
     Opcode space for 32-bits ALU instructions.

OP_IMM
     Opcode space for ALU with immediate instructions.

OP_IMM_32
     Opcode space for 32-bits ALU with immediate instructions.

OP_FP
     Opcode space for floating-point operation instructions.

MADD
     Opcode space for madd instruction.

MSUB
     Opcode space for msub instruction.

NMADD
     Opcode space for nmadd instruction.

NMSUB
     Opcode space for msub instruction.

AMO
     Opcode space for atomic memory operation instructions.

MISC_MEM
     Opcode space for misc instructions.

SYSTEM
     Opcode space for system instructions.

CUSTOM_0

CUSTOM_1

CUSTOM_2

CUSTOM_3
     Opcode space for customize instructions.

An instruction is two or four bytes in length and must be aligned on a 2 byte boundary. The first two bits of the instruction specify the length of the instruction, 00, 01 and 10 indicates a two byte instruction, 11 indicates a four byte instruction.

The following table lists the RISC-V instruction formats that are available with the .insn pseudo directive:

R type: .insn r opcode6, func3, func7, rd, rs1, rs2
     +-------+-----+-----+-------+----+---------+
     | func7 | rs2 | rs1 | func3 | rd | opcode6 |
     +-------+-----+-----+-------+----+---------+
     31      25    20    15      12   7        0

R type with 4 register operands: .insn r opcode6, func3, func2, rd, rs1, rs2, rs3
R4 type: .insn r4 opcode6, func3, func2, rd, rs1, rs2, rs3
     +-----+-------+-----+-----+-------+----+---------+
     | rs3 | func2 | rs2 | rs1 | func3 | rd | opcode6 |
     +-----+-------+-----+-----+-------+----+---------+
     31    27      25    20    15      12   7         0

I type: .insn i opcode6, func3, rd, rs1, simm12
I type: .insn i opcode6, func3, rd, simm12(rs1)
     +--------------+-----+-------+----+---------+
     | simm12[11:0] | rs1 | func3 | rd | opcode6 |
     +--------------+-----+-------+----+---------+
     31             20    15      12   7         0

S type: .insn s opcode6, func3, rs2, simm12(rs1)
     +--------------+-----+-----+-------+-------------+---------+
     | simm12[11:5] | rs2 | rs1 | func3 | simm12[4:0] | opcode6 |
     +--------------+-----+-----+-------+-------------+---------+
     31             25    20    15      12            7         0

B type: .insn s opcode6, func3, rs1, rs2, symbol
SB type: .insn sb opcode6, func3, rs1, rs2, symbol
     +-----------------+-----+-----+-------+----------------+---------+
     | simm12[12|10:5] | rs2 | rs1 | func3 | simm12[4:1|11] | opcode6 |
     +-----------------+-----+-----+-------+----------------+---------+
     31                25    20    15      12               7         0

U type: .insn u opcode6, rd, simm20
     +--------------------------+----+---------+
     | simm20[20|10:1|11|19:12] | rd | opcode6 |
     +--------------------------+----+---------+
     31                         12   7         0

J type: .insn j opcode6, rd, symbol
UJ type: .insn uj opcode6, rd, symbol
     +------------+--------------+------------+---------------+----+---------+
     | simm20[20] | simm20[10:1] | simm20[11] | simm20[19:12] | rd | opcode6 |
     +------------+--------------+------------+---------------+----+---------+
     31           30             21           20              12   7         0

CR type: .insn cr opcode2, func4, rd, rs2
     +-------+--------+-----+---------+
     | func4 | rd/rs1 | rs2 | opcode2 |
     +-------+--------+-----+---------+
     15      12       7     2        0

CI type: .insn ci opcode2, func3, rd, simm6
     +-------+----------+--------+------------+---------+
     | func3 | simm6[5] | rd/rs1 | simm6[4:0] | opcode2 |
     +-------+----------+--------+------------+---------+
     15      13         12       7            2         0

CIW type: .insn ciw opcode2, func3, rd', uimm8
     +-------+------------+-----+---------+
     | func3 | uimm8[7:0] | rd' | opcode2 |
     +-------+-------- ---+-----+---------+
     15      13           5     2         0

CSS type: .insn css opcode2, func3, rd, uimm6
     +-------+------------+----+---------+
     | func3 | uimm6[5:0] | rd | opcode2 |
     +-------+------------+----+---------+
     15      13           7    2         0

CL type: .insn cl opcode2, func3, rd', uimm5(rs1')
     +-------+------------+------+------------+------+---------+
     | func3 | uimm5[4:2] | rs1' | uimm5[1:0] |  rd' | opcode2 |
     +-------+------------+------+------------+------+---------+
     15      13           10     7            5      2         0

CS type: .insn cs opcode2, func3, rs2', uimm5(rs1')
     +-------+------------+------+------------+------+---------+
     | func3 | uimm5[4:2] | rs1' | uimm5[1:0] | rs2' | opcode2 |
     +-------+------------+------+------------+------+---------+
     15      13           10     7            5      2         0

CA type: .insn ca opcode2, func6, func2, rd', rs2'
     +-- ----+----------+-------+------+---------+
     | func6 | rd'/rs1' | func2 | rs2' | opcode2 |
     +-------+----------+-------+------+---------+
     15      10         7       5      2         0

CB type: .insn cb opcode2, func3, rs1', symbol
     +-------+--------------+------+------------------+---------+
     | func3 | simm8[8|4:3] | rs1' | simm8[7:6|2:1|5] | opcode2 |
     +-------+--------------+------+------------------+---------+
     15      13             10     7                  2         0

CJ type: .insn cj opcode2, symbol
     +-------+-------------------------------+---------+
     | func3 | simm11[11|4|9:8|10|6|7|3:1|5] | opcode2 |
     +-------+-------------------------------+---------+
     15      13                              2         0

For the complete list of all instruction format variants see The RISC-V Instruction Set Manual Volume I: User-Level ISA.

RISC-V Object Attribute
=======================

RISC-V attributes have a string value if the tag number is odd and an integer value if the tag number is even.

Tag_RISCV_stack_align (4)
     Tag_RISCV_strict_align records the N-byte stack alignment for this object.  The default value is 16 for RV32I or RV64I, and 4 for RV32E.

     The smallest value will be used if object files with different Tag_RISCV_stack_align values are merged.

Tag_RISCV_arch (5)
     Tag_RISCV_arch contains a string for the target architecture taken from the option -march.  Different architectures will be integrated into a superset when object files are merged.

     Note that the version information of the target architecture must be presented explicitly in the attribute and abbreviations must be expanded.  The version information, if not given by -march, must be in accordance with the default specified by the tool.  For example, the architecture RV32I has to be recorded in the attribute as RV32I2P0 in which 2P0 stands for the default version of its base ISA.  On the other hand, the architecture RV32G has to be presented as RV32I2P0_M2P0_A2P0_F2P0_D2P0 in which the abbreviation G is expanded to the IMAFD combination with default versions of the standard extensions.

Tag_RISCV_unaligned_access (6)
     Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned memory accesses, and 1 for files that do allow unaligned memory accesses.

Tag_RISCV_priv_spec (8)

Tag_RISCV_priv_spec_minor (10)

Tag_RISCV_priv_spec_revision (12)
     Tag_RISCV_priv_spec contains the major/minor/revision version information of the privileged specification.  It will report errors if object files of different privileged specification versions are merged.

RISC-V Custom (Vendor-Defined) Extensions
=========================================

The following table lists the custom (vendor-defined) RISC-V extensions supported and provides the location of their publicly-released documentation:

Xcvmac
     The Xcvmac extension provides instructions for multiply-accumulate operations.

     It is documented in https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Xcvalu
     The Xcvalu extension provides instructions for general ALU operations.

     It is documented in https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

XTheadBa
     The XTheadBa extension provides instructions for address calculations.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadBb
     The XTheadBb extension provides instructions for basic bit-manipulation

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadBs
     The XTheadBs extension provides single-bit instructions.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadCmo
     The XTheadCmo extension provides instructions for cache management.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadCondMov
     The XTheadCondMov extension provides instructions for conditional moves.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadFMemIdx
     The XTheadFMemIdx extension provides floating-point memory operations.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadFmv
     The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf.

XTheadInt
     The XTheadInt extension provides access to ISR stack management instructions.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf.

XTheadMac
     The XTheadMac extension provides multiply-accumulate instructions.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadMemIdx
     The XTheadMemIdx extension provides GPR memory operations.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadMemPair
     The XTheadMemPair extension provides two-GP-register memory operations.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadSync
     The XTheadSync extension provides instructions for multi-processor synchronization.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf.

XTheadVector
     The XTheadVector extension provides instructions for thead vector.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf.

XTheadZvamo
     The XTheadZvamo extension is a subextension of the XTheadVector extension, and it provides AMO instructions for the T-Head VECTOR vendor extension.

     It is documented in https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf.

XVentanaCondOps
     XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional bitwise-logic, and conditional select operations.

     It is documented in https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf.

XSfVcp
     The XSfVcp (VCIX) extension provides flexible instructions for extending vector coprocessor.  To accelerate performance, system designers may use VCIX as a low-latency, high-throughput interface to a coprocessor.

     It is documented in https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf.