/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Instruction Enum Values and Descriptors                             *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

namespace llvm::Lanai {

  enum {
    PHI                                   = 0, // Target.td:1200
    INLINEASM                             = 1, // Target.td:1206
    INLINEASM_BR                          = 2, // Target.td:1212
    CFI_INSTRUCTION                       = 3, // Target.td:1221
    EH_LABEL                              = 4, // Target.td:1230
    GC_LABEL                              = 5, // Target.td:1239
    ANNOTATION_LABEL                      = 6, // Target.td:1248
    KILL                                  = 7, // Target.td:1256
    EXTRACT_SUBREG                        = 8, // Target.td:1263
    INSERT_SUBREG                         = 9, // Target.td:1269
    IMPLICIT_DEF                          = 10, // Target.td:1276
    INIT_UNDEF                            = 11, // Target.td:1285
    SUBREG_TO_REG                         = 12, // Target.td:1292
    COPY_TO_REGCLASS                      = 13, // Target.td:1298
    DBG_VALUE                             = 14, // Target.td:1305
    DBG_VALUE_LIST                        = 15, // Target.td:1312
    DBG_INSTR_REF                         = 16, // Target.td:1319
    DBG_PHI                               = 17, // Target.td:1326
    DBG_LABEL                             = 18, // Target.td:1333
    REG_SEQUENCE                          = 19, // Target.td:1340
    COPY                                  = 20, // Target.td:1347
    COPY_LANEMASK                         = 21, // Target.td:1355
    BUNDLE                                = 22, // Target.td:1362
    LIFETIME_START                        = 23, // Target.td:1368
    LIFETIME_END                          = 24, // Target.td:1375
    PSEUDO_PROBE                          = 25, // Target.td:1382
    ARITH_FENCE                           = 26, // Target.td:1389
    STACKMAP                              = 27, // Target.td:1398
    FENTRY_CALL                           = 28, // Target.td:1533
    PATCHPOINT                            = 29, // Target.td:1406
    LOAD_STACK_GUARD                      = 30, // Target.td:1424
    PREALLOCATED_SETUP                    = 31, // Target.td:1432
    PREALLOCATED_ARG                      = 32, // Target.td:1438
    STATEPOINT                            = 33, // Target.td:1415
    LOCAL_ESCAPE                          = 34, // Target.td:1444
    FAULTING_OP                           = 35, // Target.td:1453
    PATCHABLE_OP                          = 36, // Target.td:1473
    PATCHABLE_FUNCTION_ENTER              = 37, // Target.td:1481
    PATCHABLE_RET                         = 38, // Target.td:1488
    PATCHABLE_FUNCTION_EXIT               = 39, // Target.td:1497
    PATCHABLE_TAIL_CALL                   = 40, // Target.td:1505
    PATCHABLE_EVENT_CALL                  = 41, // Target.td:1513
    PATCHABLE_TYPED_EVENT_CALL            = 42, // Target.td:1523
    ICALL_BRANCH_FUNNEL                   = 43, // Target.td:1543
    FAKE_USE                              = 44, // Target.td:1463
    MEMBARRIER                            = 45, // Target.td:1549
    JUMP_TABLE_DEBUG_INFO                 = 46, // Target.td:1557
    RELOC_NONE                            = 47, // Target.td:1565
    CONVERGENCECTRL_ENTRY                 = 48, // Target.td:1576
    CONVERGENCECTRL_ANCHOR                = 49, // Target.td:1572
    CONVERGENCECTRL_LOOP                  = 50, // Target.td:1580
    CONVERGENCECTRL_GLUE                  = 51, // Target.td:1584
    G_ASSERT_SEXT                         = 52, // GenericOpcodes.td:1859
    G_ASSERT_ZEXT                         = 53, // GenericOpcodes.td:1851
    G_ASSERT_ALIGN                        = 54, // GenericOpcodes.td:1866
    G_ADD                                 = 55, // GenericOpcodes.td:294
    G_SUB                                 = 56, // GenericOpcodes.td:302
    G_MUL                                 = 57, // GenericOpcodes.td:310
    G_SDIV                                = 58, // GenericOpcodes.td:318
    G_UDIV                                = 59, // GenericOpcodes.td:326
    G_SREM                                = 60, // GenericOpcodes.td:334
    G_UREM                                = 61, // GenericOpcodes.td:342
    G_SDIVREM                             = 62, // GenericOpcodes.td:350
    G_UDIVREM                             = 63, // GenericOpcodes.td:358
    G_AND                                 = 64, // GenericOpcodes.td:366
    G_OR                                  = 65, // GenericOpcodes.td:374
    G_XOR                                 = 66, // GenericOpcodes.td:382
    G_ABDS                                = 67, // GenericOpcodes.td:411
    G_ABDU                                = 68, // GenericOpcodes.td:419
    G_UAVGFLOOR                           = 69, // GenericOpcodes.td:427
    G_UAVGCEIL                            = 70, // GenericOpcodes.td:434
    G_SAVGFLOOR                           = 71, // GenericOpcodes.td:441
    G_SAVGCEIL                            = 72, // GenericOpcodes.td:448
    G_IMPLICIT_DEF                        = 73, // GenericOpcodes.td:110
    G_PHI                                 = 74, // GenericOpcodes.td:116
    G_FRAME_INDEX                         = 75, // GenericOpcodes.td:122
    G_GLOBAL_VALUE                        = 76, // GenericOpcodes.td:128
    G_PTRAUTH_GLOBAL_VALUE                = 77, // GenericOpcodes.td:134
    G_CONSTANT_POOL                       = 78, // GenericOpcodes.td:140
    G_EXTRACT                             = 79, // GenericOpcodes.td:1466
    G_UNMERGE_VALUES                      = 80, // GenericOpcodes.td:1478
    G_INSERT                              = 81, // GenericOpcodes.td:1486
    G_MERGE_VALUES                        = 82, // GenericOpcodes.td:1496
    G_BUILD_VECTOR                        = 83, // GenericOpcodes.td:1515
    G_BUILD_VECTOR_TRUNC                  = 84, // GenericOpcodes.td:1524
    G_CONCAT_VECTORS                      = 85, // GenericOpcodes.td:1531
    G_PTRTOINT                            = 86, // GenericOpcodes.td:152
    G_INTTOPTR                            = 87, // GenericOpcodes.td:146
    G_BITCAST                             = 88, // GenericOpcodes.td:158
    G_FREEZE                              = 89, // GenericOpcodes.td:271
    G_CONSTANT_FOLD_BARRIER               = 90, // GenericOpcodes.td:1873
    G_INTRINSIC_FPTRUNC_ROUND             = 91, // GenericOpcodes.td:1257
    G_INTRINSIC_TRUNC                     = 92, // GenericOpcodes.td:1263
    G_INTRINSIC_ROUND                     = 93, // GenericOpcodes.td:1269
    G_INTRINSIC_LRINT                     = 94, // GenericOpcodes.td:1275
    G_INTRINSIC_LLRINT                    = 95, // GenericOpcodes.td:1281
    G_INTRINSIC_ROUNDEVEN                 = 96, // GenericOpcodes.td:1287
    G_READCYCLECOUNTER                    = 97, // GenericOpcodes.td:1293
    G_READSTEADYCOUNTER                   = 98, // GenericOpcodes.td:1299
    G_LOAD                                = 99, // GenericOpcodes.td:1326
    G_SEXTLOAD                            = 100, // GenericOpcodes.td:1334
    G_ZEXTLOAD                            = 101, // GenericOpcodes.td:1342
    G_INDEXED_LOAD                        = 102, // GenericOpcodes.td:1352
    G_INDEXED_SEXTLOAD                    = 103, // GenericOpcodes.td:1360
    G_INDEXED_ZEXTLOAD                    = 104, // GenericOpcodes.td:1368
    G_STORE                               = 105, // GenericOpcodes.td:1376
    G_INDEXED_STORE                       = 106, // GenericOpcodes.td:1384
    G_ATOMIC_CMPXCHG_WITH_SUCCESS         = 107, // GenericOpcodes.td:1394
    G_ATOMIC_CMPXCHG                      = 108, // GenericOpcodes.td:1404
    G_ATOMICRMW_XCHG                      = 109, // GenericOpcodes.td:1422
    G_ATOMICRMW_ADD                       = 110, // GenericOpcodes.td:1423
    G_ATOMICRMW_SUB                       = 111, // GenericOpcodes.td:1424
    G_ATOMICRMW_AND                       = 112, // GenericOpcodes.td:1425
    G_ATOMICRMW_NAND                      = 113, // GenericOpcodes.td:1426
    G_ATOMICRMW_OR                        = 114, // GenericOpcodes.td:1427
    G_ATOMICRMW_XOR                       = 115, // GenericOpcodes.td:1428
    G_ATOMICRMW_MAX                       = 116, // GenericOpcodes.td:1429
    G_ATOMICRMW_MIN                       = 117, // GenericOpcodes.td:1430
    G_ATOMICRMW_UMAX                      = 118, // GenericOpcodes.td:1431
    G_ATOMICRMW_UMIN                      = 119, // GenericOpcodes.td:1432
    G_ATOMICRMW_FADD                      = 120, // GenericOpcodes.td:1433
    G_ATOMICRMW_FSUB                      = 121, // GenericOpcodes.td:1434
    G_ATOMICRMW_FMAX                      = 122, // GenericOpcodes.td:1435
    G_ATOMICRMW_FMIN                      = 123, // GenericOpcodes.td:1436
    G_ATOMICRMW_FMAXIMUM                  = 124, // GenericOpcodes.td:1437
    G_ATOMICRMW_FMINIMUM                  = 125, // GenericOpcodes.td:1438
    G_ATOMICRMW_UINC_WRAP                 = 126, // GenericOpcodes.td:1439
    G_ATOMICRMW_UDEC_WRAP                 = 127, // GenericOpcodes.td:1440
    G_ATOMICRMW_USUB_COND                 = 128, // GenericOpcodes.td:1441
    G_ATOMICRMW_USUB_SAT                  = 129, // GenericOpcodes.td:1442
    G_FENCE                               = 130, // GenericOpcodes.td:1444
    G_PREFETCH                            = 131, // GenericOpcodes.td:1451
    G_BRCOND                              = 132, // GenericOpcodes.td:1586
    G_BRINDIRECT                          = 133, // GenericOpcodes.td:1595
    G_INVOKE_REGION_START                 = 134, // GenericOpcodes.td:1618
    G_INTRINSIC                           = 135, // GenericOpcodes.td:1538
    G_INTRINSIC_W_SIDE_EFFECTS            = 136, // GenericOpcodes.td:1545
    G_INTRINSIC_CONVERGENT                = 137, // GenericOpcodes.td:1554
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 138, // GenericOpcodes.td:1562
    G_ANYEXT                              = 139, // GenericOpcodes.td:44
    G_TRUNC                               = 140, // GenericOpcodes.td:83
    G_TRUNC_SSAT_S                        = 141, // GenericOpcodes.td:90
    G_TRUNC_SSAT_U                        = 142, // GenericOpcodes.td:97
    G_TRUNC_USAT_U                        = 143, // GenericOpcodes.td:104
    G_CONSTANT                            = 144, // GenericOpcodes.td:165
    G_FCONSTANT                           = 145, // GenericOpcodes.td:172
    G_VASTART                             = 146, // GenericOpcodes.td:178
    G_VAARG                               = 147, // GenericOpcodes.td:185
    G_SEXT                                = 148, // GenericOpcodes.td:52
    G_SEXT_INREG                          = 149, // GenericOpcodes.td:66
    G_ZEXT                                = 150, // GenericOpcodes.td:74
    G_SHL                                 = 151, // GenericOpcodes.td:390
    G_LSHR                                = 152, // GenericOpcodes.td:397
    G_ASHR                                = 153, // GenericOpcodes.td:404
    G_FSHL                                = 154, // GenericOpcodes.td:456
    G_FSHR                                = 155, // GenericOpcodes.td:464
    G_ROTR                                = 156, // GenericOpcodes.td:471
    G_ROTL                                = 157, // GenericOpcodes.td:478
    G_ICMP                                = 158, // GenericOpcodes.td:485
    G_FCMP                                = 159, // GenericOpcodes.td:492
    G_SCMP                                = 160, // GenericOpcodes.td:499
    G_UCMP                                = 161, // GenericOpcodes.td:506
    G_SELECT                              = 162, // GenericOpcodes.td:513
    G_UADDO                               = 163, // GenericOpcodes.td:578
    G_UADDE                               = 164, // GenericOpcodes.td:586
    G_USUBO                               = 165, // GenericOpcodes.td:608
    G_USUBE                               = 166, // GenericOpcodes.td:614
    G_SADDO                               = 167, // GenericOpcodes.td:593
    G_SADDE                               = 168, // GenericOpcodes.td:601
    G_SSUBO                               = 169, // GenericOpcodes.td:621
    G_SSUBE                               = 170, // GenericOpcodes.td:628
    G_UMULO                               = 171, // GenericOpcodes.td:635
    G_SMULO                               = 172, // GenericOpcodes.td:643
    G_UMULH                               = 173, // GenericOpcodes.td:652
    G_SMULH                               = 174, // GenericOpcodes.td:661
    G_UADDSAT                             = 175, // GenericOpcodes.td:673
    G_SADDSAT                             = 176, // GenericOpcodes.td:681
    G_USUBSAT                             = 177, // GenericOpcodes.td:689
    G_SSUBSAT                             = 178, // GenericOpcodes.td:697
    G_USHLSAT                             = 179, // GenericOpcodes.td:705
    G_SSHLSAT                             = 180, // GenericOpcodes.td:713
    G_SMULFIX                             = 181, // GenericOpcodes.td:725
    G_UMULFIX                             = 182, // GenericOpcodes.td:732
    G_SMULFIXSAT                          = 183, // GenericOpcodes.td:742
    G_UMULFIXSAT                          = 184, // GenericOpcodes.td:749
    G_SDIVFIX                             = 185, // GenericOpcodes.td:760
    G_UDIVFIX                             = 186, // GenericOpcodes.td:767
    G_SDIVFIXSAT                          = 187, // GenericOpcodes.td:777
    G_UDIVFIXSAT                          = 188, // GenericOpcodes.td:784
    G_FADD                                = 189, // GenericOpcodes.td:957
    G_FSUB                                = 190, // GenericOpcodes.td:965
    G_FMUL                                = 191, // GenericOpcodes.td:973
    G_FMA                                 = 192, // GenericOpcodes.td:982
    G_FMAD                                = 193, // GenericOpcodes.td:991
    G_FDIV                                = 194, // GenericOpcodes.td:999
    G_FREM                                = 195, // GenericOpcodes.td:1006
    G_FMODF                               = 196, // GenericOpcodes.td:1013
    G_FPOW                                = 197, // GenericOpcodes.td:1020
    G_FPOWI                               = 198, // GenericOpcodes.td:1027
    G_FEXP                                = 199, // GenericOpcodes.td:1034
    G_FEXP2                               = 200, // GenericOpcodes.td:1041
    G_FEXP10                              = 201, // GenericOpcodes.td:1048
    G_FLOG                                = 202, // GenericOpcodes.td:1055
    G_FLOG2                               = 203, // GenericOpcodes.td:1062
    G_FLOG10                              = 204, // GenericOpcodes.td:1069
    G_FLDEXP                              = 205, // GenericOpcodes.td:1076
    G_FFREXP                              = 206, // GenericOpcodes.td:1083
    G_FNEG                                = 207, // GenericOpcodes.td:795
    G_FPEXT                               = 208, // GenericOpcodes.td:801
    G_FPTRUNC                             = 209, // GenericOpcodes.td:807
    G_FPTOSI                              = 210, // GenericOpcodes.td:813
    G_FPTOUI                              = 211, // GenericOpcodes.td:819
    G_SITOFP                              = 212, // GenericOpcodes.td:825
    G_UITOFP                              = 213, // GenericOpcodes.td:831
    G_FPTOSI_SAT                          = 214, // GenericOpcodes.td:837
    G_FPTOUI_SAT                          = 215, // GenericOpcodes.td:843
    G_FABS                                = 216, // GenericOpcodes.td:849
    G_FCOPYSIGN                           = 217, // GenericOpcodes.td:855
    G_IS_FPCLASS                          = 218, // GenericOpcodes.td:868
    G_FCANONICALIZE                       = 219, // GenericOpcodes.td:861
    G_FMINNUM                             = 220, // GenericOpcodes.td:881
    G_FMAXNUM                             = 221, // GenericOpcodes.td:888
    G_FMINNUM_IEEE                        = 222, // GenericOpcodes.td:906
    G_FMAXNUM_IEEE                        = 223, // GenericOpcodes.td:913
    G_FMINIMUM                            = 224, // GenericOpcodes.td:923
    G_FMAXIMUM                            = 225, // GenericOpcodes.td:930
    G_FMINIMUMNUM                         = 226, // GenericOpcodes.td:938
    G_FMAXIMUMNUM                         = 227, // GenericOpcodes.td:945
    G_GET_FPENV                           = 228, // GenericOpcodes.td:1213
    G_SET_FPENV                           = 229, // GenericOpcodes.td:1220
    G_RESET_FPENV                         = 230, // GenericOpcodes.td:1227
    G_GET_FPMODE                          = 231, // GenericOpcodes.td:1234
    G_SET_FPMODE                          = 232, // GenericOpcodes.td:1241
    G_RESET_FPMODE                        = 233, // GenericOpcodes.td:1248
    G_GET_ROUNDING                        = 234, // GenericOpcodes.td:1305
    G_SET_ROUNDING                        = 235, // GenericOpcodes.td:1311
    G_PTR_ADD                             = 236, // GenericOpcodes.td:520
    G_PTRMASK                             = 237, // GenericOpcodes.td:528
    G_SMIN                                = 238, // GenericOpcodes.td:535
    G_SMAX                                = 239, // GenericOpcodes.td:543
    G_UMIN                                = 240, // GenericOpcodes.td:551
    G_UMAX                                = 241, // GenericOpcodes.td:559
    G_ABS                                 = 242, // GenericOpcodes.td:567
    G_LROUND                              = 243, // GenericOpcodes.td:277
    G_LLROUND                             = 244, // GenericOpcodes.td:283
    G_BR                                  = 245, // GenericOpcodes.td:1576
    G_BRJT                                = 246, // GenericOpcodes.td:1606
    G_VSCALE                              = 247, // GenericOpcodes.td:1506
    G_INSERT_SUBVECTOR                    = 248, // GenericOpcodes.td:1650
    G_EXTRACT_SUBVECTOR                   = 249, // GenericOpcodes.td:1657
    G_INSERT_VECTOR_ELT                   = 250, // GenericOpcodes.td:1664
    G_EXTRACT_VECTOR_ELT                  = 251, // GenericOpcodes.td:1671
    G_SHUFFLE_VECTOR                      = 252, // GenericOpcodes.td:1681
    G_SPLAT_VECTOR                        = 253, // GenericOpcodes.td:1688
    G_STEP_VECTOR                         = 254, // GenericOpcodes.td:1695
    G_VECTOR_COMPRESS                     = 255, // GenericOpcodes.td:1702
    G_CTTZ                                = 256, // GenericOpcodes.td:205
    G_CTTZ_ZERO_UNDEF                     = 257, // GenericOpcodes.td:211
    G_CTLZ                                = 258, // GenericOpcodes.td:193
    G_CTLZ_ZERO_UNDEF                     = 259, // GenericOpcodes.td:199
    G_CTPOP                               = 260, // GenericOpcodes.td:217
    G_BSWAP                               = 261, // GenericOpcodes.td:223
    G_BITREVERSE                          = 262, // GenericOpcodes.td:229
    G_FCEIL                               = 263, // GenericOpcodes.td:1090
    G_FCOS                                = 264, // GenericOpcodes.td:1097
    G_FSIN                                = 265, // GenericOpcodes.td:1104
    G_FSINCOS                             = 266, // GenericOpcodes.td:1111
    G_FTAN                                = 267, // GenericOpcodes.td:1118
    G_FACOS                               = 268, // GenericOpcodes.td:1125
    G_FASIN                               = 269, // GenericOpcodes.td:1132
    G_FATAN                               = 270, // GenericOpcodes.td:1139
    G_FATAN2                              = 271, // GenericOpcodes.td:1146
    G_FCOSH                               = 272, // GenericOpcodes.td:1153
    G_FSINH                               = 273, // GenericOpcodes.td:1160
    G_FTANH                               = 274, // GenericOpcodes.td:1167
    G_FSQRT                               = 275, // GenericOpcodes.td:1177
    G_FFLOOR                              = 276, // GenericOpcodes.td:1184
    G_FRINT                               = 277, // GenericOpcodes.td:1191
    G_FNEARBYINT                          = 278, // GenericOpcodes.td:1198
    G_ADDRSPACE_CAST                      = 279, // GenericOpcodes.td:235
    G_BLOCK_ADDR                          = 280, // GenericOpcodes.td:241
    G_JUMP_TABLE                          = 281, // GenericOpcodes.td:247
    G_DYN_STACKALLOC                      = 282, // GenericOpcodes.td:253
    G_STACKSAVE                           = 283, // GenericOpcodes.td:259
    G_STACKRESTORE                        = 284, // GenericOpcodes.td:265
    G_STRICT_FADD                         = 285, // GenericOpcodes.td:1752
    G_STRICT_FSUB                         = 286, // GenericOpcodes.td:1753
    G_STRICT_FMUL                         = 287, // GenericOpcodes.td:1754
    G_STRICT_FDIV                         = 288, // GenericOpcodes.td:1755
    G_STRICT_FREM                         = 289, // GenericOpcodes.td:1756
    G_STRICT_FMA                          = 290, // GenericOpcodes.td:1757
    G_STRICT_FSQRT                        = 291, // GenericOpcodes.td:1758
    G_STRICT_FLDEXP                       = 292, // GenericOpcodes.td:1759
    G_READ_REGISTER                       = 293, // GenericOpcodes.td:1625
    G_WRITE_REGISTER                      = 294, // GenericOpcodes.td:1635
    G_MEMCPY                              = 295, // GenericOpcodes.td:1765
    G_MEMCPY_INLINE                       = 296, // GenericOpcodes.td:1773
    G_MEMMOVE                             = 297, // GenericOpcodes.td:1781
    G_MEMSET                              = 298, // GenericOpcodes.td:1789
    G_BZERO                               = 299, // GenericOpcodes.td:1796
    G_TRAP                                = 300, // GenericOpcodes.td:1806
    G_DEBUGTRAP                           = 301, // GenericOpcodes.td:1813
    G_UBSANTRAP                           = 302, // GenericOpcodes.td:1819
    G_VECREDUCE_SEQ_FADD                  = 303, // GenericOpcodes.td:1718
    G_VECREDUCE_SEQ_FMUL                  = 304, // GenericOpcodes.td:1724
    G_VECREDUCE_FADD                      = 305, // GenericOpcodes.td:1730
    G_VECREDUCE_FMUL                      = 306, // GenericOpcodes.td:1731
    G_VECREDUCE_FMAX                      = 307, // GenericOpcodes.td:1733
    G_VECREDUCE_FMIN                      = 308, // GenericOpcodes.td:1734
    G_VECREDUCE_FMAXIMUM                  = 309, // GenericOpcodes.td:1735
    G_VECREDUCE_FMINIMUM                  = 310, // GenericOpcodes.td:1736
    G_VECREDUCE_ADD                       = 311, // GenericOpcodes.td:1738
    G_VECREDUCE_MUL                       = 312, // GenericOpcodes.td:1739
    G_VECREDUCE_AND                       = 313, // GenericOpcodes.td:1740
    G_VECREDUCE_OR                        = 314, // GenericOpcodes.td:1741
    G_VECREDUCE_XOR                       = 315, // GenericOpcodes.td:1742
    G_VECREDUCE_SMAX                      = 316, // GenericOpcodes.td:1743
    G_VECREDUCE_SMIN                      = 317, // GenericOpcodes.td:1744
    G_VECREDUCE_UMAX                      = 318, // GenericOpcodes.td:1745
    G_VECREDUCE_UMIN                      = 319, // GenericOpcodes.td:1746
    G_SBFX                                = 320, // GenericOpcodes.td:1831
    G_UBFX                                = 321, // GenericOpcodes.td:1839
    ADJCALLSTACKDOWN                      = 322, // LanaiInstrInfo.td:753
    ADJCALLSTACKUP                        = 323, // LanaiInstrInfo.td:756
    ADJDYNALLOC                           = 324, // LanaiInstrInfo.td:762
    CALL                                  = 325, // LanaiInstrInfo.td:727
    CALLR                                 = 326, // LanaiInstrInfo.td:728
    ADDC_F_I_HI                           = 327, // LanaiInstrInfo.td:281
    ADDC_F_I_LO                           = 328, // LanaiInstrInfo.td:277
    ADDC_F_R                              = 329, // LanaiInstrInfo.td:293
    ADDC_I_HI                             = 330, // LanaiInstrInfo.td:281
    ADDC_I_LO                             = 331, // LanaiInstrInfo.td:277
    ADDC_R                                = 332, // LanaiInstrInfo.td:293
    ADD_F_I_HI                            = 333, // LanaiInstrInfo.td:281
    ADD_F_I_LO                            = 334, // LanaiInstrInfo.td:277
    ADD_F_R                               = 335, // LanaiInstrInfo.td:293
    ADD_I_HI                              = 336, // LanaiInstrInfo.td:281
    ADD_I_LO                              = 337, // LanaiInstrInfo.td:277
    ADD_R                                 = 338, // LanaiInstrInfo.td:293
    AND_F_I_HI                            = 339, // LanaiInstrInfo.td:281
    AND_F_I_LO                            = 340, // LanaiInstrInfo.td:277
    AND_F_R                               = 341, // LanaiInstrInfo.td:306
    AND_I_HI                              = 342, // LanaiInstrInfo.td:281
    AND_I_LO                              = 343, // LanaiInstrInfo.td:277
    AND_R                                 = 344, // LanaiInstrInfo.td:306
    BRCC                                  = 345, // LanaiInstrInfo.td:685
    BRIND_CC                              = 346, // LanaiInstrInfo.td:788
    BRIND_CCA                             = 347, // LanaiInstrInfo.td:796
    BRR                                   = 348, // LanaiInstrInfo.td:808
    BT                                    = 349, // LanaiInstrInfo.td:679
    JR                                    = 350, // LanaiInstrInfo.td:690
    LDADDR                                = 351, // LanaiInstrInfo.td:542
    LDBs_RI                               = 352, // LanaiInstrInfo.td:580
    LDBs_RR                               = 353, // LanaiInstrInfo.td:539
    LDBz_RI                               = 354, // LanaiInstrInfo.td:577
    LDBz_RR                               = 355, // LanaiInstrInfo.td:532
    LDHs_RI                               = 356, // LanaiInstrInfo.td:574
    LDHs_RR                               = 357, // LanaiInstrInfo.td:537
    LDHz_RI                               = 358, // LanaiInstrInfo.td:571
    LDHz_RR                               = 359, // LanaiInstrInfo.td:530
    LDW_RI                                = 360, // LanaiInstrInfo.td:515
    LDW_RR                                = 361, // LanaiInstrInfo.td:516
    LDWz_RR                               = 362, // LanaiInstrInfo.td:524
    LEADZ                                 = 363, // LanaiInstrInfo.td:818
    LOG0                                  = 364, // LanaiInstrInfo.td:249
    LOG1                                  = 365, // LanaiInstrInfo.td:251
    LOG2                                  = 366, // LanaiInstrInfo.td:253
    LOG3                                  = 367, // LanaiInstrInfo.td:255
    LOG4                                  = 368, // LanaiInstrInfo.td:257
    MOVHI                                 = 369, // LanaiInstrInfo.td:408
    NOP                                   = 370, // LanaiInstrInfo.td:245
    OR_F_I_HI                             = 371, // LanaiInstrInfo.td:281
    OR_F_I_LO                             = 372, // LanaiInstrInfo.td:277
    OR_F_R                                = 373, // LanaiInstrInfo.td:306
    OR_I_HI                               = 374, // LanaiInstrInfo.td:281
    OR_I_LO                               = 375, // LanaiInstrInfo.td:277
    OR_R                                  = 376, // LanaiInstrInfo.td:306
    POPC                                  = 377, // LanaiInstrInfo.td:813
    RET                                   = 378, // LanaiInstrInfo.td:733
    SA_F_I                                = 379, // LanaiInstrInfo.td:439
    SA_I                                  = 380, // LanaiInstrInfo.td:430
    SCC                                   = 381, // LanaiInstrInfo.td:768
    SELECT                                = 382, // LanaiInstrInfo.td:775
    SFSUB_F_RI_HI                         = 383, // LanaiInstrInfo.td:716
    SFSUB_F_RI_LO                         = 384, // LanaiInstrInfo.td:712
    SFSUB_F_RR                            = 385, // LanaiInstrInfo.td:708
    SHL_F_R                               = 386, // LanaiInstrInfo.td:460
    SHL_R                                 = 387, // LanaiInstrInfo.td:448
    SLI                                   = 388, // LanaiInstrInfo.td:582
    SL_F_I                                = 389, // LanaiInstrInfo.td:437
    SL_I                                  = 390, // LanaiInstrInfo.td:428
    SRA_F_R                               = 391, // LanaiInstrInfo.td:466
    SRA_R                                 = 392, // LanaiInstrInfo.td:455
    SRL_F_R                               = 393, // LanaiInstrInfo.td:463
    SRL_R                                 = 394, // LanaiInstrInfo.td:452
    STADDR                                = 395, // LanaiInstrInfo.td:641
    STB_RI                                = 396, // LanaiInstrInfo.td:672
    STB_RR                                = 397, // LanaiInstrInfo.td:638
    STH_RI                                = 398, // LanaiInstrInfo.td:669
    STH_RR                                = 399, // LanaiInstrInfo.td:636
    SUBB_F_I_HI                           = 400, // LanaiInstrInfo.td:281
    SUBB_F_I_LO                           = 401, // LanaiInstrInfo.td:277
    SUBB_F_R                              = 402, // LanaiInstrInfo.td:293
    SUBB_I_HI                             = 403, // LanaiInstrInfo.td:281
    SUBB_I_LO                             = 404, // LanaiInstrInfo.td:277
    SUBB_R                                = 405, // LanaiInstrInfo.td:293
    SUB_F_I_HI                            = 406, // LanaiInstrInfo.td:281
    SUB_F_I_LO                            = 407, // LanaiInstrInfo.td:277
    SUB_F_R                               = 408, // LanaiInstrInfo.td:293
    SUB_I_HI                              = 409, // LanaiInstrInfo.td:281
    SUB_I_LO                              = 410, // LanaiInstrInfo.td:277
    SUB_R                                 = 411, // LanaiInstrInfo.td:293
    SW_RI                                 = 412, // LanaiInstrInfo.td:631
    SW_RR                                 = 413, // LanaiInstrInfo.td:630
    TRAILZ                                = 414, // LanaiInstrInfo.td:822
    XOR_F_I_HI                            = 415, // LanaiInstrInfo.td:281
    XOR_F_I_LO                            = 416, // LanaiInstrInfo.td:277
    XOR_F_R                               = 417, // LanaiInstrInfo.td:306
    XOR_I_HI                              = 418, // LanaiInstrInfo.td:281
    XOR_I_LO                              = 419, // LanaiInstrInfo.td:277
    XOR_R                                 = 420, // LanaiInstrInfo.td:306
    INSTRUCTION_LIST_END = 421
  };

} // namespace llvm::Lanai

#endif // GET_INSTRINFO_ENUM

#ifdef GET_INSTRINFO_SCHED_ENUM
#undef GET_INSTRINFO_SCHED_ENUM

namespace llvm::Lanai::Sched {

  enum {
    NoInstrModel	= 0,
    IIC_ALU_WriteALU	= 1,
    IIC_ALU	= 2,
    IIC_LD_WriteLD	= 3,
    IIC_LDSW_WriteLDSW	= 4,
    WriteLD	= 5,
    IIC_ST_WriteST	= 6,
    IIC_STSW_WriteSTSW	= 7,
    SCHED_LIST_END = 8
  };

} // namespace llvm::Lanai::Sched

#endif // GET_INSTRINFO_SCHED_ENUM

#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

namespace llvm {

struct LanaiInstrTable {
  MCInstrDesc Insts[421];
  static_assert(alignof(MCInstrDesc) >= alignof(MCPhysReg), "Unwanted padding between Insts and ImplicitOps");
  MCPhysReg ImplicitOps[8];
  char Padding[sizeof(MCOperandInfo) - sizeof ImplicitOps % sizeof(MCOperandInfo)];
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
  MCOperandInfo OperandInfo[178];
};
} // namespace llvm

#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)

#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

namespace llvm {

static_assert((sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) % sizeof(MCOperandInfo) == 0);
static constexpr unsigned LanaiOpInfoBase = (sizeof LanaiInstrTable::ImplicitOps + sizeof LanaiInstrTable::Padding) / sizeof(MCOperandInfo);

extern const LanaiInstrTable LanaiDescs = {
  {
    { 420,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_R
    { 419,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_I_LO
    { 418,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_I_HI
    { 417,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_F_R
    { 416,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_F_I_LO
    { 415,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // XOR_F_I_HI
    { 414,	2,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 155,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // TRAILZ
    { 413,	4,	0,	4,	6,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SW_RR
    { 412,	4,	0,	4,	6,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SW_RI
    { 411,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_R
    { 410,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_I_LO
    { 409,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_I_HI
    { 408,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_F_R
    { 407,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_F_I_LO
    { 406,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUB_F_I_HI
    { 405,	4,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_R
    { 404,	3,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_I_LO
    { 403,	3,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_I_HI
    { 402,	4,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 160,	4,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_F_R
    { 401,	3,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 157,	4,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_F_I_LO
    { 400,	3,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 157,	4,	0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBB_F_I_HI
    { 399,	4,	0,	4,	6,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STH_RR
    { 398,	4,	0,	4,	7,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STH_RI
    { 397,	4,	0,	4,	6,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STB_RR
    { 396,	4,	0,	4,	7,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STB_RI
    { 395,	2,	0,	4,	6,	0,	0,	LanaiOpInfoBase + 38,	0,	0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STADDR
    { 394,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SRL_R
    { 393,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SRL_F_R
    { 392,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SRA_R
    { 391,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SRA_F_R
    { 390,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SL_I
    { 389,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SL_F_I
    { 388,	2,	1,	4,	0,	0,	0,	LanaiOpInfoBase + 38,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SLI
    { 387,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SHL_R
    { 386,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SHL_F_R
    { 385,	2,	0,	4,	1,	0,	1,	LanaiOpInfoBase + 155,	6,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SFSUB_F_RR
    { 384,	2,	0,	4,	1,	0,	1,	LanaiOpInfoBase + 38,	6,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SFSUB_F_RI_LO
    { 383,	2,	0,	4,	1,	0,	1,	LanaiOpInfoBase + 38,	6,	0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SFSUB_F_RI_HI
    { 382,	4,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 174,	6,	0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SELECT
    { 381,	2,	1,	4,	2,	1,	0,	LanaiOpInfoBase + 38,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SCC
    { 380,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SA_I
    { 379,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SA_F_I
    { 378,	0,	0,	4,	0,	1,	0,	LanaiOpInfoBase + 1,	7,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RET
    { 377,	2,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 155,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // POPC
    { 376,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_R
    { 375,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_I_LO
    { 374,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_I_HI
    { 373,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_F_R
    { 372,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_F_I_LO
    { 371,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // OR_F_I_HI
    { 370,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // NOP
    { 369,	2,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 38,	0,	0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MOVHI
    { 368,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOG4
    { 367,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOG3
    { 366,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOG2
    { 365,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOG1
    { 364,	0,	0,	4,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOG0
    { 363,	2,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 155,	0,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LEADZ
    { 362,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDWz_RR
    { 361,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDW_RR
    { 360,	4,	1,	4,	3,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDW_RI
    { 359,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDHz_RR
    { 358,	4,	1,	4,	4,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDHz_RI
    { 357,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDHs_RR
    { 356,	4,	1,	4,	4,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDHs_RI
    { 355,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDBz_RR
    { 354,	4,	1,	4,	4,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDBz_RI
    { 353,	4,	1,	4,	5,	0,	0,	LanaiOpInfoBase + 170,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDBs_RR
    { 352,	4,	1,	4,	4,	0,	0,	LanaiOpInfoBase + 166,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDBs_RI
    { 351,	2,	1,	4,	3,	0,	0,	LanaiOpInfoBase + 38,	0,	0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LDADDR
    { 350,	1,	0,	4,	1,	0,	0,	LanaiOpInfoBase + 32,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // JR
    { 349,	1,	0,	4,	2,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BT
    { 348,	2,	0,	4,	0,	1,	0,	LanaiOpInfoBase + 164,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRR
    { 347,	3,	0,	4,	1,	1,	0,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRIND_CCA
    { 346,	2,	0,	4,	1,	1,	0,	LanaiOpInfoBase + 38,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRIND_CC
    { 345,	2,	0,	4,	2,	1,	0,	LanaiOpInfoBase + 13,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BRCC
    { 344,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_R
    { 343,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_I_LO
    { 342,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_I_HI
    { 341,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_F_R
    { 340,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_F_I_LO
    { 339,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // AND_F_I_HI
    { 338,	4,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 160,	0,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_R
    { 337,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_I_LO
    { 336,	3,	1,	4,	1,	0,	0,	LanaiOpInfoBase + 157,	0,	0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_I_HI
    { 335,	4,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_F_R
    { 334,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_F_I_LO
    { 333,	3,	1,	4,	1,	0,	1,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADD_F_I_HI
    { 332,	4,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 160,	6,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_R
    { 331,	3,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_I_LO
    { 330,	3,	1,	4,	1,	1,	0,	LanaiOpInfoBase + 157,	6,	0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_I_HI
    { 329,	4,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 160,	4,	0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_F_R
    { 328,	3,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 157,	4,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_F_I_LO
    { 327,	3,	1,	4,	1,	1,	1,	LanaiOpInfoBase + 157,	4,	0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADDC_F_I_HI
    { 326,	1,	0,	4,	0,	1,	1,	LanaiOpInfoBase + 32,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CALLR
    { 325,	1,	0,	4,	0,	1,	1,	LanaiOpInfoBase + 0,	2,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CALL
    { 324,	2,	1,	4,	0,	1,	1,	LanaiOpInfoBase + 155,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADJDYNALLOC
    { 323,	2,	0,	4,	0,	1,	1,	LanaiOpInfoBase + 24,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADJCALLSTACKUP
    { 322,	2,	0,	4,	0,	1,	1,	LanaiOpInfoBase + 24,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ADJCALLSTACKDOWN
    { 321,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UBFX
    { 320,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 151,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SBFX
    { 319,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_UMIN
    { 318,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_UMAX
    { 317,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SMIN
    { 316,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SMAX
    { 315,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_XOR
    { 314,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_OR
    { 313,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_AND
    { 312,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_MUL
    { 311,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_ADD
    { 310,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMINIMUM
    { 309,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMAXIMUM
    { 308,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMIN
    { 307,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMAX
    { 306,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FMUL
    { 305,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_FADD
    { 304,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SEQ_FMUL
    { 303,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECREDUCE_SEQ_FADD
    { 302,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UBSANTRAP
    { 301,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_DEBUGTRAP
    { 300,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRAP
    { 299,	3,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BZERO
    { 298,	4,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMSET
    { 297,	4,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMMOVE
    { 296,	3,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMCPY_INLINE
    { 295,	4,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 147,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MEMCPY
    { 294,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 145,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_WRITE_REGISTER
    { 293,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_READ_REGISTER
    { 292,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FLDEXP
    { 291,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FSQRT
    { 290,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FMA
    { 289,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FREM
    { 288,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FDIV
    { 287,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FMUL
    { 286,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FSUB
    { 285,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STRICT_FADD
    { 284,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STACKRESTORE
    { 283,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STACKSAVE
    { 282,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_DYN_STACKALLOC
    { 281,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_JUMP_TABLE
    { 280,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BLOCK_ADDR
    { 279,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ADDRSPACE_CAST
    { 278,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FNEARBYINT
    { 277,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FRINT
    { 276,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FFLOOR
    { 275,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSQRT
    { 274,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FTANH
    { 273,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSINH
    { 272,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOSH
    { 271,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FATAN2
    { 270,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FATAN
    { 269,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FASIN
    { 268,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FACOS
    { 267,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FTAN
    { 266,	3,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSINCOS
    { 265,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSIN
    { 264,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOS
    { 263,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCEIL
    { 262,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BITREVERSE
    { 261,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BSWAP
    { 260,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTPOP
    { 259,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTLZ_ZERO_UNDEF
    { 258,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTLZ
    { 257,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTTZ_ZERO_UNDEF
    { 256,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CTTZ
    { 255,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 141,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VECTOR_COMPRESS
    { 254,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STEP_VECTOR
    { 253,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SPLAT_VECTOR
    { 252,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 137,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SHUFFLE_VECTOR
    { 251,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 134,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT_VECTOR_ELT
    { 250,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 130,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT_VECTOR_ELT
    { 249,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT_SUBVECTOR
    { 248,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT_SUBVECTOR
    { 247,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VSCALE
    { 246,	3,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 127,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRJT
    { 245,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BR
    { 244,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LLROUND
    { 243,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LROUND
    { 242,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABS
    { 241,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMAX
    { 240,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMIN
    { 239,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMAX
    { 238,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMIN
    { 237,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRMASK
    { 236,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTR_ADD
    { 235,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_ROUNDING
    { 234,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_ROUNDING
    { 233,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_RESET_FPMODE
    { 232,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_FPMODE
    { 231,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_FPMODE
    { 230,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_RESET_FPENV
    { 229,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SET_FPENV
    { 228,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GET_FPENV
    { 227,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXIMUMNUM
    { 226,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINIMUMNUM
    { 225,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXIMUM
    { 224,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINIMUM
    { 223,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXNUM_IEEE
    { 222,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINNUM_IEEE
    { 221,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAXNUM
    { 220,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMINNUM
    { 219,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCANONICALIZE
    { 218,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_IS_FPCLASS
    { 217,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCOPYSIGN
    { 216,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FABS
    { 215,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOUI_SAT
    { 214,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOSI_SAT
    { 213,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UITOFP
    { 212,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SITOFP
    { 211,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOUI
    { 210,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTOSI
    { 209,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPTRUNC
    { 208,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPEXT
    { 207,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FNEG
    { 206,	3,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FFREXP
    { 205,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLDEXP
    { 204,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG10
    { 203,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG2
    { 202,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FLOG
    { 201,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP10
    { 200,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP2
    { 199,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FEXP
    { 198,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPOWI
    { 197,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FPOW
    { 196,	3,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMODF
    { 195,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FREM
    { 194,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FDIV
    { 193,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMAD
    { 192,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMA
    { 191,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FMUL
    { 190,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSUB
    { 189,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FADD
    { 188,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVFIXSAT
    { 187,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVFIXSAT
    { 186,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVFIX
    { 185,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVFIX
    { 184,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULFIXSAT
    { 183,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULFIXSAT
    { 182,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULFIX
    { 181,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 123,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULFIX
    { 180,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSHLSAT
    { 179,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USHLSAT
    { 178,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBSAT
    { 177,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBSAT
    { 176,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDSAT
    { 175,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDSAT
    { 174,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULH
    { 173,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULH
    { 172,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SMULO
    { 171,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UMULO
    { 170,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBE
    { 169,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SSUBO
    { 168,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDE
    { 167,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SADDO
    { 166,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBE
    { 165,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_USUBO
    { 164,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 118,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDE
    { 163,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UADDO
    { 162,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SELECT
    { 161,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UCMP
    { 160,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 115,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SCMP
    { 159,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCMP
    { 158,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 111,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ICMP
    { 157,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ROTL
    { 156,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ROTR
    { 155,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSHR
    { 154,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 107,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FSHL
    { 153,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASHR
    { 152,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LSHR
    { 151,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 104,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SHL
    { 150,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ZEXT
    { 149,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXT_INREG
    { 148,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXT
    { 147,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 101,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VAARG
    { 146,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_VASTART
    { 145,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FCONSTANT
    { 144,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT
    { 143,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_USAT_U
    { 142,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_SSAT_U
    { 141,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC_SSAT_S
    { 140,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_TRUNC
    { 139,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ANYEXT
    { 138,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    { 137,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // G_INTRINSIC_CONVERGENT
    { 136,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_W_SIDE_EFFECTS
    { 135,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC
    { 134,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INVOKE_REGION_START
    { 133,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRINDIRECT
    { 132,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BRCOND
    { 131,	4,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 97,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PREFETCH
    { 130,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 24,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FENCE
    { 129,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_USUB_SAT
    { 128,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_USUB_COND
    { 127,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UDEC_WRAP
    { 126,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UINC_WRAP
    { 125,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMINIMUM
    { 124,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMAXIMUM
    { 123,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMIN
    { 122,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FMAX
    { 121,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FSUB
    { 120,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_FADD
    { 119,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UMIN
    { 118,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_UMAX
    { 117,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_MIN
    { 116,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_MAX
    { 115,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_XOR
    { 114,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_OR
    { 113,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_NAND
    { 112,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_AND
    { 111,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_SUB
    { 110,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_ADD
    { 109,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 94,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMICRMW_XCHG
    { 108,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 90,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMIC_CMPXCHG
    { 107,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 85,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    { 106,	5,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 80,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_STORE
    { 105,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_STORE
    { 104,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_ZEXTLOAD
    { 103,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_SEXTLOAD
    { 102,	5,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 75,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INDEXED_LOAD
    { 101,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ZEXTLOAD
    { 100,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SEXTLOAD
    { 99,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_LOAD
    { 98,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_READSTEADYCOUNTER
    { 97,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_READCYCLECOUNTER
    { 96,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_ROUNDEVEN
    { 95,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_LLRINT
    { 94,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_LRINT
    { 93,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_ROUND
    { 92,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_TRUNC
    { 91,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 72,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTRINSIC_FPTRUNC_ROUND
    { 90,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT_FOLD_BARRIER
    { 89,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 70,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FREEZE
    { 88,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BITCAST
    { 87,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INTTOPTR
    { 86,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRTOINT
    { 85,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONCAT_VECTORS
    { 84,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BUILD_VECTOR_TRUNC
    { 83,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_BUILD_VECTOR
    { 82,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MERGE_VALUES
    { 81,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 66,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_INSERT
    { 80,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 64,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UNMERGE_VALUES
    { 79,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 61,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_EXTRACT
    { 78,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_CONSTANT_POOL
    { 77,	5,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 56,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PTRAUTH_GLOBAL_VALUE
    { 76,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_GLOBAL_VALUE
    { 75,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 54,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_FRAME_INDEX
    { 74,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_PHI
    { 73,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 53,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_IMPLICIT_DEF
    { 72,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SAVGCEIL
    { 71,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SAVGFLOOR
    { 70,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UAVGCEIL
    { 69,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UAVGFLOOR
    { 68,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABDU
    { 67,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ABDS
    { 66,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_XOR
    { 65,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_OR
    { 64,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_AND
    { 63,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIVREM
    { 62,	4,	2,	0,	0,	0,	0,	LanaiOpInfoBase + 49,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIVREM
    { 61,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UREM
    { 60,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SREM
    { 59,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_UDIV
    { 58,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SDIV
    { 57,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_MUL
    { 56,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_SUB
    { 55,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 46,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ADD
    { 54,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_ALIGN
    { 53,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_ZEXT
    { 52,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 43,	0,	0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // G_ASSERT_SEXT
    { 51,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_GLUE
    { 50,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_LOOP
    { 49,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ANCHOR
    { 48,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // CONVERGENCECTRL_ENTRY
    { 47,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // RELOC_NONE
    { 46,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // JUMP_TABLE_DEBUG_INFO
    { 45,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // MEMBARRIER
    { 44,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FAKE_USE
    { 43,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ICALL_BRANCH_FUNNEL
    { 42,	3,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 40,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14555
    { 41,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 38,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14554
    { 40,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_TAIL_CALL
    { 39,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_FUNCTION_EXIT
    { 38,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_RET
    { 37,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_FUNCTION_ENTER
    { 36,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHABLE_OP
    { 35,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FAULTING_OP
    { 34,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 36,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LOCAL_ESCAPE
    { 33,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STATEPOINT
    { 32,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 33,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14553
    { 31,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PREALLOCATED_SETUP
    { 30,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 32,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // anonymous_14196
    { 29,	6,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 26,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PATCHPOINT
    { 28,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // FENTRY_CALL
    { 27,	2,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 24,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // STACKMAP
    { 26,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 22,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ARITH_FENCE
    { 25,	4,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 18,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PSEUDO_PROBE
    { 24,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LIFETIME_END
    { 23,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // LIFETIME_START
    { 22,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // BUNDLE
    { 21,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 15,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY_LANEMASK
    { 20,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY
    { 19,	2,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 13,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // REG_SEQUENCE
    { 18,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_LABEL
    { 17,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_PHI
    { 16,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_INSTR_REF
    { 15,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_VALUE_LIST
    { 14,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // DBG_VALUE
    { 13,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // COPY_TO_REGCLASS
    { 12,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 9,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // SUBREG_TO_REG
    { 11,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INIT_UNDEF
    { 10,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // IMPLICIT_DEF
    { 9,	4,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 5,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INSERT_SUBREG
    { 8,	3,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 2,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EXTRACT_SUBREG
    { 7,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // KILL
    { 6,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // ANNOTATION_LABEL
    { 5,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // GC_LABEL
    { 4,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // EH_LABEL
    { 3,	1,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // CFI_INSTRUCTION
    { 2,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INLINEASM_BR
    { 1,	0,	0,	0,	0,	0,	0,	LanaiOpInfoBase + 1,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // INLINEASM
    { 0,	1,	1,	0,	0,	0,	0,	LanaiOpInfoBase + 0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // PHI
  }, {
    /* 0 */
    /* 0 */ Lanai::SP, Lanai::SP,
    /* 2 */ Lanai::SP, Lanai::RCA,
    /* 4 */ Lanai::SR, Lanai::SR,
    /* 6 */ Lanai::SR,
    /* 7 */ Lanai::RCA,
  }, {
    0
  }, {
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 1 */
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 15 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 18 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 22 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
    /* 24 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 26 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 32 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 33 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 36 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 38 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 40 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 49 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 54 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 61 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 66 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 70 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 75 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 80 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 85 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 90 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 94 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 97 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
    /* 101 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 104 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 111 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 115 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 118 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 127 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 130 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 134 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
    /* 137 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 141 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 145 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
    /* 147 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
    /* 151 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
    /* 155 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
    /* 157 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 160 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
    /* 164 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 166 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 170 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
    /* 174 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
  }
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char LanaiInstrNameData[] = {
  /* 0 */ "G_FLOG10\000"
  /* 9 */ "G_FEXP10\000"
  /* 18 */ "LOG0\000"
  /* 23 */ "LOG1\000"
  /* 28 */ "G_FLOG2\000"
  /* 36 */ "G_FATAN2\000"
  /* 45 */ "G_FEXP2\000"
  /* 53 */ "LOG3\000"
  /* 58 */ "LOG4\000"
  /* 63 */ "BRIND_CCA\000"
  /* 73 */ "G_FMA\000"
  /* 79 */ "G_STRICT_FMA\000"
  /* 92 */ "G_FSUB\000"
  /* 99 */ "G_STRICT_FSUB\000"
  /* 113 */ "G_ATOMICRMW_FSUB\000"
  /* 130 */ "G_SUB\000"
  /* 136 */ "G_ATOMICRMW_SUB\000"
  /* 152 */ "BRCC\000"
  /* 157 */ "SCC\000"
  /* 161 */ "BRIND_CC\000"
  /* 170 */ "G_INTRINSIC\000"
  /* 182 */ "G_FPTRUNC\000"
  /* 192 */ "G_INTRINSIC_TRUNC\000"
  /* 210 */ "G_TRUNC\000"
  /* 218 */ "G_BUILD_VECTOR_TRUNC\000"
  /* 239 */ "G_DYN_STACKALLOC\000"
  /* 256 */ "ADJDYNALLOC\000"
  /* 268 */ "POPC\000"
  /* 273 */ "G_FMAD\000"
  /* 280 */ "G_INDEXED_SEXTLOAD\000"
  /* 299 */ "G_SEXTLOAD\000"
  /* 310 */ "G_INDEXED_ZEXTLOAD\000"
  /* 329 */ "G_ZEXTLOAD\000"
  /* 340 */ "G_INDEXED_LOAD\000"
  /* 355 */ "G_LOAD\000"
  /* 362 */ "G_VECREDUCE_FADD\000"
  /* 379 */ "G_FADD\000"
  /* 386 */ "G_VECREDUCE_SEQ_FADD\000"
  /* 407 */ "G_STRICT_FADD\000"
  /* 421 */ "G_ATOMICRMW_FADD\000"
  /* 438 */ "G_VECREDUCE_ADD\000"
  /* 454 */ "G_ADD\000"
  /* 460 */ "G_PTR_ADD\000"
  /* 470 */ "G_ATOMICRMW_ADD\000"
  /* 486 */ "G_ATOMICRMW_NAND\000"
  /* 503 */ "G_VECREDUCE_AND\000"
  /* 519 */ "G_AND\000"
  /* 525 */ "G_ATOMICRMW_AND\000"
  /* 541 */ "LIFETIME_END\000"
  /* 554 */ "G_BRCOND\000"
  /* 563 */ "G_ATOMICRMW_USUB_COND\000"
  /* 585 */ "G_LLROUND\000"
  /* 595 */ "G_LROUND\000"
  /* 604 */ "G_INTRINSIC_ROUND\000"
  /* 622 */ "G_INTRINSIC_FPTRUNC_ROUND\000"
  /* 648 */ "LOAD_STACK_GUARD\000"
  /* 665 */ "PSEUDO_PROBE\000"
  /* 678 */ "G_SSUBE\000"
  /* 686 */ "G_USUBE\000"
  /* 694 */ "G_FENCE\000"
  /* 702 */ "ARITH_FENCE\000"
  /* 714 */ "REG_SEQUENCE\000"
  /* 727 */ "G_SADDE\000"
  /* 735 */ "G_UADDE\000"
  /* 743 */ "G_GET_FPMODE\000"
  /* 756 */ "G_RESET_FPMODE\000"
  /* 771 */ "G_SET_FPMODE\000"
  /* 784 */ "G_FMINNUM_IEEE\000"
  /* 799 */ "G_FMAXNUM_IEEE\000"
  /* 814 */ "G_VSCALE\000"
  /* 823 */ "G_JUMP_TABLE\000"
  /* 836 */ "BUNDLE\000"
  /* 843 */ "G_MEMCPY_INLINE\000"
  /* 859 */ "RELOC_NONE\000"
  /* 870 */ "LOCAL_ESCAPE\000"
  /* 883 */ "G_STACKRESTORE\000"
  /* 898 */ "G_INDEXED_STORE\000"
  /* 914 */ "G_STORE\000"
  /* 922 */ "G_BITREVERSE\000"
  /* 935 */ "FAKE_USE\000"
  /* 944 */ "DBG_VALUE\000"
  /* 954 */ "G_GLOBAL_VALUE\000"
  /* 969 */ "G_PTRAUTH_GLOBAL_VALUE\000"
  /* 992 */ "CONVERGENCECTRL_GLUE\000"
  /* 1013 */ "G_STACKSAVE\000"
  /* 1025 */ "G_MEMMOVE\000"
  /* 1035 */ "G_FREEZE\000"
  /* 1044 */ "G_FCANONICALIZE\000"
  /* 1060 */ "G_FMODF\000"
  /* 1068 */ "G_CTLZ_ZERO_UNDEF\000"
  /* 1086 */ "G_CTTZ_ZERO_UNDEF\000"
  /* 1104 */ "INIT_UNDEF\000"
  /* 1115 */ "G_IMPLICIT_DEF\000"
  /* 1130 */ "DBG_INSTR_REF\000"
  /* 1144 */ "G_FNEG\000"
  /* 1151 */ "EXTRACT_SUBREG\000"
  /* 1166 */ "INSERT_SUBREG\000"
  /* 1180 */ "G_SEXT_INREG\000"
  /* 1193 */ "SUBREG_TO_REG\000"
  /* 1207 */ "G_ATOMIC_CMPXCHG\000"
  /* 1224 */ "G_ATOMICRMW_XCHG\000"
  /* 1241 */ "G_GET_ROUNDING\000"
  /* 1256 */ "G_SET_ROUNDING\000"
  /* 1271 */ "G_FLOG\000"
  /* 1278 */ "G_VAARG\000"
  /* 1286 */ "PREALLOCATED_ARG\000"
  /* 1303 */ "G_PREFETCH\000"
  /* 1314 */ "G_SMULH\000"
  /* 1322 */ "G_UMULH\000"
  /* 1330 */ "G_FTANH\000"
  /* 1338 */ "G_FSINH\000"
  /* 1346 */ "G_FCOSH\000"
  /* 1354 */ "DBG_PHI\000"
  /* 1362 */ "MOVHI\000"
  /* 1368 */ "SFSUB_F_RI_HI\000"
  /* 1382 */ "SUBB_I_HI\000"
  /* 1392 */ "SUB_I_HI\000"
  /* 1401 */ "ADDC_I_HI\000"
  /* 1411 */ "ADD_I_HI\000"
  /* 1420 */ "AND_I_HI\000"
  /* 1429 */ "SUBB_F_I_HI\000"
  /* 1441 */ "SUB_F_I_HI\000"
  /* 1452 */ "ADDC_F_I_HI\000"
  /* 1464 */ "ADD_F_I_HI\000"
  /* 1475 */ "AND_F_I_HI\000"
  /* 1486 */ "XOR_F_I_HI\000"
  /* 1497 */ "XOR_I_HI\000"
  /* 1506 */ "SLI\000"
  /* 1510 */ "STB_RI\000"
  /* 1517 */ "STH_RI\000"
  /* 1524 */ "LDW_RI\000"
  /* 1531 */ "SW_RI\000"
  /* 1537 */ "LDBs_RI\000"
  /* 1545 */ "LDHs_RI\000"
  /* 1553 */ "LDBz_RI\000"
  /* 1561 */ "LDHz_RI\000"
  /* 1569 */ "G_FPTOSI\000"
  /* 1578 */ "G_FPTOUI\000"
  /* 1587 */ "G_FPOWI\000"
  /* 1595 */ "SA_I\000"
  /* 1600 */ "SA_F_I\000"
  /* 1607 */ "SL_F_I\000"
  /* 1614 */ "SL_I\000"
  /* 1619 */ "COPY_LANEMASK\000"
  /* 1633 */ "G_PTRMASK\000"
  /* 1643 */ "GC_LABEL\000"
  /* 1652 */ "DBG_LABEL\000"
  /* 1662 */ "EH_LABEL\000"
  /* 1671 */ "ANNOTATION_LABEL\000"
  /* 1688 */ "ICALL_BRANCH_FUNNEL\000"
  /* 1708 */ "G_FSHL\000"
  /* 1715 */ "G_SHL\000"
  /* 1721 */ "G_FCEIL\000"
  /* 1729 */ "G_SAVGCEIL\000"
  /* 1740 */ "G_UAVGCEIL\000"
  /* 1751 */ "PATCHABLE_TAIL_CALL\000"
  /* 1771 */ "PATCHABLE_TYPED_EVENT_CALL\000"
  /* 1798 */ "PATCHABLE_EVENT_CALL\000"
  /* 1819 */ "FENTRY_CALL\000"
  /* 1831 */ "KILL\000"
  /* 1836 */ "G_CONSTANT_POOL\000"
  /* 1852 */ "G_ROTL\000"
  /* 1859 */ "G_VECREDUCE_FMUL\000"
  /* 1876 */ "G_FMUL\000"
  /* 1883 */ "G_VECREDUCE_SEQ_FMUL\000"
  /* 1904 */ "G_STRICT_FMUL\000"
  /* 1918 */ "G_VECREDUCE_MUL\000"
  /* 1934 */ "G_MUL\000"
  /* 1940 */ "G_FREM\000"
  /* 1947 */ "G_STRICT_FREM\000"
  /* 1961 */ "G_SREM\000"
  /* 1968 */ "G_UREM\000"
  /* 1975 */ "G_SDIVREM\000"
  /* 1985 */ "G_UDIVREM\000"
  /* 1995 */ "INLINEASM\000"
  /* 2005 */ "G_VECREDUCE_FMINIMUM\000"
  /* 2026 */ "G_FMINIMUM\000"
  /* 2037 */ "G_ATOMICRMW_FMINIMUM\000"
  /* 2058 */ "G_VECREDUCE_FMAXIMUM\000"
  /* 2079 */ "G_FMAXIMUM\000"
  /* 2090 */ "G_ATOMICRMW_FMAXIMUM\000"
  /* 2111 */ "G_FMINIMUMNUM\000"
  /* 2125 */ "G_FMAXIMUMNUM\000"
  /* 2139 */ "G_FMINNUM\000"
  /* 2149 */ "G_FMAXNUM\000"
  /* 2159 */ "G_FATAN\000"
  /* 2167 */ "G_FTAN\000"
  /* 2174 */ "G_INTRINSIC_ROUNDEVEN\000"
  /* 2196 */ "G_ASSERT_ALIGN\000"
  /* 2211 */ "G_FCOPYSIGN\000"
  /* 2223 */ "G_VECREDUCE_FMIN\000"
  /* 2240 */ "G_ATOMICRMW_FMIN\000"
  /* 2257 */ "G_VECREDUCE_SMIN\000"
  /* 2274 */ "G_SMIN\000"
  /* 2281 */ "G_VECREDUCE_UMIN\000"
  /* 2298 */ "G_UMIN\000"
  /* 2305 */ "G_ATOMICRMW_UMIN\000"
  /* 2322 */ "G_ATOMICRMW_MIN\000"
  /* 2338 */ "G_FASIN\000"
  /* 2346 */ "G_FSIN\000"
  /* 2353 */ "CFI_INSTRUCTION\000"
  /* 2369 */ "ADJCALLSTACKDOWN\000"
  /* 2386 */ "G_SSUBO\000"
  /* 2394 */ "G_USUBO\000"
  /* 2402 */ "G_SADDO\000"
  /* 2410 */ "G_UADDO\000"
  /* 2418 */ "JUMP_TABLE_DEBUG_INFO\000"
  /* 2440 */ "G_SMULO\000"
  /* 2448 */ "G_UMULO\000"
  /* 2456 */ "SFSUB_F_RI_LO\000"
  /* 2470 */ "SUBB_I_LO\000"
  /* 2480 */ "SUB_I_LO\000"
  /* 2489 */ "ADDC_I_LO\000"
  /* 2499 */ "ADD_I_LO\000"
  /* 2508 */ "AND_I_LO\000"
  /* 2517 */ "SUBB_F_I_LO\000"
  /* 2529 */ "SUB_F_I_LO\000"
  /* 2540 */ "ADDC_F_I_LO\000"
  /* 2552 */ "ADD_F_I_LO\000"
  /* 2563 */ "AND_F_I_LO\000"
  /* 2574 */ "XOR_F_I_LO\000"
  /* 2585 */ "XOR_I_LO\000"
  /* 2594 */ "G_BZERO\000"
  /* 2602 */ "STACKMAP\000"
  /* 2611 */ "G_DEBUGTRAP\000"
  /* 2623 */ "G_UBSANTRAP\000"
  /* 2635 */ "G_TRAP\000"
  /* 2642 */ "G_ATOMICRMW_UDEC_WRAP\000"
  /* 2664 */ "G_ATOMICRMW_UINC_WRAP\000"
  /* 2686 */ "G_BSWAP\000"
  /* 2694 */ "G_SITOFP\000"
  /* 2703 */ "G_UITOFP\000"
  /* 2712 */ "G_FCMP\000"
  /* 2719 */ "G_ICMP\000"
  /* 2726 */ "G_SCMP\000"
  /* 2733 */ "G_UCMP\000"
  /* 2740 */ "NOP\000"
  /* 2744 */ "CONVERGENCECTRL_LOOP\000"
  /* 2765 */ "G_CTPOP\000"
  /* 2773 */ "PATCHABLE_OP\000"
  /* 2786 */ "FAULTING_OP\000"
  /* 2798 */ "ADJCALLSTACKUP\000"
  /* 2813 */ "PREALLOCATED_SETUP\000"
  /* 2832 */ "G_FLDEXP\000"
  /* 2841 */ "G_STRICT_FLDEXP\000"
  /* 2857 */ "G_FEXP\000"
  /* 2864 */ "G_FFREXP\000"
  /* 2873 */ "G_BR\000"
  /* 2878 */ "INLINEASM_BR\000"
  /* 2891 */ "LDADDR\000"
  /* 2898 */ "STADDR\000"
  /* 2905 */ "G_BLOCK_ADDR\000"
  /* 2918 */ "MEMBARRIER\000"
  /* 2929 */ "G_CONSTANT_FOLD_BARRIER\000"
  /* 2953 */ "PATCHABLE_FUNCTION_ENTER\000"
  /* 2978 */ "G_READCYCLECOUNTER\000"
  /* 2997 */ "G_READSTEADYCOUNTER\000"
  /* 3017 */ "G_READ_REGISTER\000"
  /* 3033 */ "G_WRITE_REGISTER\000"
  /* 3050 */ "G_ASHR\000"
  /* 3057 */ "G_FSHR\000"
  /* 3064 */ "G_LSHR\000"
  /* 3071 */ "JR\000"
  /* 3074 */ "CALLR\000"
  /* 3080 */ "CONVERGENCECTRL_ANCHOR\000"
  /* 3103 */ "G_FFLOOR\000"
  /* 3112 */ "G_SAVGFLOOR\000"
  /* 3124 */ "G_UAVGFLOOR\000"
  /* 3136 */ "G_EXTRACT_SUBVECTOR\000"
  /* 3156 */ "G_INSERT_SUBVECTOR\000"
  /* 3175 */ "G_BUILD_VECTOR\000"
  /* 3190 */ "G_SHUFFLE_VECTOR\000"
  /* 3207 */ "G_STEP_VECTOR\000"
  /* 3221 */ "G_SPLAT_VECTOR\000"
  /* 3236 */ "G_VECREDUCE_XOR\000"
  /* 3252 */ "G_XOR\000"
  /* 3258 */ "G_ATOMICRMW_XOR\000"
  /* 3274 */ "G_VECREDUCE_OR\000"
  /* 3289 */ "G_OR\000"
  /* 3294 */ "G_ATOMICRMW_OR\000"
  /* 3309 */ "BRR\000"
  /* 3313 */ "STB_RR\000"
  /* 3320 */ "SFSUB_F_RR\000"
  /* 3331 */ "STH_RR\000"
  /* 3338 */ "LDW_RR\000"
  /* 3345 */ "SW_RR\000"
  /* 3351 */ "LDBs_RR\000"
  /* 3359 */ "LDHs_RR\000"
  /* 3367 */ "LDBz_RR\000"
  /* 3375 */ "LDHz_RR\000"
  /* 3383 */ "LDWz_RR\000"
  /* 3391 */ "G_ROTR\000"
  /* 3398 */ "G_INTTOPTR\000"
  /* 3409 */ "SRA_R\000"
  /* 3415 */ "SUBB_R\000"
  /* 3422 */ "SUB_R\000"
  /* 3428 */ "ADDC_R\000"
  /* 3435 */ "ADD_R\000"
  /* 3441 */ "AND_R\000"
  /* 3447 */ "SRA_F_R\000"
  /* 3455 */ "SUBB_F_R\000"
  /* 3464 */ "SUB_F_R\000"
  /* 3472 */ "ADDC_F_R\000"
  /* 3481 */ "ADD_F_R\000"
  /* 3489 */ "AND_F_R\000"
  /* 3497 */ "SHL_F_R\000"
  /* 3505 */ "SRL_F_R\000"
  /* 3513 */ "XOR_F_R\000"
  /* 3521 */ "SHL_R\000"
  /* 3527 */ "SRL_R\000"
  /* 3533 */ "XOR_R\000"
  /* 3539 */ "G_FABS\000"
  /* 3546 */ "G_ABS\000"
  /* 3552 */ "G_ABDS\000"
  /* 3559 */ "G_UNMERGE_VALUES\000"
  /* 3576 */ "G_MERGE_VALUES\000"
  /* 3591 */ "G_FACOS\000"
  /* 3599 */ "G_FCOS\000"
  /* 3606 */ "G_FSINCOS\000"
  /* 3616 */ "G_CONCAT_VECTORS\000"
  /* 3633 */ "COPY_TO_REGCLASS\000"
  /* 3650 */ "G_IS_FPCLASS\000"
  /* 3663 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\000"
  /* 3693 */ "G_VECTOR_COMPRESS\000"
  /* 3711 */ "G_INTRINSIC_W_SIDE_EFFECTS\000"
  /* 3738 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\000"
  /* 3776 */ "G_TRUNC_SSAT_S\000"
  /* 3791 */ "G_SSUBSAT\000"
  /* 3801 */ "G_USUBSAT\000"
  /* 3811 */ "G_SADDSAT\000"
  /* 3821 */ "G_UADDSAT\000"
  /* 3831 */ "G_SSHLSAT\000"
  /* 3841 */ "G_USHLSAT\000"
  /* 3851 */ "G_SMULFIXSAT\000"
  /* 3864 */ "G_UMULFIXSAT\000"
  /* 3877 */ "G_SDIVFIXSAT\000"
  /* 3890 */ "G_UDIVFIXSAT\000"
  /* 3903 */ "G_ATOMICRMW_USUB_SAT\000"
  /* 3924 */ "G_FPTOSI_SAT\000"
  /* 3937 */ "G_FPTOUI_SAT\000"
  /* 3950 */ "BT\000"
  /* 3953 */ "G_EXTRACT\000"
  /* 3963 */ "G_SELECT\000"
  /* 3972 */ "G_BRINDIRECT\000"
  /* 3985 */ "PATCHABLE_RET\000"
  /* 3999 */ "G_MEMSET\000"
  /* 4008 */ "PATCHABLE_FUNCTION_EXIT\000"
  /* 4032 */ "G_BRJT\000"
  /* 4039 */ "G_EXTRACT_VECTOR_ELT\000"
  /* 4060 */ "G_INSERT_VECTOR_ELT\000"
  /* 4080 */ "G_FCONSTANT\000"
  /* 4092 */ "G_CONSTANT\000"
  /* 4103 */ "G_INTRINSIC_CONVERGENT\000"
  /* 4126 */ "STATEPOINT\000"
  /* 4137 */ "PATCHPOINT\000"
  /* 4148 */ "G_PTRTOINT\000"
  /* 4159 */ "G_FRINT\000"
  /* 4167 */ "G_INTRINSIC_LLRINT\000"
  /* 4186 */ "G_INTRINSIC_LRINT\000"
  /* 4204 */ "G_FNEARBYINT\000"
  /* 4217 */ "G_VASTART\000"
  /* 4227 */ "LIFETIME_START\000"
  /* 4242 */ "G_INVOKE_REGION_START\000"
  /* 4264 */ "G_INSERT\000"
  /* 4273 */ "G_FSQRT\000"
  /* 4281 */ "G_STRICT_FSQRT\000"
  /* 4296 */ "G_BITCAST\000"
  /* 4306 */ "G_ADDRSPACE_CAST\000"
  /* 4323 */ "DBG_VALUE_LIST\000"
  /* 4338 */ "G_FPEXT\000"
  /* 4346 */ "G_SEXT\000"
  /* 4353 */ "G_ASSERT_SEXT\000"
  /* 4367 */ "G_ANYEXT\000"
  /* 4376 */ "G_ZEXT\000"
  /* 4383 */ "G_ASSERT_ZEXT\000"
  /* 4397 */ "G_ABDU\000"
  /* 4404 */ "G_TRUNC_SSAT_U\000"
  /* 4419 */ "G_TRUNC_USAT_U\000"
  /* 4434 */ "G_FDIV\000"
  /* 4441 */ "G_STRICT_FDIV\000"
  /* 4455 */ "G_SDIV\000"
  /* 4462 */ "G_UDIV\000"
  /* 4469 */ "G_GET_FPENV\000"
  /* 4481 */ "G_RESET_FPENV\000"
  /* 4495 */ "G_SET_FPENV\000"
  /* 4507 */ "G_FPOW\000"
  /* 4514 */ "G_VECREDUCE_FMAX\000"
  /* 4531 */ "G_ATOMICRMW_FMAX\000"
  /* 4548 */ "G_VECREDUCE_SMAX\000"
  /* 4565 */ "G_SMAX\000"
  /* 4572 */ "G_VECREDUCE_UMAX\000"
  /* 4589 */ "G_UMAX\000"
  /* 4596 */ "G_ATOMICRMW_UMAX\000"
  /* 4613 */ "G_ATOMICRMW_MAX\000"
  /* 4629 */ "G_FRAME_INDEX\000"
  /* 4643 */ "G_SBFX\000"
  /* 4650 */ "G_UBFX\000"
  /* 4657 */ "G_SMULFIX\000"
  /* 4667 */ "G_UMULFIX\000"
  /* 4677 */ "G_SDIVFIX\000"
  /* 4687 */ "G_UDIVFIX\000"
  /* 4697 */ "G_MEMCPY\000"
  /* 4706 */ "COPY\000"
  /* 4711 */ "CONVERGENCECTRL_ENTRY\000"
  /* 4733 */ "LEADZ\000"
  /* 4739 */ "TRAILZ\000"
  /* 4746 */ "G_CTLZ\000"
  /* 4753 */ "G_CTTZ\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const unsigned LanaiInstrNameIndices[] = {
    1358U, 1995U, 2878U, 2353U, 1662U, 1643U, 1671U, 1831U, 
    1151U, 1166U, 1117U, 1104U, 1193U, 3633U, 944U, 4323U, 
    1130U, 1354U, 1652U, 714U, 4706U, 1619U, 836U, 4227U, 
    541U, 665U, 702U, 2602U, 1819U, 4137U, 648U, 2813U, 
    1286U, 4126U, 870U, 2786U, 2773U, 2953U, 3985U, 4008U, 
    1751U, 1798U, 1771U, 1688U, 935U, 2918U, 2418U, 859U, 
    4711U, 3080U, 2744U, 992U, 4353U, 4383U, 2196U, 454U, 
    130U, 1934U, 4455U, 4462U, 1961U, 1968U, 1975U, 1985U, 
    519U, 3289U, 3252U, 3552U, 4397U, 3124U, 1740U, 3112U, 
    1729U, 1115U, 1356U, 4629U, 954U, 969U, 1836U, 3953U, 
    3559U, 4264U, 3576U, 3175U, 218U, 3616U, 4148U, 3398U, 
    4296U, 1035U, 2929U, 622U, 192U, 604U, 4186U, 4167U, 
    2174U, 2978U, 2997U, 355U, 299U, 329U, 340U, 280U, 
    310U, 914U, 898U, 3663U, 1207U, 1224U, 470U, 136U, 
    525U, 486U, 3294U, 3258U, 4613U, 2322U, 4596U, 2305U, 
    421U, 113U, 4531U, 2240U, 2090U, 2037U, 2664U, 2642U, 
    563U, 3903U, 694U, 1303U, 554U, 3972U, 4242U, 170U, 
    3711U, 4103U, 3738U, 4367U, 210U, 3776U, 4404U, 4419U, 
    4092U, 4080U, 4217U, 1278U, 4346U, 1180U, 4376U, 1715U, 
    3064U, 3050U, 1708U, 3057U, 3391U, 1852U, 2719U, 2712U, 
    2726U, 2733U, 3963U, 2410U, 735U, 2394U, 686U, 2402U, 
    727U, 2386U, 678U, 2448U, 2440U, 1322U, 1314U, 3821U, 
    3811U, 3801U, 3791U, 3841U, 3831U, 4657U, 4667U, 3851U, 
    3864U, 4677U, 4687U, 3877U, 3890U, 379U, 92U, 1876U, 
    73U, 273U, 4434U, 1940U, 1060U, 4507U, 1587U, 2857U, 
    45U, 9U, 1271U, 28U, 0U, 2832U, 2864U, 1144U, 
    4338U, 182U, 1569U, 1578U, 2694U, 2703U, 3924U, 3937U, 
    3539U, 2211U, 3650U, 1044U, 2139U, 2149U, 784U, 799U, 
    2026U, 2079U, 2111U, 2125U, 4469U, 4495U, 4481U, 743U, 
    771U, 756U, 1241U, 1256U, 460U, 1633U, 2274U, 4565U, 
    2298U, 4589U, 3546U, 595U, 585U, 2873U, 4032U, 814U, 
    3156U, 3136U, 4060U, 4039U, 3190U, 3221U, 3207U, 3693U, 
    4753U, 1086U, 4746U, 1068U, 2765U, 2686U, 922U, 1721U, 
    3599U, 2346U, 3606U, 2167U, 3591U, 2338U, 2159U, 36U, 
    1346U, 1338U, 1330U, 4273U, 3103U, 4159U, 4204U, 4306U, 
    2905U, 823U, 239U, 1013U, 883U, 407U, 99U, 1904U, 
    4441U, 1947U, 79U, 4281U, 2841U, 3017U, 3033U, 4697U, 
    843U, 1025U, 3999U, 2594U, 2635U, 2611U, 2623U, 386U, 
    1883U, 362U, 1859U, 4514U, 2223U, 2058U, 2005U, 438U, 
    1918U, 503U, 3274U, 3236U, 4548U, 2257U, 4572U, 2281U, 
    4643U, 4650U, 2369U, 2798U, 256U, 1766U, 3074U, 1452U, 
    2540U, 3472U, 1401U, 2489U, 3428U, 1464U, 2552U, 3481U, 
    1411U, 2499U, 3435U, 1475U, 2563U, 3489U, 1420U, 2508U, 
    3441U, 152U, 161U, 63U, 3309U, 3950U, 3071U, 2891U, 
    1537U, 3351U, 1553U, 3367U, 1545U, 3359U, 1561U, 3375U, 
    1524U, 3338U, 3383U, 4733U, 18U, 23U, 31U, 53U, 
    58U, 1362U, 2740U, 1487U, 2575U, 3514U, 1498U, 2586U, 
    3534U, 268U, 3995U, 1600U, 1595U, 157U, 3965U, 1368U, 
    2456U, 3320U, 3497U, 3521U, 1506U, 1607U, 1614U, 3447U, 
    3409U, 3505U, 3527U, 2898U, 1510U, 3313U, 1517U, 3331U, 
    1429U, 2517U, 3455U, 1382U, 2470U, 3415U, 1441U, 2529U, 
    3464U, 1392U, 2480U, 3422U, 1531U, 3345U, 4739U, 1486U, 
    2574U, 3513U, 1497U, 2585U, 3533U, 
};

static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
  II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 421, nullptr, 0);
}


} // namespace llvm

#endif // GET_INSTRINFO_MC_DESC

#ifdef GET_INSTRINFO_HEADER
#undef GET_INSTRINFO_HEADER

namespace llvm {

struct LanaiGenInstrInfo : public TargetInstrInfo {
  explicit LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
  ~LanaiGenInstrInfo() override = default;
};

} // namespace llvm

namespace llvm::Lanai {

constexpr unsigned SUBOP_MEMri_base = 0;
constexpr unsigned SUBOP_MEMri_offset = 1;
constexpr unsigned SUBOP_MEMri_Opcode = 2;
constexpr unsigned SUBOP_MEMrr_Op1 = 0;
constexpr unsigned SUBOP_MEMrr_Op2 = 1;
constexpr unsigned SUBOP_MEMrr_Opcode = 2;
constexpr unsigned SUBOP_MEMspls_base = 0;
constexpr unsigned SUBOP_MEMspls_offset = 1;
constexpr unsigned SUBOP_MEMspls_Opcode = 2;

} // namespace llvm::Lanai

#endif // GET_INSTRINFO_HEADER

#ifdef GET_INSTRINFO_HELPER_DECLS
#undef GET_INSTRINFO_HELPER_DECLS


#endif // GET_INSTRINFO_HELPER_DECLS

#ifdef GET_INSTRINFO_HELPERS
#undef GET_INSTRINFO_HELPERS


#endif // GET_INSTRINFO_HELPERS

#ifdef GET_INSTRINFO_CTOR_DTOR
#undef GET_INSTRINFO_CTOR_DTOR

namespace llvm {

extern const LanaiInstrTable LanaiDescs;
extern const unsigned LanaiInstrNameIndices[];
extern const char LanaiInstrNameData[];
LanaiGenInstrInfo::LanaiGenInstrInfo(const TargetSubtargetInfo &STI, const TargetRegisterInfo &TRI, unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
  : TargetInstrInfo(TRI, CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
  InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 421);
}

} // namespace llvm

#endif // GET_INSTRINFO_CTOR_DTOR

#ifdef GET_INSTRINFO_MC_HELPER_DECLS
#undef GET_INSTRINFO_MC_HELPER_DECLS

namespace llvm {

class MCInst;
class FeatureBitset;

namespace Lanai_MC {

void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);

} // namespace Lanai_MC

} // namespace llvm

#endif // GET_INSTRINFO_MC_HELPER_DECLS

#ifdef GET_INSTRINFO_MC_HELPERS
#undef GET_INSTRINFO_MC_HELPERS

namespace llvm::Lanai_MC {


} // namespace llvm::Lanai_MC

#endif // GET_INSTRINFO_MC_HELPERS

#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
    defined(GET_AVAILABLE_OPCODE_CHECKER)
#define GET_COMPUTE_FEATURES
#endif
#ifdef GET_COMPUTE_FEATURES
#undef GET_COMPUTE_FEATURES

namespace llvm::Lanai_MC {

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
};

inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
  FeatureBitset Features;
  return Features;
}

inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
  enum : uint8_t {
    CEFBS_None,
  };

  static constexpr FeatureBitset FeatureBitsets[] = {
    {}, // CEFBS_None
  };
  static constexpr uint8_t RequiredFeaturesRefs[] = {
    CEFBS_None, // PHI
    CEFBS_None, // INLINEASM
    CEFBS_None, // INLINEASM_BR
    CEFBS_None, // CFI_INSTRUCTION
    CEFBS_None, // EH_LABEL
    CEFBS_None, // GC_LABEL
    CEFBS_None, // ANNOTATION_LABEL
    CEFBS_None, // KILL
    CEFBS_None, // EXTRACT_SUBREG
    CEFBS_None, // INSERT_SUBREG
    CEFBS_None, // IMPLICIT_DEF
    CEFBS_None, // INIT_UNDEF
    CEFBS_None, // SUBREG_TO_REG
    CEFBS_None, // COPY_TO_REGCLASS
    CEFBS_None, // DBG_VALUE
    CEFBS_None, // DBG_VALUE_LIST
    CEFBS_None, // DBG_INSTR_REF
    CEFBS_None, // DBG_PHI
    CEFBS_None, // DBG_LABEL
    CEFBS_None, // REG_SEQUENCE
    CEFBS_None, // COPY
    CEFBS_None, // COPY_LANEMASK
    CEFBS_None, // BUNDLE
    CEFBS_None, // LIFETIME_START
    CEFBS_None, // LIFETIME_END
    CEFBS_None, // PSEUDO_PROBE
    CEFBS_None, // ARITH_FENCE
    CEFBS_None, // STACKMAP
    CEFBS_None, // FENTRY_CALL
    CEFBS_None, // PATCHPOINT
    CEFBS_None, // LOAD_STACK_GUARD
    CEFBS_None, // PREALLOCATED_SETUP
    CEFBS_None, // PREALLOCATED_ARG
    CEFBS_None, // STATEPOINT
    CEFBS_None, // LOCAL_ESCAPE
    CEFBS_None, // FAULTING_OP
    CEFBS_None, // PATCHABLE_OP
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER
    CEFBS_None, // PATCHABLE_RET
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT
    CEFBS_None, // PATCHABLE_TAIL_CALL
    CEFBS_None, // PATCHABLE_EVENT_CALL
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL
    CEFBS_None, // ICALL_BRANCH_FUNNEL
    CEFBS_None, // FAKE_USE
    CEFBS_None, // MEMBARRIER
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO
    CEFBS_None, // RELOC_NONE
    CEFBS_None, // CONVERGENCECTRL_ENTRY
    CEFBS_None, // CONVERGENCECTRL_ANCHOR
    CEFBS_None, // CONVERGENCECTRL_LOOP
    CEFBS_None, // CONVERGENCECTRL_GLUE
    CEFBS_None, // G_ASSERT_SEXT
    CEFBS_None, // G_ASSERT_ZEXT
    CEFBS_None, // G_ASSERT_ALIGN
    CEFBS_None, // G_ADD
    CEFBS_None, // G_SUB
    CEFBS_None, // G_MUL
    CEFBS_None, // G_SDIV
    CEFBS_None, // G_UDIV
    CEFBS_None, // G_SREM
    CEFBS_None, // G_UREM
    CEFBS_None, // G_SDIVREM
    CEFBS_None, // G_UDIVREM
    CEFBS_None, // G_AND
    CEFBS_None, // G_OR
    CEFBS_None, // G_XOR
    CEFBS_None, // G_ABDS
    CEFBS_None, // G_ABDU
    CEFBS_None, // G_UAVGFLOOR
    CEFBS_None, // G_UAVGCEIL
    CEFBS_None, // G_SAVGFLOOR
    CEFBS_None, // G_SAVGCEIL
    CEFBS_None, // G_IMPLICIT_DEF
    CEFBS_None, // G_PHI
    CEFBS_None, // G_FRAME_INDEX
    CEFBS_None, // G_GLOBAL_VALUE
    CEFBS_None, // G_PTRAUTH_GLOBAL_VALUE
    CEFBS_None, // G_CONSTANT_POOL
    CEFBS_None, // G_EXTRACT
    CEFBS_None, // G_UNMERGE_VALUES
    CEFBS_None, // G_INSERT
    CEFBS_None, // G_MERGE_VALUES
    CEFBS_None, // G_BUILD_VECTOR
    CEFBS_None, // G_BUILD_VECTOR_TRUNC
    CEFBS_None, // G_CONCAT_VECTORS
    CEFBS_None, // G_PTRTOINT
    CEFBS_None, // G_INTTOPTR
    CEFBS_None, // G_BITCAST
    CEFBS_None, // G_FREEZE
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND
    CEFBS_None, // G_INTRINSIC_TRUNC
    CEFBS_None, // G_INTRINSIC_ROUND
    CEFBS_None, // G_INTRINSIC_LRINT
    CEFBS_None, // G_INTRINSIC_LLRINT
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN
    CEFBS_None, // G_READCYCLECOUNTER
    CEFBS_None, // G_READSTEADYCOUNTER
    CEFBS_None, // G_LOAD
    CEFBS_None, // G_SEXTLOAD
    CEFBS_None, // G_ZEXTLOAD
    CEFBS_None, // G_INDEXED_LOAD
    CEFBS_None, // G_INDEXED_SEXTLOAD
    CEFBS_None, // G_INDEXED_ZEXTLOAD
    CEFBS_None, // G_STORE
    CEFBS_None, // G_INDEXED_STORE
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    CEFBS_None, // G_ATOMIC_CMPXCHG
    CEFBS_None, // G_ATOMICRMW_XCHG
    CEFBS_None, // G_ATOMICRMW_ADD
    CEFBS_None, // G_ATOMICRMW_SUB
    CEFBS_None, // G_ATOMICRMW_AND
    CEFBS_None, // G_ATOMICRMW_NAND
    CEFBS_None, // G_ATOMICRMW_OR
    CEFBS_None, // G_ATOMICRMW_XOR
    CEFBS_None, // G_ATOMICRMW_MAX
    CEFBS_None, // G_ATOMICRMW_MIN
    CEFBS_None, // G_ATOMICRMW_UMAX
    CEFBS_None, // G_ATOMICRMW_UMIN
    CEFBS_None, // G_ATOMICRMW_FADD
    CEFBS_None, // G_ATOMICRMW_FSUB
    CEFBS_None, // G_ATOMICRMW_FMAX
    CEFBS_None, // G_ATOMICRMW_FMIN
    CEFBS_None, // G_ATOMICRMW_FMAXIMUM
    CEFBS_None, // G_ATOMICRMW_FMINIMUM
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP
    CEFBS_None, // G_ATOMICRMW_USUB_COND
    CEFBS_None, // G_ATOMICRMW_USUB_SAT
    CEFBS_None, // G_FENCE
    CEFBS_None, // G_PREFETCH
    CEFBS_None, // G_BRCOND
    CEFBS_None, // G_BRINDIRECT
    CEFBS_None, // G_INVOKE_REGION_START
    CEFBS_None, // G_INTRINSIC
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS
    CEFBS_None, // G_INTRINSIC_CONVERGENT
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    CEFBS_None, // G_ANYEXT
    CEFBS_None, // G_TRUNC
    CEFBS_None, // G_TRUNC_SSAT_S
    CEFBS_None, // G_TRUNC_SSAT_U
    CEFBS_None, // G_TRUNC_USAT_U
    CEFBS_None, // G_CONSTANT
    CEFBS_None, // G_FCONSTANT
    CEFBS_None, // G_VASTART
    CEFBS_None, // G_VAARG
    CEFBS_None, // G_SEXT
    CEFBS_None, // G_SEXT_INREG
    CEFBS_None, // G_ZEXT
    CEFBS_None, // G_SHL
    CEFBS_None, // G_LSHR
    CEFBS_None, // G_ASHR
    CEFBS_None, // G_FSHL
    CEFBS_None, // G_FSHR
    CEFBS_None, // G_ROTR
    CEFBS_None, // G_ROTL
    CEFBS_None, // G_ICMP
    CEFBS_None, // G_FCMP
    CEFBS_None, // G_SCMP
    CEFBS_None, // G_UCMP
    CEFBS_None, // G_SELECT
    CEFBS_None, // G_UADDO
    CEFBS_None, // G_UADDE
    CEFBS_None, // G_USUBO
    CEFBS_None, // G_USUBE
    CEFBS_None, // G_SADDO
    CEFBS_None, // G_SADDE
    CEFBS_None, // G_SSUBO
    CEFBS_None, // G_SSUBE
    CEFBS_None, // G_UMULO
    CEFBS_None, // G_SMULO
    CEFBS_None, // G_UMULH
    CEFBS_None, // G_SMULH
    CEFBS_None, // G_UADDSAT
    CEFBS_None, // G_SADDSAT
    CEFBS_None, // G_USUBSAT
    CEFBS_None, // G_SSUBSAT
    CEFBS_None, // G_USHLSAT
    CEFBS_None, // G_SSHLSAT
    CEFBS_None, // G_SMULFIX
    CEFBS_None, // G_UMULFIX
    CEFBS_None, // G_SMULFIXSAT
    CEFBS_None, // G_UMULFIXSAT
    CEFBS_None, // G_SDIVFIX
    CEFBS_None, // G_UDIVFIX
    CEFBS_None, // G_SDIVFIXSAT
    CEFBS_None, // G_UDIVFIXSAT
    CEFBS_None, // G_FADD
    CEFBS_None, // G_FSUB
    CEFBS_None, // G_FMUL
    CEFBS_None, // G_FMA
    CEFBS_None, // G_FMAD
    CEFBS_None, // G_FDIV
    CEFBS_None, // G_FREM
    CEFBS_None, // G_FMODF
    CEFBS_None, // G_FPOW
    CEFBS_None, // G_FPOWI
    CEFBS_None, // G_FEXP
    CEFBS_None, // G_FEXP2
    CEFBS_None, // G_FEXP10
    CEFBS_None, // G_FLOG
    CEFBS_None, // G_FLOG2
    CEFBS_None, // G_FLOG10
    CEFBS_None, // G_FLDEXP
    CEFBS_None, // G_FFREXP
    CEFBS_None, // G_FNEG
    CEFBS_None, // G_FPEXT
    CEFBS_None, // G_FPTRUNC
    CEFBS_None, // G_FPTOSI
    CEFBS_None, // G_FPTOUI
    CEFBS_None, // G_SITOFP
    CEFBS_None, // G_UITOFP
    CEFBS_None, // G_FPTOSI_SAT
    CEFBS_None, // G_FPTOUI_SAT
    CEFBS_None, // G_FABS
    CEFBS_None, // G_FCOPYSIGN
    CEFBS_None, // G_IS_FPCLASS
    CEFBS_None, // G_FCANONICALIZE
    CEFBS_None, // G_FMINNUM
    CEFBS_None, // G_FMAXNUM
    CEFBS_None, // G_FMINNUM_IEEE
    CEFBS_None, // G_FMAXNUM_IEEE
    CEFBS_None, // G_FMINIMUM
    CEFBS_None, // G_FMAXIMUM
    CEFBS_None, // G_FMINIMUMNUM
    CEFBS_None, // G_FMAXIMUMNUM
    CEFBS_None, // G_GET_FPENV
    CEFBS_None, // G_SET_FPENV
    CEFBS_None, // G_RESET_FPENV
    CEFBS_None, // G_GET_FPMODE
    CEFBS_None, // G_SET_FPMODE
    CEFBS_None, // G_RESET_FPMODE
    CEFBS_None, // G_GET_ROUNDING
    CEFBS_None, // G_SET_ROUNDING
    CEFBS_None, // G_PTR_ADD
    CEFBS_None, // G_PTRMASK
    CEFBS_None, // G_SMIN
    CEFBS_None, // G_SMAX
    CEFBS_None, // G_UMIN
    CEFBS_None, // G_UMAX
    CEFBS_None, // G_ABS
    CEFBS_None, // G_LROUND
    CEFBS_None, // G_LLROUND
    CEFBS_None, // G_BR
    CEFBS_None, // G_BRJT
    CEFBS_None, // G_VSCALE
    CEFBS_None, // G_INSERT_SUBVECTOR
    CEFBS_None, // G_EXTRACT_SUBVECTOR
    CEFBS_None, // G_INSERT_VECTOR_ELT
    CEFBS_None, // G_EXTRACT_VECTOR_ELT
    CEFBS_None, // G_SHUFFLE_VECTOR
    CEFBS_None, // G_SPLAT_VECTOR
    CEFBS_None, // G_STEP_VECTOR
    CEFBS_None, // G_VECTOR_COMPRESS
    CEFBS_None, // G_CTTZ
    CEFBS_None, // G_CTTZ_ZERO_UNDEF
    CEFBS_None, // G_CTLZ
    CEFBS_None, // G_CTLZ_ZERO_UNDEF
    CEFBS_None, // G_CTPOP
    CEFBS_None, // G_BSWAP
    CEFBS_None, // G_BITREVERSE
    CEFBS_None, // G_FCEIL
    CEFBS_None, // G_FCOS
    CEFBS_None, // G_FSIN
    CEFBS_None, // G_FSINCOS
    CEFBS_None, // G_FTAN
    CEFBS_None, // G_FACOS
    CEFBS_None, // G_FASIN
    CEFBS_None, // G_FATAN
    CEFBS_None, // G_FATAN2
    CEFBS_None, // G_FCOSH
    CEFBS_None, // G_FSINH
    CEFBS_None, // G_FTANH
    CEFBS_None, // G_FSQRT
    CEFBS_None, // G_FFLOOR
    CEFBS_None, // G_FRINT
    CEFBS_None, // G_FNEARBYINT
    CEFBS_None, // G_ADDRSPACE_CAST
    CEFBS_None, // G_BLOCK_ADDR
    CEFBS_None, // G_JUMP_TABLE
    CEFBS_None, // G_DYN_STACKALLOC
    CEFBS_None, // G_STACKSAVE
    CEFBS_None, // G_STACKRESTORE
    CEFBS_None, // G_STRICT_FADD
    CEFBS_None, // G_STRICT_FSUB
    CEFBS_None, // G_STRICT_FMUL
    CEFBS_None, // G_STRICT_FDIV
    CEFBS_None, // G_STRICT_FREM
    CEFBS_None, // G_STRICT_FMA
    CEFBS_None, // G_STRICT_FSQRT
    CEFBS_None, // G_STRICT_FLDEXP
    CEFBS_None, // G_READ_REGISTER
    CEFBS_None, // G_WRITE_REGISTER
    CEFBS_None, // G_MEMCPY
    CEFBS_None, // G_MEMCPY_INLINE
    CEFBS_None, // G_MEMMOVE
    CEFBS_None, // G_MEMSET
    CEFBS_None, // G_BZERO
    CEFBS_None, // G_TRAP
    CEFBS_None, // G_DEBUGTRAP
    CEFBS_None, // G_UBSANTRAP
    CEFBS_None, // G_VECREDUCE_SEQ_FADD
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL
    CEFBS_None, // G_VECREDUCE_FADD
    CEFBS_None, // G_VECREDUCE_FMUL
    CEFBS_None, // G_VECREDUCE_FMAX
    CEFBS_None, // G_VECREDUCE_FMIN
    CEFBS_None, // G_VECREDUCE_FMAXIMUM
    CEFBS_None, // G_VECREDUCE_FMINIMUM
    CEFBS_None, // G_VECREDUCE_ADD
    CEFBS_None, // G_VECREDUCE_MUL
    CEFBS_None, // G_VECREDUCE_AND
    CEFBS_None, // G_VECREDUCE_OR
    CEFBS_None, // G_VECREDUCE_XOR
    CEFBS_None, // G_VECREDUCE_SMAX
    CEFBS_None, // G_VECREDUCE_SMIN
    CEFBS_None, // G_VECREDUCE_UMAX
    CEFBS_None, // G_VECREDUCE_UMIN
    CEFBS_None, // G_SBFX
    CEFBS_None, // G_UBFX
    CEFBS_None, // ADJCALLSTACKDOWN
    CEFBS_None, // ADJCALLSTACKUP
    CEFBS_None, // ADJDYNALLOC
    CEFBS_None, // CALL
    CEFBS_None, // CALLR
    CEFBS_None, // ADDC_F_I_HI
    CEFBS_None, // ADDC_F_I_LO
    CEFBS_None, // ADDC_F_R
    CEFBS_None, // ADDC_I_HI
    CEFBS_None, // ADDC_I_LO
    CEFBS_None, // ADDC_R
    CEFBS_None, // ADD_F_I_HI
    CEFBS_None, // ADD_F_I_LO
    CEFBS_None, // ADD_F_R
    CEFBS_None, // ADD_I_HI
    CEFBS_None, // ADD_I_LO
    CEFBS_None, // ADD_R
    CEFBS_None, // AND_F_I_HI
    CEFBS_None, // AND_F_I_LO
    CEFBS_None, // AND_F_R
    CEFBS_None, // AND_I_HI
    CEFBS_None, // AND_I_LO
    CEFBS_None, // AND_R
    CEFBS_None, // BRCC
    CEFBS_None, // BRIND_CC
    CEFBS_None, // BRIND_CCA
    CEFBS_None, // BRR
    CEFBS_None, // BT
    CEFBS_None, // JR
    CEFBS_None, // LDADDR
    CEFBS_None, // LDBs_RI
    CEFBS_None, // LDBs_RR
    CEFBS_None, // LDBz_RI
    CEFBS_None, // LDBz_RR
    CEFBS_None, // LDHs_RI
    CEFBS_None, // LDHs_RR
    CEFBS_None, // LDHz_RI
    CEFBS_None, // LDHz_RR
    CEFBS_None, // LDW_RI
    CEFBS_None, // LDW_RR
    CEFBS_None, // LDWz_RR
    CEFBS_None, // LEADZ
    CEFBS_None, // LOG0
    CEFBS_None, // LOG1
    CEFBS_None, // LOG2
    CEFBS_None, // LOG3
    CEFBS_None, // LOG4
    CEFBS_None, // MOVHI
    CEFBS_None, // NOP
    CEFBS_None, // OR_F_I_HI
    CEFBS_None, // OR_F_I_LO
    CEFBS_None, // OR_F_R
    CEFBS_None, // OR_I_HI
    CEFBS_None, // OR_I_LO
    CEFBS_None, // OR_R
    CEFBS_None, // POPC
    CEFBS_None, // RET
    CEFBS_None, // SA_F_I
    CEFBS_None, // SA_I
    CEFBS_None, // SCC
    CEFBS_None, // SELECT
    CEFBS_None, // SFSUB_F_RI_HI
    CEFBS_None, // SFSUB_F_RI_LO
    CEFBS_None, // SFSUB_F_RR
    CEFBS_None, // SHL_F_R
    CEFBS_None, // SHL_R
    CEFBS_None, // SLI
    CEFBS_None, // SL_F_I
    CEFBS_None, // SL_I
    CEFBS_None, // SRA_F_R
    CEFBS_None, // SRA_R
    CEFBS_None, // SRL_F_R
    CEFBS_None, // SRL_R
    CEFBS_None, // STADDR
    CEFBS_None, // STB_RI
    CEFBS_None, // STB_RR
    CEFBS_None, // STH_RI
    CEFBS_None, // STH_RR
    CEFBS_None, // SUBB_F_I_HI
    CEFBS_None, // SUBB_F_I_LO
    CEFBS_None, // SUBB_F_R
    CEFBS_None, // SUBB_I_HI
    CEFBS_None, // SUBB_I_LO
    CEFBS_None, // SUBB_R
    CEFBS_None, // SUB_F_I_HI
    CEFBS_None, // SUB_F_I_LO
    CEFBS_None, // SUB_F_R
    CEFBS_None, // SUB_I_HI
    CEFBS_None, // SUB_I_LO
    CEFBS_None, // SUB_R
    CEFBS_None, // SW_RI
    CEFBS_None, // SW_RR
    CEFBS_None, // TRAILZ
    CEFBS_None, // XOR_F_I_HI
    CEFBS_None, // XOR_F_I_LO
    CEFBS_None, // XOR_F_R
    CEFBS_None, // XOR_I_HI
    CEFBS_None, // XOR_I_LO
    CEFBS_None, // XOR_R
  };

  assert(Opcode < 421);
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
}


} // namespace llvm::Lanai_MC

#endif // GET_COMPUTE_FEATURES

#ifdef GET_AVAILABLE_OPCODE_CHECKER
#undef GET_AVAILABLE_OPCODE_CHECKER

namespace llvm::Lanai_MC {

bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  return !MissingFeatures.any();
}

} // namespace llvm::Lanai_MC

#endif // GET_AVAILABLE_OPCODE_CHECKER

#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
#undef ENABLE_INSTR_PREDICATE_VERIFIER

#include <sstream>

namespace llvm::Lanai_MC {

#ifndef NDEBUG
static const char *SubtargetFeatureNames[] = {
  nullptr
};

#endif // NDEBUG

void verifyInstructionPredicates(
    unsigned Opcode, const FeatureBitset &Features) {
#ifndef NDEBUG
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
  FeatureBitset MissingFeatures =
      (AvailableFeatures & RequiredFeatures) ^
      RequiredFeatures;
  if (MissingFeatures.any()) {
    std::ostringstream Msg;
    Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
        << " instruction but the ";
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
      if (MissingFeatures.test(i))
        Msg << SubtargetFeatureNames[i] << " ";
    Msg << "predicate(s) are not met";
    report_fatal_error(Msg.str().c_str());
  }
#endif // NDEBUG
}

} // namespace llvm::Lanai_MC

#endif // ENABLE_INSTR_PREDICATE_VERIFIER

#ifdef GET_INSTRMAP_INFO
#undef GET_INSTRMAP_INFO

namespace llvm::Lanai {

enum PostEncoderMethod {
  PostEncoderMethod_adjustPqBitsSpls
};

// splsIdempotent
LLVM_READONLY
int splsIdempotent(uint16_t Opcode) {
  using namespace Lanai;
  static constexpr uint16_t Table[][2] = {
    { LDBs_RI, LDBs_RI },
    { LDBz_RI, LDBz_RI },
    { LDHs_RI, LDHs_RI },
    { LDHz_RI, LDHz_RI },
    { STB_RI, STB_RI },
    { STH_RI, STH_RI },
  }; // End of Table

  unsigned mid;
  unsigned start = 0;
  unsigned end = 6;
  while (start < end) {
    mid = start + (end - start) / 2;
    if (Opcode == Table[mid][0]) 
      break;
    if (Opcode < Table[mid][0])
      end = mid;
    else
      start = mid + 1;
  }
  if (start == end)
    return -1; // Instruction doesn't exist in this table.

  return Table[mid][1];
}


} // namespace llvm::Lanai

#endif // GET_INSTRMAP_INFO

