/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the Mips target                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 44;
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_v2s16,
  GILLT_v2s64,
  GILLT_v4s8,
  GILLT_v4s32,
  GILLT_v8s16,
  GILLT_v16s8,
};
const static size_t NumTypeObjects = 9;
const static LLT TypeObjects[] = {
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::vector(ElementCount::getFixed(2), 16),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(4), 8),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(16), 8),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_IsPTR64bitBit = 23,
  Feature_UseCompactBranchesBit = 40,
  Feature_HasMips2Bit = 7,
  Feature_HasMips3Bit = 17,
  Feature_HasMips4_32Bit = 26,
  Feature_NotMips4_32Bit = 27,
  Feature_HasMips4_32r2Bit = 18,
  Feature_HasMips32Bit = 3,
  Feature_HasMips32r2Bit = 6,
  Feature_HasMips32r6Bit = 28,
  Feature_NotMips32r6Bit = 4,
  Feature_IsGP64bitBit = 21,
  Feature_HasMips64Bit = 24,
  Feature_HasMips64r2Bit = 22,
  Feature_HasMips64r6Bit = 29,
  Feature_NotMips64r6Bit = 5,
  Feature_InMips16ModeBit = 30,
  Feature_NotInMips16ModeBit = 0,
  Feature_HasCnMipsBit = 25,
  Feature_NotCnMipsBit = 8,
  Feature_IsSym32Bit = 37,
  Feature_IsSym64Bit = 38,
  Feature_IsN64Bit = 39,
  Feature_RelocNotPICBit = 9,
  Feature_RelocPICBit = 36,
  Feature_NoNaNsFPMathBit = 20,
  Feature_UseAbsBit = 14,
  Feature_HasStdEncBit = 1,
  Feature_NotDSPBit = 11,
  Feature_InMicroMipsBit = 34,
  Feature_NotInMicroMipsBit = 2,
  Feature_IsLEBit = 42,
  Feature_IsBEBit = 43,
  Feature_HasEVABit = 35,
  Feature_HasMSABit = 33,
  Feature_HasMadd4Bit = 19,
  Feature_UseIndirectJumpsHazardBit = 12,
  Feature_NoIndirectJumpGuardsBit = 10,
  Feature_AllowFPOpFusionBit = 41,
  Feature_IsFP64bitBit = 16,
  Feature_NotFP64bitBit = 15,
  Feature_IsNotSoftFloatBit = 13,
  Feature_HasDSPBit = 31,
  Feature_HasDSPR2Bit = 32,
};

PredicateBitset MipsInstructionSelector::
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
  PredicateBitset Features{};
  if (Subtarget->isABI_N64())
    Features.set(Feature_IsPTR64bitBit);
  if (Subtarget->useCompactBranches())
    Features.set(Feature_UseCompactBranchesBit);
  if (Subtarget->hasMips2())
    Features.set(Feature_HasMips2Bit);
  if (Subtarget->hasMips3())
    Features.set(Feature_HasMips3Bit);
  if (Subtarget->hasMips4_32())
    Features.set(Feature_HasMips4_32Bit);
  if (!Subtarget->hasMips4_32())
    Features.set(Feature_NotMips4_32Bit);
  if (Subtarget->hasMips4_32r2())
    Features.set(Feature_HasMips4_32r2Bit);
  if (Subtarget->hasMips32())
    Features.set(Feature_HasMips32Bit);
  if (Subtarget->hasMips32r2())
    Features.set(Feature_HasMips32r2Bit);
  if (Subtarget->hasMips32r6())
    Features.set(Feature_HasMips32r6Bit);
  if (!Subtarget->hasMips32r6())
    Features.set(Feature_NotMips32r6Bit);
  if (Subtarget->isGP64bit())
    Features.set(Feature_IsGP64bitBit);
  if (Subtarget->hasMips64())
    Features.set(Feature_HasMips64Bit);
  if (Subtarget->hasMips64r2())
    Features.set(Feature_HasMips64r2Bit);
  if (Subtarget->hasMips64r6())
    Features.set(Feature_HasMips64r6Bit);
  if (!Subtarget->hasMips64r6())
    Features.set(Feature_NotMips64r6Bit);
  if (Subtarget->inMips16Mode())
    Features.set(Feature_InMips16ModeBit);
  if (!Subtarget->inMips16Mode())
    Features.set(Feature_NotInMips16ModeBit);
  if (Subtarget->hasCnMips())
    Features.set(Feature_HasCnMipsBit);
  if (!Subtarget->hasCnMips())
    Features.set(Feature_NotCnMipsBit);
  if (Subtarget->hasSym32())
    Features.set(Feature_IsSym32Bit);
  if (!Subtarget->hasSym32())
    Features.set(Feature_IsSym64Bit);
  if (Subtarget->isABI_N64())
    Features.set(Feature_IsN64Bit);
  if (!TM.isPositionIndependent())
    Features.set(Feature_RelocNotPICBit);
  if (TM.isPositionIndependent())
    Features.set(Feature_RelocPICBit);
  if (TM.Options.NoNaNsFPMath)
    Features.set(Feature_NoNaNsFPMathBit);
  if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
    Features.set(Feature_UseAbsBit);
  if (Subtarget->hasStandardEncoding())
    Features.set(Feature_HasStdEncBit);
  if (!Subtarget->hasDSP())
    Features.set(Feature_NotDSPBit);
  if (Subtarget->inMicroMipsMode())
    Features.set(Feature_InMicroMipsBit);
  if (!Subtarget->inMicroMipsMode())
    Features.set(Feature_NotInMicroMipsBit);
  if (Subtarget->isLittle())
    Features.set(Feature_IsLEBit);
  if (!Subtarget->isLittle())
    Features.set(Feature_IsBEBit);
  if (Subtarget->hasEVA())
    Features.set(Feature_HasEVABit);
  if (Subtarget->hasMSA())
    Features.set(Feature_HasMSABit);
  if (!Subtarget->disableMadd4())
    Features.set(Feature_HasMadd4Bit);
  if (Subtarget->useIndirectJumpsHazard())
    Features.set(Feature_UseIndirectJumpsHazardBit);
  if (!Subtarget->useIndirectJumpsHazard())
    Features.set(Feature_NoIndirectJumpGuardsBit);
  if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
    Features.set(Feature_AllowFPOpFusionBit);
  if (Subtarget->isFP64bit())
    Features.set(Feature_IsFP64bitBit);
  if (!Subtarget->isFP64bit())
    Features.set(Feature_NotFP64bitBit);
  if (!Subtarget->useSoftFloat())
    Features.set(Feature_IsNotSoftFloatBit);
  if (Subtarget->hasDSP())
    Features.set(Feature_HasDSPBit);
  if (Subtarget->hasDSPR2())
    Features.set(Feature_HasDSPR2Bit);
  return Features;
}

void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset MipsInstructionSelector::
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features{};
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_HasCnMips,
  GIFBS_HasDSP,
  GIFBS_HasDSPR2,
  GIFBS_HasMSA,
  GIFBS_InMicroMips,
  GIFBS_InMips16Mode,
  GIFBS_IsFP64bit,
  GIFBS_NotFP64bit,
  GIFBS_NotInMips16Mode,
  GIFBS_HasDSP_InMicroMips,
  GIFBS_HasDSP_NotInMicroMips,
  GIFBS_HasDSPR2_InMicroMips,
  GIFBS_HasMSA_HasStdEnc,
  GIFBS_HasMSA_IsBE,
  GIFBS_HasMSA_IsLE,
  GIFBS_HasMips32r6_HasStdEnc,
  GIFBS_HasMips32r6_InMicroMips,
  GIFBS_HasMips64r2_HasStdEnc,
  GIFBS_HasMips64r6_HasStdEnc,
  GIFBS_HasStdEnc_IsNotSoftFloat,
  GIFBS_HasStdEnc_NotInMicroMips,
  GIFBS_HasStdEnc_NotMips4_32,
  GIFBS_InMicroMips_IsFP64bit,
  GIFBS_InMicroMips_IsNotSoftFloat,
  GIFBS_InMicroMips_NotFP64bit,
  GIFBS_InMicroMips_NotMips32r6,
  GIFBS_IsGP64bit_NotInMips16Mode,
  GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
  GIFBS_HasMSA_HasMips64_HasStdEnc,
  GIFBS_HasMips3_HasStdEnc_IsGP64bit,
  GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r2_HasStdEnc_IsGP64bit,
  GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
  GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
  GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
  GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
  GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
  GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
  GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
  GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
  GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
  GIFBS_InMicroMips_NotMips32r6_RelocPIC,
  GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
  GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
  GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6,
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
  GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6,
  GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
  GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
  GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
  GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches,
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
  GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6,
  GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
  GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
  GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
  GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
  GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
  GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
  GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_HasCnMipsBit, },
  {Feature_HasDSPBit, },
  {Feature_HasDSPR2Bit, },
  {Feature_HasMSABit, },
  {Feature_InMicroMipsBit, },
  {Feature_InMips16ModeBit, },
  {Feature_IsFP64bitBit, },
  {Feature_NotFP64bitBit, },
  {Feature_NotInMips16ModeBit, },
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
  {Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
  {Feature_HasMSABit, Feature_HasStdEncBit, },
  {Feature_HasMSABit, Feature_IsBEBit, },
  {Feature_HasMSABit, Feature_IsLEBit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
  {Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
  {Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
  {Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
  {Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
  {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
  {Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_UseCompactBranchesBit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
  {Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
  {Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
};
// See constructor for table contents

MipsInstructionSelector::ComplexMatcherMemFn
MipsInstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
};

// PatFrag predicates.
enum {
  GICXXPred_MI_Predicate_or_disjoint = GICXXPred_Invalid + 1,
};
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  switch (PredicateID) {
  case GICXXPred_MI_Predicate_or_disjoint: {
    
        return MI.getFlag(MachineInstr::Disjoint);
      
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
bool MipsInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
  const auto &Operands = State.RecordedOperands;
  Register Reg = MO.getReg();
  (void)Operands;
  (void)Reg;
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_immLi16 = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_immSExt6,
  GICXXPred_I64_Predicate_immSExt10,
  GICXXPred_I64_Predicate_immSExtAddiur2,
  GICXXPred_I64_Predicate_immSExtAddius5,
  GICXXPred_I64_Predicate_immZExt1,
  GICXXPred_I64_Predicate_immZExt1Ptr,
  GICXXPred_I64_Predicate_immZExt2,
  GICXXPred_I64_Predicate_immZExt2Lsa,
  GICXXPred_I64_Predicate_immZExt2Ptr,
  GICXXPred_I64_Predicate_immZExt2Shift,
  GICXXPred_I64_Predicate_immZExt3,
  GICXXPred_I64_Predicate_immZExt3Ptr,
  GICXXPred_I64_Predicate_immZExt4,
  GICXXPred_I64_Predicate_immZExt4Ptr,
  GICXXPred_I64_Predicate_immZExt5,
  GICXXPred_I64_Predicate_immZExt5_64,
  GICXXPred_I64_Predicate_immZExt6,
  GICXXPred_I64_Predicate_immZExt8,
  GICXXPred_I64_Predicate_immZExt10,
  GICXXPred_I64_Predicate_immZExtAndi16,
  GICXXPred_I64_Predicate_immi32Cst7,
  GICXXPred_I64_Predicate_immi32Cst15,
  GICXXPred_I64_Predicate_immi32Cst31,
  GICXXPred_I64_Predicate_timmSExt6,
  GICXXPred_I64_Predicate_timmZExt1,
  GICXXPred_I64_Predicate_timmZExt1Ptr,
  GICXXPred_I64_Predicate_timmZExt2,
  GICXXPred_I64_Predicate_timmZExt2Ptr,
  GICXXPred_I64_Predicate_timmZExt3,
  GICXXPred_I64_Predicate_timmZExt3Ptr,
  GICXXPred_I64_Predicate_timmZExt4,
  GICXXPred_I64_Predicate_timmZExt4Ptr,
  GICXXPred_I64_Predicate_timmZExt5,
  GICXXPred_I64_Predicate_timmZExt6,
  GICXXPred_I64_Predicate_timmZExt8,
  GICXXPred_I64_Predicate_timmZExt10,
};
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_immLi16: {
    return Imm >= -1 && Imm <= 126;
  }
  case GICXXPred_I64_Predicate_immSExt6: {
    return isInt<6>(Imm);
  }
  case GICXXPred_I64_Predicate_immSExt10: {
    return isInt<10>(Imm);
  }
  case GICXXPred_I64_Predicate_immSExtAddiur2: {
    return Imm == 1 || Imm == -1 ||
                                               ((Imm % 4 == 0) &&
                                                Imm < 28 && Imm > 0);
  }
  case GICXXPred_I64_Predicate_immSExtAddius5: {
    return Imm >= -8 && Imm <= 7;
  }
  case GICXXPred_I64_Predicate_immZExt1: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt1Ptr: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2Lsa: {
    return isUInt<2>(Imm - 1);
  }
  case GICXXPred_I64_Predicate_immZExt2Ptr: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt2Shift: {
    return Imm >= 1 && Imm <= 8;
  }
  case GICXXPred_I64_Predicate_immZExt3: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt3Ptr: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt4: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt4Ptr: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt5: {
    return Imm == (Imm & 0x1f);
  }
  case GICXXPred_I64_Predicate_immZExt5_64: {
     return Imm == (Imm & 0x1f); 
  }
  case GICXXPred_I64_Predicate_immZExt6: {
    return Imm == (Imm & 0x3f);
  }
  case GICXXPred_I64_Predicate_immZExt8: {
    return isUInt<8>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExt10: {
    return isUInt<10>(Imm);
  }
  case GICXXPred_I64_Predicate_immZExtAndi16: {
    return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
                Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
                Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
  }
  case GICXXPred_I64_Predicate_immi32Cst7: {
    return isUInt<32>(Imm) && Imm == 7;
  }
  case GICXXPred_I64_Predicate_immi32Cst15: {
    return isUInt<32>(Imm) && Imm == 15;
  }
  case GICXXPred_I64_Predicate_immi32Cst31: {
    return isUInt<32>(Imm) && Imm == 31;
  }
  case GICXXPred_I64_Predicate_timmSExt6: {
    return isInt<6>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt1: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt1Ptr: {
    return isUInt<1>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt2: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt2Ptr: {
    return isUInt<2>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt3: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt3Ptr: {
    return isUInt<3>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt4: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt4Ptr: {
    return isUInt<4>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt5: {
    return Imm == (Imm & 0x1f);
  }
  case GICXXPred_I64_Predicate_timmZExt6: {
    return Imm == (Imm & 0x3f);
  }
  case GICXXPred_I64_Predicate_timmZExt8: {
    return isUInt<8>(Imm);
  }
  case GICXXPred_I64_Predicate_timmZExt10: {
    return isUInt<10>(Imm);
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APInt_Predicate_imm32SExt16 = GICXXPred_Invalid + 1,
  GICXXPred_APInt_Predicate_imm32ZExt16,
};
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APInt_Predicate_imm32SExt16: {
     return isInt<16>(Imm.getSExtValue()); 
  }
  case GICXXPred_APInt_Predicate_imm32ZExt16: {
    
      return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
bool MipsInstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("MipsInstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
};
MipsInstructionSelector::CustomRendererFn
MipsInstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
};

bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

bool MipsInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("MipsInstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24),  uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
#else
#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32),  uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
#endif
const uint8_t *MipsInstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
     /*     0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(301), /*)*//*default:*//*Label 84*/ GIMT_Encode4(76993),
     /*    10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(994),
     /*    14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(2292),
     /*    18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(2983),
     /*    22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(3464),
     /*    26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(3733),
     /*    30 */ /*TargetOpcode::G_SREM*//*Label 5*/ GIMT_Encode4(4002),
     /*    34 */ /*TargetOpcode::G_UREM*//*Label 6*/ GIMT_Encode4(4271), GIMT_Encode4(0), GIMT_Encode4(0),
     /*    46 */ /*TargetOpcode::G_AND*//*Label 7*/ GIMT_Encode4(4540),
     /*    50 */ /*TargetOpcode::G_OR*//*Label 8*/ GIMT_Encode4(5096),
     /*    54 */ /*TargetOpcode::G_XOR*//*Label 9*/ GIMT_Encode4(5500), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   118 */ /*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ GIMT_Encode4(6392),
     /*   122 */ /*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ GIMT_Encode4(6465), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   142 */ /*TargetOpcode::G_BITCAST*//*Label 12*/ GIMT_Encode4(6806), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   186 */ /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(11117),
     /*   190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(11182),
     /*   194 */ /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(11250), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   222 */ /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(11318),
     /*   226 */ /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(11510),
     /*   230 */ /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(11680),
     /*   234 */ /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(11850),
     /*   238 */ /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(12020),
     /*   242 */ /*TargetOpcode::G_ATOMICRMW_NAND*//*Label 21*/ GIMT_Encode4(12190),
     /*   246 */ /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(12360),
     /*   250 */ /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(12530),
     /*   254 */ /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(12700),
     /*   258 */ /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(12870),
     /*   262 */ /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(13040),
     /*   266 */ /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(13210), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   318 */ /*TargetOpcode::G_BRCOND*//*Label 28*/ GIMT_Encode4(13380), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   330 */ /*TargetOpcode::G_INTRINSIC*//*Label 29*/ GIMT_Encode4(19925),
     /*   334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 30*/ GIMT_Encode4(34190), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   346 */ /*TargetOpcode::G_ANYEXT*//*Label 31*/ GIMT_Encode4(39284),
     /*   350 */ /*TargetOpcode::G_TRUNC*//*Label 32*/ GIMT_Encode4(39350), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   366 */ /*TargetOpcode::G_CONSTANT*//*Label 33*/ GIMT_Encode4(39414), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   382 */ /*TargetOpcode::G_SEXT*//*Label 34*/ GIMT_Encode4(39475),
     /*   386 */ /*TargetOpcode::G_SEXT_INREG*//*Label 35*/ GIMT_Encode4(40939),
     /*   390 */ /*TargetOpcode::G_ZEXT*//*Label 36*/ GIMT_Encode4(41287),
     /*   394 */ /*TargetOpcode::G_SHL*//*Label 37*/ GIMT_Encode4(41488),
     /*   398 */ /*TargetOpcode::G_LSHR*//*Label 38*/ GIMT_Encode4(43285),
     /*   402 */ /*TargetOpcode::G_ASHR*//*Label 39*/ GIMT_Encode4(45082), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   414 */ /*TargetOpcode::G_ROTR*//*Label 40*/ GIMT_Encode4(46837), GIMT_Encode4(0),
     /*   422 */ /*TargetOpcode::G_ICMP*//*Label 41*/ GIMT_Encode4(47125),
     /*   426 */ /*TargetOpcode::G_FCMP*//*Label 42*/ GIMT_Encode4(49656), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   438 */ /*TargetOpcode::G_SELECT*//*Label 43*/ GIMT_Encode4(50656), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   482 */ /*TargetOpcode::G_UMULH*//*Label 44*/ GIMT_Encode4(62786),
     /*   486 */ /*TargetOpcode::G_SMULH*//*Label 45*/ GIMT_Encode4(62895), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   546 */ /*TargetOpcode::G_FADD*//*Label 46*/ GIMT_Encode4(63004),
     /*   550 */ /*TargetOpcode::G_FSUB*//*Label 47*/ GIMT_Encode4(64299),
     /*   554 */ /*TargetOpcode::G_FMUL*//*Label 48*/ GIMT_Encode4(65114),
     /*   558 */ /*TargetOpcode::G_FMA*//*Label 49*/ GIMT_Encode4(65625), GIMT_Encode4(0),
     /*   566 */ /*TargetOpcode::G_FDIV*//*Label 50*/ GIMT_Encode4(65731), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   590 */ /*TargetOpcode::G_FEXP2*//*Label 51*/ GIMT_Encode4(66054), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   602 */ /*TargetOpcode::G_FLOG2*//*Label 52*/ GIMT_Encode4(66132), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   618 */ /*TargetOpcode::G_FNEG*//*Label 53*/ GIMT_Encode4(66210),
     /*   622 */ /*TargetOpcode::G_FPEXT*//*Label 54*/ GIMT_Encode4(71115),
     /*   626 */ /*TargetOpcode::G_FPTRUNC*//*Label 55*/ GIMT_Encode4(71309),
     /*   630 */ /*TargetOpcode::G_FPTOSI*//*Label 56*/ GIMT_Encode4(71488),
     /*   634 */ /*TargetOpcode::G_FPTOUI*//*Label 57*/ GIMT_Encode4(71566),
     /*   638 */ /*TargetOpcode::G_SITOFP*//*Label 58*/ GIMT_Encode4(71644),
     /*   642 */ /*TargetOpcode::G_UITOFP*//*Label 59*/ GIMT_Encode4(71897), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   654 */ /*TargetOpcode::G_FABS*//*Label 60*/ GIMT_Encode4(71975), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   666 */ /*TargetOpcode::G_FCANONICALIZE*//*Label 61*/ GIMT_Encode4(72223),
     /*   670 */ /*TargetOpcode::G_FMINNUM*//*Label 62*/ GIMT_Encode4(72297),
     /*   674 */ /*TargetOpcode::G_FMAXNUM*//*Label 63*/ GIMT_Encode4(72369),
     /*   678 */ /*TargetOpcode::G_FMINNUM_IEEE*//*Label 64*/ GIMT_Encode4(72441),
     /*   682 */ /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 65*/ GIMT_Encode4(72513), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   742 */ /*TargetOpcode::G_SMIN*//*Label 66*/ GIMT_Encode4(72585),
     /*   746 */ /*TargetOpcode::G_SMAX*//*Label 67*/ GIMT_Encode4(72753),
     /*   750 */ /*TargetOpcode::G_UMIN*//*Label 68*/ GIMT_Encode4(72921),
     /*   754 */ /*TargetOpcode::G_UMAX*//*Label 69*/ GIMT_Encode4(73089), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   770 */ /*TargetOpcode::G_BR*//*Label 70*/ GIMT_Encode4(73257), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   790 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 71*/ GIMT_Encode4(73381),
     /*   794 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 72*/ GIMT_Encode4(73945), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   822 */ /*TargetOpcode::G_CTLZ*//*Label 73*/ GIMT_Encode4(73997), GIMT_Encode4(0),
     /*   830 */ /*TargetOpcode::G_CTPOP*//*Label 74*/ GIMT_Encode4(74502),
     /*   834 */ /*TargetOpcode::G_BSWAP*//*Label 75*/ GIMT_Encode4(74708), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   890 */ /*TargetOpcode::G_FSQRT*//*Label 76*/ GIMT_Encode4(74872), GIMT_Encode4(0),
     /*   898 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(75136), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   930 */ /*TargetOpcode::G_STRICT_FADD*//*Label 78*/ GIMT_Encode4(75214),
     /*   934 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 79*/ GIMT_Encode4(76069),
     /*   938 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 80*/ GIMT_Encode4(76566),
     /*   942 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 81*/ GIMT_Encode4(76699), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   954 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 82*/ GIMT_Encode4(76832), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
     /*   990 */ /*TargetOpcode::G_TRAP*//*Label 83*/ GIMT_Encode4(76947),
     /*   994 */ // Label 0: @994
     /*   994 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 93*/ GIMT_Encode4(2291),
     /*  1005 */ /*GILLT_s32*//*Label 85*/ GIMT_Encode4(1037),
     /*  1009 */ /*GILLT_s64*//*Label 86*/ GIMT_Encode4(1445),
     /*  1013 */ /*GILLT_v2s16*//*Label 87*/ GIMT_Encode4(1611),
     /*  1017 */ /*GILLT_v2s64*//*Label 88*/ GIMT_Encode4(1643),
     /*  1021 */ /*GILLT_v4s8*//*Label 89*/ GIMT_Encode4(1797),
     /*  1025 */ /*GILLT_v4s32*//*Label 90*/ GIMT_Encode4(1829),
     /*  1029 */ /*GILLT_v8s16*//*Label 91*/ GIMT_Encode4(1983),
     /*  1033 */ /*GILLT_v16s8*//*Label 92*/ GIMT_Encode4(2137),
     /*  1037 */ // Label 85: @1037
     /*  1037 */ GIM_Try, /*On fail goto*//*Label 94*/ GIMT_Encode4(1444),
     /*  1042 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  1045 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  1048 */   GIM_Try, /*On fail goto*//*Label 95*/ GIMT_Encode4(1115), // Rule ID 2561 //
     /*  1053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1056 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  1064 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  1068 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  1072 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  1076 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1081 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  1085 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1089 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
     /*  1093 */     // MIs[2] Operand 1
     /*  1093 */     // No operand predicates
     /*  1093 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1097 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  1099 */     // (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt)  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
     /*  1099 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
     /*  1102 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  1104 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  1108 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /*  1110 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
     /*  1113 */     GIR_RootConstrainSelectedInstOperands,
     /*  1114 */     // GIR_Coverage, 2561,
     /*  1114 */     GIR_EraseRootFromParent_Done,
     /*  1115 */   // Label 95: @1115
     /*  1115 */   GIM_Try, /*On fail goto*//*Label 96*/ GIMT_Encode4(1182), // Rule ID 909 //
     /*  1120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1123 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1131 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1135 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  1139 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  1143 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  1147 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1152 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  1156 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1160 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
     /*  1164 */     // MIs[2] Operand 1
     /*  1164 */     // No operand predicates
     /*  1164 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  1166 */     // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
     /*  1166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LSA),
     /*  1169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  1171 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  1175 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /*  1177 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
     /*  1180 */     GIR_RootConstrainSelectedInstOperands,
     /*  1181 */     // GIR_Coverage, 909,
     /*  1181 */     GIR_EraseRootFromParent_Done,
     /*  1182 */   // Label 96: @1182
     /*  1182 */   GIM_Try, /*On fail goto*//*Label 97*/ GIMT_Encode4(1224), // Rule ID 40 //
     /*  1187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  1190 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1194 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1198 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1202 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1206 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32SExt16),
     /*  1210 */     // MIs[1] Operand 1
     /*  1210 */     // No operand predicates
     /*  1210 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1212 */     // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16)  =>  (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
     /*  1212 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDiu),
     /*  1215 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  1217 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  1219 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
     /*  1222 */     GIR_RootConstrainSelectedInstOperands,
     /*  1223 */     // GIR_Coverage, 40,
     /*  1223 */     GIR_EraseRootFromParent_Done,
     /*  1224 */   // Label 97: @1224
     /*  1224 */   GIM_Try, /*On fail goto*//*Label 98*/ GIMT_Encode4(1266), // Rule ID 2296 //
     /*  1229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /*  1232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1240 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1244 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1248 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddiur2),
     /*  1252 */     // MIs[1] Operand 1
     /*  1252 */     // No operand predicates
     /*  1252 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1254 */     // (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)  =>  (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
     /*  1254 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUR2_MM),
     /*  1257 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  1259 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  1261 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /*  1264 */     GIR_RootConstrainSelectedInstOperands,
     /*  1265 */     // GIR_Coverage, 2296,
     /*  1265 */     GIR_EraseRootFromParent_Done,
     /*  1266 */   // Label 98: @1266
     /*  1266 */   GIM_Try, /*On fail goto*//*Label 99*/ GIMT_Encode4(1308), // Rule ID 2297 //
     /*  1271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /*  1274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1278 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1282 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1286 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1290 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExtAddius5),
     /*  1294 */     // MIs[1] Operand 1
     /*  1294 */     // No operand predicates
     /*  1294 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1296 */     // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)  =>  (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
     /*  1296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDIUS5_MM),
     /*  1299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  1301 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  1303 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /*  1306 */     GIR_RootConstrainSelectedInstOperands,
     /*  1307 */     // GIR_Coverage, 2297,
     /*  1307 */     GIR_EraseRootFromParent_Done,
     /*  1308 */   // Label 99: @1308
     /*  1308 */   GIM_Try, /*On fail goto*//*Label 100*/ GIMT_Encode4(1335), // Rule ID 1283 //
     /*  1313 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  1316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1320 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1328 */     // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  1328 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MMR6),
     /*  1333 */     GIR_RootConstrainSelectedInstOperands,
     /*  1334 */     // GIR_Coverage, 1283,
     /*  1334 */     GIR_Done,
     /*  1335 */   // Label 100: @1335
     /*  1335 */   GIM_Try, /*On fail goto*//*Label 101*/ GIMT_Encode4(1362), // Rule ID 46 //
     /*  1340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  1343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1355 */     // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  1355 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu),
     /*  1360 */     GIR_RootConstrainSelectedInstOperands,
     /*  1361 */     // GIR_Coverage, 46,
     /*  1361 */     GIR_Done,
     /*  1362 */   // Label 101: @1362
     /*  1362 */   GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(1389), // Rule ID 1135 //
     /*  1367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  1370 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1374 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  1382 */     // (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  1382 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU16_MM),
     /*  1387 */     GIR_RootConstrainSelectedInstOperands,
     /*  1388 */     // GIR_Coverage, 1135,
     /*  1388 */     GIR_Done,
     /*  1389 */   // Label 102: @1389
     /*  1389 */   GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1416), // Rule ID 1147 //
     /*  1394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  1397 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  1409 */     // (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  1409 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDu_MM),
     /*  1414 */     GIR_RootConstrainSelectedInstOperands,
     /*  1415 */     // GIR_Coverage, 1147,
     /*  1415 */     GIR_Done,
     /*  1416 */   // Label 103: @1416
     /*  1416 */   GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1443), // Rule ID 1954 //
     /*  1421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  1424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  1428 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  1432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  1436 */     // (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  1436 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AdduRxRyRz16),
     /*  1441 */     GIR_RootConstrainSelectedInstOperands,
     /*  1442 */     // GIR_Coverage, 1954,
     /*  1442 */     GIR_Done,
     /*  1443 */   // Label 104: @1443
     /*  1443 */   GIM_Reject,
     /*  1444 */ // Label 94: @1444
     /*  1444 */ GIM_Reject,
     /*  1445 */ // Label 86: @1445
     /*  1445 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1610),
     /*  1450 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  1453 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  1456 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1460 */   GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1523), // Rule ID 2562 //
     /*  1465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
     /*  1468 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  1472 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  1476 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  1480 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  1484 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1489 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  1493 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1497 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
     /*  1501 */     // MIs[2] Operand 1
     /*  1501 */     // No operand predicates
     /*  1501 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1505 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  1507 */     // (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt)  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
     /*  1507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
     /*  1510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  1512 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  1516 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /*  1518 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
     /*  1521 */     GIR_RootConstrainSelectedInstOperands,
     /*  1522 */     // GIR_Coverage, 2562,
     /*  1522 */     GIR_EraseRootFromParent_Done,
     /*  1523 */   // Label 106: @1523
     /*  1523 */   GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1586), // Rule ID 910 //
     /*  1528 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
     /*  1531 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1535 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1539 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /*  1543 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  1547 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  1551 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1556 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /*  1560 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  1564 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Lsa),
     /*  1568 */     // MIs[2] Operand 1
     /*  1568 */     // No operand predicates
     /*  1568 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /*  1570 */     // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa))  =>  (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
     /*  1570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DLSA),
     /*  1573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  1575 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  1579 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /*  1581 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
     /*  1584 */     GIR_RootConstrainSelectedInstOperands,
     /*  1585 */     // GIR_Coverage, 910,
     /*  1585 */     GIR_EraseRootFromParent_Done,
     /*  1586 */   // Label 107: @1586
     /*  1586 */   GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1609), // Rule ID 277 //
     /*  1591 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /*  1594 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  1602 */     // (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  1602 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DADDu),
     /*  1607 */     GIR_RootConstrainSelectedInstOperands,
     /*  1608 */     // GIR_Coverage, 277,
     /*  1608 */     GIR_Done,
     /*  1609 */   // Label 108: @1609
     /*  1609 */   GIM_Reject,
     /*  1610 */ // Label 105: @1610
     /*  1610 */ GIM_Reject,
     /*  1611 */ // Label 87: @1611
     /*  1611 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1642), // Rule ID 2053 //
     /*  1616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  1619 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*  1622 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  1625 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  1629 */   // (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /*  1629 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
     /*  1634 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
     /*  1640 */   GIR_RootConstrainSelectedInstOperands,
     /*  1641 */   // GIR_Coverage, 2053,
     /*  1641 */   GIR_Done,
     /*  1642 */ // Label 109: @1642
     /*  1642 */ GIM_Reject,
     /*  1643 */ // Label 88: @1643
     /*  1643 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1796),
     /*  1648 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  1651 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  1654 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1658 */   GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1715), // Rule ID 2566 //
     /*  1663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1666 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  1670 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  1674 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  1678 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  1682 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1687 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1696 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1698 */     // (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in)  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  1698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
     /*  1701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  1703 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /*  1705 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  1709 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  1713 */     GIR_RootConstrainSelectedInstOperands,
     /*  1714 */     // GIR_Coverage, 2566,
     /*  1714 */     GIR_EraseRootFromParent_Done,
     /*  1715 */   // Label 111: @1715
     /*  1715 */   GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1772), // Rule ID 918 //
     /*  1720 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1723 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1727 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1731 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  1735 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  1739 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  1743 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1748 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1753 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1755 */     // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  1755 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_D),
     /*  1758 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  1760 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  1762 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  1766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  1770 */     GIR_RootConstrainSelectedInstOperands,
     /*  1771 */     // GIR_Coverage, 918,
     /*  1771 */     GIR_EraseRootFromParent_Done,
     /*  1772 */   // Label 112: @1772
     /*  1772 */   GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(1795), // Rule ID 585 //
     /*  1777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1780 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  1788 */     // (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  1788 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_D),
     /*  1793 */     GIR_RootConstrainSelectedInstOperands,
     /*  1794 */     // GIR_Coverage, 585,
     /*  1794 */     GIR_Done,
     /*  1795 */   // Label 113: @1795
     /*  1795 */   GIM_Reject,
     /*  1796 */ // Label 110: @1796
     /*  1796 */ GIM_Reject,
     /*  1797 */ // Label 89: @1797
     /*  1797 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(1828), // Rule ID 2059 //
     /*  1802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  1805 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /*  1808 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /*  1811 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  1815 */   // (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
     /*  1815 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
     /*  1820 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
     /*  1826 */   GIR_RootConstrainSelectedInstOperands,
     /*  1827 */   // GIR_Coverage, 2059,
     /*  1827 */   GIR_Done,
     /*  1828 */ // Label 114: @1828
     /*  1828 */ GIM_Reject,
     /*  1829 */ // Label 90: @1829
     /*  1829 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(1982),
     /*  1834 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  1837 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  1840 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1844 */   GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1901), // Rule ID 2565 //
     /*  1849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1852 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  1856 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  1860 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  1864 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  1868 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1873 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1882 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1884 */     // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in)  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  1884 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
     /*  1887 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  1889 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /*  1891 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  1895 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  1899 */     GIR_RootConstrainSelectedInstOperands,
     /*  1900 */     // GIR_Coverage, 2565,
     /*  1900 */     GIR_EraseRootFromParent_Done,
     /*  1901 */   // Label 116: @1901
     /*  1901 */   GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(1958), // Rule ID 917 //
     /*  1906 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1909 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1913 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  1917 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  1921 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  1925 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  1929 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1934 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1939 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  1941 */     // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  1941 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_W),
     /*  1944 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  1946 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  1948 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  1952 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  1956 */     GIR_RootConstrainSelectedInstOperands,
     /*  1957 */     // GIR_Coverage, 917,
     /*  1957 */     GIR_EraseRootFromParent_Done,
     /*  1958 */   // Label 117: @1958
     /*  1958 */   GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(1981), // Rule ID 584 //
     /*  1963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  1966 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1970 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  1974 */     // (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  1974 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_W),
     /*  1979 */     GIR_RootConstrainSelectedInstOperands,
     /*  1980 */     // GIR_Coverage, 584,
     /*  1980 */     GIR_Done,
     /*  1981 */   // Label 118: @1981
     /*  1981 */   GIM_Reject,
     /*  1982 */ // Label 115: @1982
     /*  1982 */ GIM_Reject,
     /*  1983 */ // Label 91: @1983
     /*  1983 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2136),
     /*  1988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  1991 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  1994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  1998 */   GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2055), // Rule ID 2564 //
     /*  2003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2006 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  2010 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2014 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  2018 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  2022 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2027 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2032 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2036 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2038 */     // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in)  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  2038 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
     /*  2041 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2043 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /*  2045 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2049 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2053 */     GIR_RootConstrainSelectedInstOperands,
     /*  2054 */     // GIR_Coverage, 2564,
     /*  2054 */     GIR_EraseRootFromParent_Done,
     /*  2055 */   // Label 120: @2055
     /*  2055 */   GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2112), // Rule ID 916 //
     /*  2060 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2063 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2067 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2071 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2075 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  2079 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  2083 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2088 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2093 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2095 */     // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  2095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_H),
     /*  2098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2100 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2102 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2106 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2110 */     GIR_RootConstrainSelectedInstOperands,
     /*  2111 */     // GIR_Coverage, 916,
     /*  2111 */     GIR_EraseRootFromParent_Done,
     /*  2112 */   // Label 121: @2112
     /*  2112 */   GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2135), // Rule ID 583 //
     /*  2117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2120 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2128 */     // (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  2128 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_H),
     /*  2133 */     GIR_RootConstrainSelectedInstOperands,
     /*  2134 */     // GIR_Coverage, 583,
     /*  2134 */     GIR_Done,
     /*  2135 */   // Label 122: @2135
     /*  2135 */   GIM_Reject,
     /*  2136 */ // Label 119: @2136
     /*  2136 */ GIM_Reject,
     /*  2137 */ // Label 92: @2137
     /*  2137 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(2290),
     /*  2142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  2145 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  2148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2152 */   GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(2209), // Rule ID 2563 //
     /*  2157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2160 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  2164 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2168 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  2172 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  2176 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2181 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2186 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2190 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2192 */     // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  2192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
     /*  2195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2197 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /*  2199 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2203 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2207 */     GIR_RootConstrainSelectedInstOperands,
     /*  2208 */     // GIR_Coverage, 2563,
     /*  2208 */     GIR_EraseRootFromParent_Done,
     /*  2209 */   // Label 124: @2209
     /*  2209 */   GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(2266), // Rule ID 915 //
     /*  2214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2217 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2221 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2225 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2229 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  2233 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  2237 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2242 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2247 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2249 */     // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  2249 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDV_B),
     /*  2252 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2254 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2256 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2260 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2264 */     GIR_RootConstrainSelectedInstOperands,
     /*  2265 */     // GIR_Coverage, 915,
     /*  2265 */     GIR_EraseRootFromParent_Done,
     /*  2266 */   // Label 125: @2266
     /*  2266 */   GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(2289), // Rule ID 582 //
     /*  2271 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2278 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2282 */     // (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  2282 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ADDV_B),
     /*  2287 */     GIR_RootConstrainSelectedInstOperands,
     /*  2288 */     // GIR_Coverage, 582,
     /*  2288 */     GIR_Done,
     /*  2289 */   // Label 126: @2289
     /*  2289 */   GIM_Reject,
     /*  2290 */ // Label 123: @2290
     /*  2290 */ GIM_Reject,
     /*  2291 */ // Label 93: @2291
     /*  2291 */ GIM_Reject,
     /*  2292 */ // Label 1: @2292
     /*  2292 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 135*/ GIMT_Encode4(2982),
     /*  2303 */ /*GILLT_s32*//*Label 127*/ GIMT_Encode4(2335),
     /*  2307 */ /*GILLT_s64*//*Label 128*/ GIMT_Encode4(2512),
     /*  2311 */ /*GILLT_v2s16*//*Label 129*/ GIMT_Encode4(2546),
     /*  2315 */ /*GILLT_v2s64*//*Label 130*/ GIMT_Encode4(2578),
     /*  2319 */ /*GILLT_v4s8*//*Label 131*/ GIMT_Encode4(2671),
     /*  2323 */ /*GILLT_v4s32*//*Label 132*/ GIMT_Encode4(2703),
     /*  2327 */ /*GILLT_v8s16*//*Label 133*/ GIMT_Encode4(2796),
     /*  2331 */ /*GILLT_v16s8*//*Label 134*/ GIMT_Encode4(2889),
     /*  2335 */ // Label 127: @2335
     /*  2335 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(2511),
     /*  2340 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  2343 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  2346 */   GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(2375), // Rule ID 1953 //
     /*  2351 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  2354 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  2358 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
     /*  2362 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  2366 */     // (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r)  =>  (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
     /*  2366 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NegRxRy16),
     /*  2369 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /*  2371 */     GIR_RootToRootCopy, /*OpIdx*/2, // r
     /*  2373 */     GIR_RootConstrainSelectedInstOperands,
     /*  2374 */     // GIR_Coverage, 1953,
     /*  2374 */     GIR_EraseRootFromParent_Done,
     /*  2375 */   // Label 137: @2375
     /*  2375 */   GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(2402), // Rule ID 1285 //
     /*  2380 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  2383 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2387 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2391 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2395 */     // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  2395 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MMR6),
     /*  2400 */     GIR_RootConstrainSelectedInstOperands,
     /*  2401 */     // GIR_Coverage, 1285,
     /*  2401 */     GIR_Done,
     /*  2402 */   // Label 138: @2402
     /*  2402 */   GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(2429), // Rule ID 47 //
     /*  2407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  2410 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2414 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2418 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2422 */     // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  2422 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu),
     /*  2427 */     GIR_RootConstrainSelectedInstOperands,
     /*  2428 */     // GIR_Coverage, 47,
     /*  2428 */     GIR_Done,
     /*  2429 */   // Label 139: @2429
     /*  2429 */   GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(2456), // Rule ID 1139 //
     /*  2434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  2437 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2441 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2445 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  2449 */     // (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  2449 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU16_MM),
     /*  2454 */     GIR_RootConstrainSelectedInstOperands,
     /*  2455 */     // GIR_Coverage, 1139,
     /*  2455 */     GIR_Done,
     /*  2456 */   // Label 140: @2456
     /*  2456 */   GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(2483), // Rule ID 1148 //
     /*  2461 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  2464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2468 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2472 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  2476 */     // (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  2476 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBu_MM),
     /*  2481 */     GIR_RootConstrainSelectedInstOperands,
     /*  2482 */     // GIR_Coverage, 1148,
     /*  2482 */     GIR_Done,
     /*  2483 */   // Label 141: @2483
     /*  2483 */   GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(2510), // Rule ID 1958 //
     /*  2488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  2491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  2495 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  2499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  2503 */     // (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  2503 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SubuRxRyRz16),
     /*  2508 */     GIR_RootConstrainSelectedInstOperands,
     /*  2509 */     // GIR_Coverage, 1958,
     /*  2509 */     GIR_Done,
     /*  2510 */   // Label 142: @2510
     /*  2510 */   GIM_Reject,
     /*  2511 */ // Label 136: @2511
     /*  2511 */ GIM_Reject,
     /*  2512 */ // Label 128: @2512
     /*  2512 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(2545), // Rule ID 278 //
     /*  2517 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /*  2520 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  2523 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  2526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  2530 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  2534 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  2538 */   // (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  2538 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSUBu),
     /*  2543 */   GIR_RootConstrainSelectedInstOperands,
     /*  2544 */   // GIR_Coverage, 278,
     /*  2544 */   GIR_Done,
     /*  2545 */ // Label 143: @2545
     /*  2545 */ GIM_Reject,
     /*  2546 */ // Label 129: @2546
     /*  2546 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(2577), // Rule ID 2055 //
     /*  2551 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  2554 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*  2557 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  2560 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  2564 */   // (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /*  2564 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
     /*  2569 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
     /*  2575 */   GIR_RootConstrainSelectedInstOperands,
     /*  2576 */   // GIR_Coverage, 2055,
     /*  2576 */   GIR_Done,
     /*  2577 */ // Label 144: @2577
     /*  2577 */ GIM_Reject,
     /*  2578 */ // Label 130: @2578
     /*  2578 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(2670),
     /*  2583 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  2586 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  2589 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  2593 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  2597 */   GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(2650), // Rule ID 974 //
     /*  2602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2605 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2609 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2613 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  2617 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  2621 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  2626 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  2631 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2633 */     // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt))  =>  (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  2633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_D),
     /*  2636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2638 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2640 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2644 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2648 */     GIR_RootConstrainSelectedInstOperands,
     /*  2649 */     // GIR_Coverage, 974,
     /*  2649 */     GIR_EraseRootFromParent_Done,
     /*  2650 */   // Label 146: @2650
     /*  2650 */   GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(2669), // Rule ID 1103 //
     /*  2655 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  2662 */     // (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  2662 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_D),
     /*  2667 */     GIR_RootConstrainSelectedInstOperands,
     /*  2668 */     // GIR_Coverage, 1103,
     /*  2668 */     GIR_Done,
     /*  2669 */   // Label 147: @2669
     /*  2669 */   GIM_Reject,
     /*  2670 */ // Label 145: @2670
     /*  2670 */ GIM_Reject,
     /*  2671 */ // Label 131: @2671
     /*  2671 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(2702), // Rule ID 2061 //
     /*  2676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  2679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /*  2682 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /*  2685 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  2689 */   // (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
     /*  2689 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
     /*  2694 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag20), GIMT_Encode2(RegState::Dead),
     /*  2700 */   GIR_RootConstrainSelectedInstOperands,
     /*  2701 */   // GIR_Coverage, 2061,
     /*  2701 */   GIR_Done,
     /*  2702 */ // Label 148: @2702
     /*  2702 */ GIM_Reject,
     /*  2703 */ // Label 132: @2703
     /*  2703 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(2795),
     /*  2708 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  2711 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  2714 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  2718 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  2722 */   GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(2775), // Rule ID 973 //
     /*  2727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2730 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2734 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2738 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  2742 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  2746 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  2751 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  2756 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2758 */     // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt))  =>  (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  2758 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_W),
     /*  2761 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2763 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2765 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2769 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2773 */     GIR_RootConstrainSelectedInstOperands,
     /*  2774 */     // GIR_Coverage, 973,
     /*  2774 */     GIR_EraseRootFromParent_Done,
     /*  2775 */   // Label 150: @2775
     /*  2775 */   GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(2794), // Rule ID 1102 //
     /*  2780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2783 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  2787 */     // (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  2787 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_W),
     /*  2792 */     GIR_RootConstrainSelectedInstOperands,
     /*  2793 */     // GIR_Coverage, 1102,
     /*  2793 */     GIR_Done,
     /*  2794 */   // Label 151: @2794
     /*  2794 */   GIM_Reject,
     /*  2795 */ // Label 149: @2795
     /*  2795 */ GIM_Reject,
     /*  2796 */ // Label 133: @2796
     /*  2796 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(2888),
     /*  2801 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  2804 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  2807 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2811 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2815 */   GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(2868), // Rule ID 972 //
     /*  2820 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2823 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2827 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2831 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  2835 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  2839 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2844 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2849 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2851 */     // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt))  =>  (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  2851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_H),
     /*  2854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2856 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2858 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2862 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2866 */     GIR_RootConstrainSelectedInstOperands,
     /*  2867 */     // GIR_Coverage, 972,
     /*  2867 */     GIR_EraseRootFromParent_Done,
     /*  2868 */   // Label 153: @2868
     /*  2868 */   GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(2887), // Rule ID 1101 //
     /*  2873 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2876 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  2880 */     // (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  2880 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_H),
     /*  2885 */     GIR_RootConstrainSelectedInstOperands,
     /*  2886 */     // GIR_Coverage, 1101,
     /*  2886 */     GIR_Done,
     /*  2887 */   // Label 154: @2887
     /*  2887 */   GIM_Reject,
     /*  2888 */ // Label 152: @2888
     /*  2888 */ GIM_Reject,
     /*  2889 */ // Label 134: @2889
     /*  2889 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(2981),
     /*  2894 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  2897 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  2900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2904 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2908 */   GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(2961), // Rule ID 971 //
     /*  2913 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2916 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  2920 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /*  2924 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  2928 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  2932 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2937 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2942 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  2944 */     // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt))  =>  (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  2944 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBV_B),
     /*  2947 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  2949 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /*  2951 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /*  2955 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /*  2959 */     GIR_RootConstrainSelectedInstOperands,
     /*  2960 */     // GIR_Coverage, 971,
     /*  2960 */     GIR_EraseRootFromParent_Done,
     /*  2961 */   // Label 156: @2961
     /*  2961 */   GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(2980), // Rule ID 1100 //
     /*  2966 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  2969 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  2973 */     // (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  2973 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SUBV_B),
     /*  2978 */     GIR_RootConstrainSelectedInstOperands,
     /*  2979 */     // GIR_Coverage, 1100,
     /*  2979 */     GIR_Done,
     /*  2980 */   // Label 157: @2980
     /*  2980 */   GIM_Reject,
     /*  2981 */ // Label 155: @2981
     /*  2981 */ GIM_Reject,
     /*  2982 */ // Label 135: @2982
     /*  2982 */ GIM_Reject,
     /*  2983 */ // Label 2: @2983
     /*  2983 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 165*/ GIMT_Encode4(3463),
     /*  2994 */ /*GILLT_s32*//*Label 158*/ GIMT_Encode4(3026),
     /*  2998 */ /*GILLT_s64*//*Label 159*/ GIMT_Encode4(3210),
     /*  3002 */ /*GILLT_v2s16*//*Label 160*/ GIMT_Encode4(3295),
     /*  3006 */ /*GILLT_v2s64*//*Label 161*/ GIMT_Encode4(3327), GIMT_Encode4(0),
     /*  3014 */ /*GILLT_v4s32*//*Label 162*/ GIMT_Encode4(3361),
     /*  3018 */ /*GILLT_v8s16*//*Label 163*/ GIMT_Encode4(3395),
     /*  3022 */ /*GILLT_v16s8*//*Label 164*/ GIMT_Encode4(3429),
     /*  3026 */ // Label 158: @3026
     /*  3026 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(3209),
     /*  3031 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  3034 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  3037 */   GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(3076), // Rule ID 48 //
     /*  3042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /*  3045 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3049 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3057 */     // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3057 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL),
     /*  3062 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
     /*  3068 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
     /*  3074 */     GIR_RootConstrainSelectedInstOperands,
     /*  3075 */     // GIR_Coverage, 48,
     /*  3075 */     GIR_Done,
     /*  3076 */   // Label 167: @3076
     /*  3076 */   GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(3103), // Rule ID 407 //
     /*  3081 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /*  3084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3088 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3092 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3096 */     // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3096 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
     /*  3101 */     GIR_RootConstrainSelectedInstOperands,
     /*  3102 */     // GIR_Coverage, 407,
     /*  3102 */     GIR_Done,
     /*  3103 */   // Label 168: @3103
     /*  3103 */   GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(3142), // Rule ID 1149 //
     /*  3108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  3111 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3115 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3123 */     // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3123 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MM),
     /*  3128 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
     /*  3134 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
     /*  3140 */     GIR_RootConstrainSelectedInstOperands,
     /*  3141 */     // GIR_Coverage, 1149,
     /*  3141 */     GIR_Done,
     /*  3142 */   // Label 169: @3142
     /*  3142 */   GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(3169), // Rule ID 1254 //
     /*  3147 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  3150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3154 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3158 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3162 */     // (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3162 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_MMR6),
     /*  3167 */     GIR_RootConstrainSelectedInstOperands,
     /*  3168 */     // GIR_Coverage, 1254,
     /*  3168 */     GIR_Done,
     /*  3169 */   // Label 170: @3169
     /*  3169 */   GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(3208), // Rule ID 1956 //
     /*  3174 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  3177 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  3181 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  3185 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  3189 */     // (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  3189 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MultRxRyRz16),
     /*  3194 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
     /*  3200 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
     /*  3206 */     GIR_RootConstrainSelectedInstOperands,
     /*  3207 */     // GIR_Coverage, 1956,
     /*  3207 */     GIR_Done,
     /*  3208 */   // Label 171: @3208
     /*  3208 */   GIM_Reject,
     /*  3209 */ // Label 166: @3209
     /*  3209 */ GIM_Reject,
     /*  3210 */ // Label 159: @3210
     /*  3210 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(3294),
     /*  3215 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  3218 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  3221 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3225 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3229 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3233 */   GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(3278), // Rule ID 349 //
     /*  3238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /*  3241 */     // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  3241 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL),
     /*  3246 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::HI0), GIMT_Encode2(RegState::Dead),
     /*  3252 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::LO0), GIMT_Encode2(RegState::Dead),
     /*  3258 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P0), GIMT_Encode2(RegState::Dead),
     /*  3264 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P1), GIMT_Encode2(RegState::Dead),
     /*  3270 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::P2), GIMT_Encode2(RegState::Dead),
     /*  3276 */     GIR_RootConstrainSelectedInstOperands,
     /*  3277 */     // GIR_Coverage, 349,
     /*  3277 */     GIR_Done,
     /*  3278 */   // Label 173: @3278
     /*  3278 */   GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(3293), // Rule ID 422 //
     /*  3283 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /*  3286 */     // (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  3286 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUL_R6),
     /*  3291 */     GIR_RootConstrainSelectedInstOperands,
     /*  3292 */     // GIR_Coverage, 422,
     /*  3292 */     GIR_Done,
     /*  3293 */   // Label 174: @3293
     /*  3293 */   GIM_Reject,
     /*  3294 */ // Label 172: @3294
     /*  3294 */ GIM_Reject,
     /*  3295 */ // Label 160: @3295
     /*  3295 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(3326), // Rule ID 2057 //
     /*  3300 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /*  3303 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*  3306 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /*  3309 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  3313 */   // (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /*  3313 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
     /*  3318 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::DSPOutFlag21), GIMT_Encode2(RegState::Dead),
     /*  3324 */   GIR_RootConstrainSelectedInstOperands,
     /*  3325 */   // GIR_Coverage, 2057,
     /*  3325 */   GIR_Done,
     /*  3326 */ // Label 175: @3326
     /*  3326 */ GIM_Reject,
     /*  3327 */ // Label 161: @3327
     /*  3327 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(3360), // Rule ID 982 //
     /*  3332 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3335 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  3338 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  3341 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3345 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3349 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3353 */   // (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  3353 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_D),
     /*  3358 */   GIR_RootConstrainSelectedInstOperands,
     /*  3359 */   // GIR_Coverage, 982,
     /*  3359 */   GIR_Done,
     /*  3360 */ // Label 176: @3360
     /*  3360 */ GIM_Reject,
     /*  3361 */ // Label 162: @3361
     /*  3361 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(3394), // Rule ID 981 //
     /*  3366 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3369 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  3372 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  3375 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3379 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3383 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3387 */   // (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  3387 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_W),
     /*  3392 */   GIR_RootConstrainSelectedInstOperands,
     /*  3393 */   // GIR_Coverage, 981,
     /*  3393 */   GIR_Done,
     /*  3394 */ // Label 177: @3394
     /*  3394 */ GIM_Reject,
     /*  3395 */ // Label 163: @3395
     /*  3395 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(3428), // Rule ID 980 //
     /*  3400 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  3406 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  3409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3413 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3417 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3421 */   // (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  3421 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_H),
     /*  3426 */   GIR_RootConstrainSelectedInstOperands,
     /*  3427 */   // GIR_Coverage, 980,
     /*  3427 */   GIR_Done,
     /*  3428 */ // Label 178: @3428
     /*  3428 */ GIM_Reject,
     /*  3429 */ // Label 164: @3429
     /*  3429 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(3462), // Rule ID 979 //
     /*  3434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  3440 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  3443 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3447 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3451 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3455 */   // (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  3455 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MULV_B),
     /*  3460 */   GIR_RootConstrainSelectedInstOperands,
     /*  3461 */   // GIR_Coverage, 979,
     /*  3461 */   GIR_Done,
     /*  3462 */ // Label 179: @3462
     /*  3462 */ GIM_Reject,
     /*  3463 */ // Label 165: @3463
     /*  3463 */ GIM_Reject,
     /*  3464 */ // Label 3: @3464
     /*  3464 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 186*/ GIMT_Encode4(3732),
     /*  3475 */ /*GILLT_s32*//*Label 180*/ GIMT_Encode4(3507),
     /*  3479 */ /*GILLT_s64*//*Label 181*/ GIMT_Encode4(3562), GIMT_Encode4(0),
     /*  3487 */ /*GILLT_v2s64*//*Label 182*/ GIMT_Encode4(3596), GIMT_Encode4(0),
     /*  3495 */ /*GILLT_v4s32*//*Label 183*/ GIMT_Encode4(3630),
     /*  3499 */ /*GILLT_v8s16*//*Label 184*/ GIMT_Encode4(3664),
     /*  3503 */ /*GILLT_v16s8*//*Label 185*/ GIMT_Encode4(3698),
     /*  3507 */ // Label 180: @3507
     /*  3507 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(3561),
     /*  3512 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  3515 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  3518 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3522 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3526 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3530 */   GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(3545), // Rule ID 401 //
     /*  3535 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /*  3538 */     // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3538 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV),
     /*  3543 */     GIR_RootConstrainSelectedInstOperands,
     /*  3544 */     // GIR_Coverage, 401,
     /*  3544 */     GIR_Done,
     /*  3545 */   // Label 188: @3545
     /*  3545 */   GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(3560), // Rule ID 1247 //
     /*  3550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  3553 */     // (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3553 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_MMR6),
     /*  3558 */     GIR_RootConstrainSelectedInstOperands,
     /*  3559 */     // GIR_Coverage, 1247,
     /*  3559 */     GIR_Done,
     /*  3560 */   // Label 189: @3560
     /*  3560 */   GIM_Reject,
     /*  3561 */ // Label 187: @3561
     /*  3561 */ GIM_Reject,
     /*  3562 */ // Label 181: @3562
     /*  3562 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(3595), // Rule ID 416 //
     /*  3567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /*  3570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  3573 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  3576 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3580 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3584 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3588 */   // (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  3588 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIV),
     /*  3593 */   GIR_RootConstrainSelectedInstOperands,
     /*  3594 */   // GIR_Coverage, 416,
     /*  3594 */   GIR_Done,
     /*  3595 */ // Label 190: @3595
     /*  3595 */ GIM_Reject,
     /*  3596 */ // Label 182: @3596
     /*  3596 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(3629), // Rule ID 722 //
     /*  3601 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3604 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  3607 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  3610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3614 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3618 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3622 */   // (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  3622 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_D),
     /*  3627 */   GIR_RootConstrainSelectedInstOperands,
     /*  3628 */   // GIR_Coverage, 722,
     /*  3628 */   GIR_Done,
     /*  3629 */ // Label 191: @3629
     /*  3629 */ GIM_Reject,
     /*  3630 */ // Label 183: @3630
     /*  3630 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(3663), // Rule ID 721 //
     /*  3635 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3638 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  3641 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  3644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3648 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3652 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3656 */   // (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  3656 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_W),
     /*  3661 */   GIR_RootConstrainSelectedInstOperands,
     /*  3662 */   // GIR_Coverage, 721,
     /*  3662 */   GIR_Done,
     /*  3663 */ // Label 192: @3663
     /*  3663 */ GIM_Reject,
     /*  3664 */ // Label 184: @3664
     /*  3664 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(3697), // Rule ID 720 //
     /*  3669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  3675 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  3678 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3682 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3686 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3690 */   // (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  3690 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_H),
     /*  3695 */   GIR_RootConstrainSelectedInstOperands,
     /*  3696 */   // GIR_Coverage, 720,
     /*  3696 */   GIR_Done,
     /*  3697 */ // Label 193: @3697
     /*  3697 */ GIM_Reject,
     /*  3698 */ // Label 185: @3698
     /*  3698 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(3731), // Rule ID 719 //
     /*  3703 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3706 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  3709 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  3712 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3716 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3720 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3724 */   // (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  3724 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_S_B),
     /*  3729 */   GIR_RootConstrainSelectedInstOperands,
     /*  3730 */   // GIR_Coverage, 719,
     /*  3730 */   GIR_Done,
     /*  3731 */ // Label 194: @3731
     /*  3731 */ GIM_Reject,
     /*  3732 */ // Label 186: @3732
     /*  3732 */ GIM_Reject,
     /*  3733 */ // Label 4: @3733
     /*  3733 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 201*/ GIMT_Encode4(4001),
     /*  3744 */ /*GILLT_s32*//*Label 195*/ GIMT_Encode4(3776),
     /*  3748 */ /*GILLT_s64*//*Label 196*/ GIMT_Encode4(3831), GIMT_Encode4(0),
     /*  3756 */ /*GILLT_v2s64*//*Label 197*/ GIMT_Encode4(3865), GIMT_Encode4(0),
     /*  3764 */ /*GILLT_v4s32*//*Label 198*/ GIMT_Encode4(3899),
     /*  3768 */ /*GILLT_v8s16*//*Label 199*/ GIMT_Encode4(3933),
     /*  3772 */ /*GILLT_v16s8*//*Label 200*/ GIMT_Encode4(3967),
     /*  3776 */ // Label 195: @3776
     /*  3776 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(3830),
     /*  3781 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  3784 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  3787 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3791 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3795 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  3799 */   GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(3814), // Rule ID 402 //
     /*  3804 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /*  3807 */     // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3807 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU),
     /*  3812 */     GIR_RootConstrainSelectedInstOperands,
     /*  3813 */     // GIR_Coverage, 402,
     /*  3813 */     GIR_Done,
     /*  3814 */   // Label 203: @3814
     /*  3814 */   GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(3829), // Rule ID 1248 //
     /*  3819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  3822 */     // (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  3822 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIVU_MMR6),
     /*  3827 */     GIR_RootConstrainSelectedInstOperands,
     /*  3828 */     // GIR_Coverage, 1248,
     /*  3828 */     GIR_Done,
     /*  3829 */   // Label 204: @3829
     /*  3829 */   GIM_Reject,
     /*  3830 */ // Label 202: @3830
     /*  3830 */ GIM_Reject,
     /*  3831 */ // Label 196: @3831
     /*  3831 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(3864), // Rule ID 417 //
     /*  3836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /*  3839 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  3842 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  3845 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3849 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3853 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  3857 */   // (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  3857 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DDIVU),
     /*  3862 */   GIR_RootConstrainSelectedInstOperands,
     /*  3863 */   // GIR_Coverage, 417,
     /*  3863 */   GIR_Done,
     /*  3864 */ // Label 205: @3864
     /*  3864 */ GIM_Reject,
     /*  3865 */ // Label 197: @3865
     /*  3865 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(3898), // Rule ID 726 //
     /*  3870 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3873 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  3876 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  3879 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3883 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3887 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  3891 */   // (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  3891 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_D),
     /*  3896 */   GIR_RootConstrainSelectedInstOperands,
     /*  3897 */   // GIR_Coverage, 726,
     /*  3897 */   GIR_Done,
     /*  3898 */ // Label 206: @3898
     /*  3898 */ GIM_Reject,
     /*  3899 */ // Label 198: @3899
     /*  3899 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(3932), // Rule ID 725 //
     /*  3904 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3907 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  3910 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  3913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3917 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3921 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  3925 */   // (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  3925 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_W),
     /*  3930 */   GIR_RootConstrainSelectedInstOperands,
     /*  3931 */   // GIR_Coverage, 725,
     /*  3931 */   GIR_Done,
     /*  3932 */ // Label 207: @3932
     /*  3932 */ GIM_Reject,
     /*  3933 */ // Label 199: @3933
     /*  3933 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(3966), // Rule ID 724 //
     /*  3938 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3941 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  3944 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  3947 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3951 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3955 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  3959 */   // (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  3959 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_H),
     /*  3964 */   GIR_RootConstrainSelectedInstOperands,
     /*  3965 */   // GIR_Coverage, 724,
     /*  3965 */   GIR_Done,
     /*  3966 */ // Label 208: @3966
     /*  3966 */ GIM_Reject,
     /*  3967 */ // Label 200: @3967
     /*  3967 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(4000), // Rule ID 723 //
     /*  3972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  3975 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  3978 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  3981 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3985 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3989 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  3993 */   // (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  3993 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DIV_U_B),
     /*  3998 */   GIR_RootConstrainSelectedInstOperands,
     /*  3999 */   // GIR_Coverage, 723,
     /*  3999 */   GIR_Done,
     /*  4000 */ // Label 209: @4000
     /*  4000 */ GIM_Reject,
     /*  4001 */ // Label 201: @4001
     /*  4001 */ GIM_Reject,
     /*  4002 */ // Label 5: @4002
     /*  4002 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 216*/ GIMT_Encode4(4270),
     /*  4013 */ /*GILLT_s32*//*Label 210*/ GIMT_Encode4(4045),
     /*  4017 */ /*GILLT_s64*//*Label 211*/ GIMT_Encode4(4100), GIMT_Encode4(0),
     /*  4025 */ /*GILLT_v2s64*//*Label 212*/ GIMT_Encode4(4134), GIMT_Encode4(0),
     /*  4033 */ /*GILLT_v4s32*//*Label 213*/ GIMT_Encode4(4168),
     /*  4037 */ /*GILLT_v8s16*//*Label 214*/ GIMT_Encode4(4202),
     /*  4041 */ /*GILLT_v16s8*//*Label 215*/ GIMT_Encode4(4236),
     /*  4045 */ // Label 210: @4045
     /*  4045 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(4099),
     /*  4050 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  4053 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  4056 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4060 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4064 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4068 */   GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(4083), // Rule ID 403 //
     /*  4073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /*  4076 */     // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4076 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD),
     /*  4081 */     GIR_RootConstrainSelectedInstOperands,
     /*  4082 */     // GIR_Coverage, 403,
     /*  4082 */     GIR_Done,
     /*  4083 */   // Label 218: @4083
     /*  4083 */   GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(4098), // Rule ID 1252 //
     /*  4088 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  4091 */     // (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4091 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_MMR6),
     /*  4096 */     GIR_RootConstrainSelectedInstOperands,
     /*  4097 */     // GIR_Coverage, 1252,
     /*  4097 */     GIR_Done,
     /*  4098 */   // Label 219: @4098
     /*  4098 */   GIM_Reject,
     /*  4099 */ // Label 217: @4099
     /*  4099 */ GIM_Reject,
     /*  4100 */ // Label 211: @4100
     /*  4100 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(4133), // Rule ID 418 //
     /*  4105 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /*  4108 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  4111 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  4114 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4118 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4122 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4126 */   // (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  4126 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMOD),
     /*  4131 */   GIR_RootConstrainSelectedInstOperands,
     /*  4132 */   // GIR_Coverage, 418,
     /*  4132 */   GIR_Done,
     /*  4133 */ // Label 220: @4133
     /*  4133 */ GIM_Reject,
     /*  4134 */ // Label 212: @4134
     /*  4134 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(4167), // Rule ID 962 //
     /*  4139 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  4145 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  4148 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4152 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4156 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4160 */   // (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  4160 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_D),
     /*  4165 */   GIR_RootConstrainSelectedInstOperands,
     /*  4166 */   // GIR_Coverage, 962,
     /*  4166 */   GIR_Done,
     /*  4167 */ // Label 221: @4167
     /*  4167 */ GIM_Reject,
     /*  4168 */ // Label 213: @4168
     /*  4168 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(4201), // Rule ID 961 //
     /*  4173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  4179 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  4182 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4186 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4190 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4194 */   // (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  4194 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_W),
     /*  4199 */   GIR_RootConstrainSelectedInstOperands,
     /*  4200 */   // GIR_Coverage, 961,
     /*  4200 */   GIR_Done,
     /*  4201 */ // Label 222: @4201
     /*  4201 */ GIM_Reject,
     /*  4202 */ // Label 214: @4202
     /*  4202 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(4235), // Rule ID 960 //
     /*  4207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4210 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  4213 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  4216 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4220 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4224 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4228 */   // (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  4228 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_H),
     /*  4233 */   GIR_RootConstrainSelectedInstOperands,
     /*  4234 */   // GIR_Coverage, 960,
     /*  4234 */   GIR_Done,
     /*  4235 */ // Label 223: @4235
     /*  4235 */ GIM_Reject,
     /*  4236 */ // Label 215: @4236
     /*  4236 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(4269), // Rule ID 959 //
     /*  4241 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4244 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  4247 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  4250 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4254 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4258 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4262 */   // (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  4262 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_S_B),
     /*  4267 */   GIR_RootConstrainSelectedInstOperands,
     /*  4268 */   // GIR_Coverage, 959,
     /*  4268 */   GIR_Done,
     /*  4269 */ // Label 224: @4269
     /*  4269 */ GIM_Reject,
     /*  4270 */ // Label 216: @4270
     /*  4270 */ GIM_Reject,
     /*  4271 */ // Label 6: @4271
     /*  4271 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 231*/ GIMT_Encode4(4539),
     /*  4282 */ /*GILLT_s32*//*Label 225*/ GIMT_Encode4(4314),
     /*  4286 */ /*GILLT_s64*//*Label 226*/ GIMT_Encode4(4369), GIMT_Encode4(0),
     /*  4294 */ /*GILLT_v2s64*//*Label 227*/ GIMT_Encode4(4403), GIMT_Encode4(0),
     /*  4302 */ /*GILLT_v4s32*//*Label 228*/ GIMT_Encode4(4437),
     /*  4306 */ /*GILLT_v8s16*//*Label 229*/ GIMT_Encode4(4471),
     /*  4310 */ /*GILLT_v16s8*//*Label 230*/ GIMT_Encode4(4505),
     /*  4314 */ // Label 225: @4314
     /*  4314 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(4368),
     /*  4319 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  4322 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  4325 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4329 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4333 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4337 */   GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(4352), // Rule ID 404 //
     /*  4342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /*  4345 */     // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4345 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU),
     /*  4350 */     GIR_RootConstrainSelectedInstOperands,
     /*  4351 */     // GIR_Coverage, 404,
     /*  4351 */     GIR_Done,
     /*  4352 */   // Label 233: @4352
     /*  4352 */   GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(4367), // Rule ID 1253 //
     /*  4357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  4360 */     // (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4360 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MODU_MMR6),
     /*  4365 */     GIR_RootConstrainSelectedInstOperands,
     /*  4366 */     // GIR_Coverage, 1253,
     /*  4366 */     GIR_Done,
     /*  4367 */   // Label 234: @4367
     /*  4367 */   GIM_Reject,
     /*  4368 */ // Label 232: @4368
     /*  4368 */ GIM_Reject,
     /*  4369 */ // Label 226: @4369
     /*  4369 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(4402), // Rule ID 419 //
     /*  4374 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /*  4377 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  4380 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  4383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4387 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4391 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4395 */   // (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  4395 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMODU),
     /*  4400 */   GIR_RootConstrainSelectedInstOperands,
     /*  4401 */   // GIR_Coverage, 419,
     /*  4401 */   GIR_Done,
     /*  4402 */ // Label 235: @4402
     /*  4402 */ GIM_Reject,
     /*  4403 */ // Label 227: @4403
     /*  4403 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(4436), // Rule ID 966 //
     /*  4408 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4411 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  4414 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  4417 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4421 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4425 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4429 */   // (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  4429 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_D),
     /*  4434 */   GIR_RootConstrainSelectedInstOperands,
     /*  4435 */   // GIR_Coverage, 966,
     /*  4435 */   GIR_Done,
     /*  4436 */ // Label 236: @4436
     /*  4436 */ GIM_Reject,
     /*  4437 */ // Label 228: @4437
     /*  4437 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(4470), // Rule ID 965 //
     /*  4442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4445 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  4448 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  4451 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4455 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4459 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  4463 */   // (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  4463 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_W),
     /*  4468 */   GIR_RootConstrainSelectedInstOperands,
     /*  4469 */   // GIR_Coverage, 965,
     /*  4469 */   GIR_Done,
     /*  4470 */ // Label 237: @4470
     /*  4470 */ GIM_Reject,
     /*  4471 */ // Label 229: @4471
     /*  4471 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(4504), // Rule ID 964 //
     /*  4476 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4479 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  4482 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  4485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4489 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4493 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  4497 */   // (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  4497 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_H),
     /*  4502 */   GIR_RootConstrainSelectedInstOperands,
     /*  4503 */   // GIR_Coverage, 964,
     /*  4503 */   GIR_Done,
     /*  4504 */ // Label 238: @4504
     /*  4504 */ GIM_Reject,
     /*  4505 */ // Label 230: @4505
     /*  4505 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(4538), // Rule ID 963 //
     /*  4510 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4513 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  4516 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  4519 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4523 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4527 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  4531 */   // (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  4531 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MOD_U_B),
     /*  4536 */   GIR_RootConstrainSelectedInstOperands,
     /*  4537 */   // GIR_Coverage, 963,
     /*  4537 */   GIR_Done,
     /*  4538 */ // Label 239: @4538
     /*  4538 */ GIM_Reject,
     /*  4539 */ // Label 231: @4539
     /*  4539 */ GIM_Reject,
     /*  4540 */ // Label 7: @4540
     /*  4540 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 246*/ GIMT_Encode4(5095),
     /*  4551 */ /*GILLT_s32*//*Label 240*/ GIMT_Encode4(4583),
     /*  4555 */ /*GILLT_s64*//*Label 241*/ GIMT_Encode4(4857), GIMT_Encode4(0),
     /*  4563 */ /*GILLT_v2s64*//*Label 242*/ GIMT_Encode4(4959), GIMT_Encode4(0),
     /*  4571 */ /*GILLT_v4s32*//*Label 243*/ GIMT_Encode4(4993),
     /*  4575 */ /*GILLT_v8s16*//*Label 244*/ GIMT_Encode4(5027),
     /*  4579 */ /*GILLT_v16s8*//*Label 245*/ GIMT_Encode4(5061),
     /*  4583 */ // Label 240: @4583
     /*  4583 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(4856),
     /*  4588 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  4591 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  4594 */   GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(4636), // Rule ID 41 //
     /*  4599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  4602 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4606 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4610 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  4614 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  4618 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
     /*  4622 */     // MIs[1] Operand 1
     /*  4622 */     // No operand predicates
     /*  4622 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  4624 */     // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
     /*  4624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDi),
     /*  4627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  4629 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  4631 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
     /*  4634 */     GIR_RootConstrainSelectedInstOperands,
     /*  4635 */     // GIR_Coverage, 41,
     /*  4635 */     GIR_EraseRootFromParent_Done,
     /*  4636 */   // Label 248: @4636
     /*  4636 */   GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(4678), // Rule ID 2299 //
     /*  4641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /*  4644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4648 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4652 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  4656 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  4660 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
     /*  4664 */     // MIs[1] Operand 1
     /*  4664 */     // No operand predicates
     /*  4664 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  4666 */     // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
     /*  4666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MM),
     /*  4669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  4671 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  4673 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /*  4676 */     GIR_RootConstrainSelectedInstOperands,
     /*  4677 */     // GIR_Coverage, 2299,
     /*  4677 */     GIR_EraseRootFromParent_Done,
     /*  4678 */   // Label 249: @4678
     /*  4678 */   GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(4720), // Rule ID 2462 //
     /*  4683 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  4686 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4690 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4694 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  4698 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  4702 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExtAndi16),
     /*  4706 */     // MIs[1] Operand 1
     /*  4706 */     // No operand predicates
     /*  4706 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  4708 */     // (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)  =>  (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
     /*  4708 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ANDI16_MMR6),
     /*  4711 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  4713 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /*  4715 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /*  4718 */     GIR_RootConstrainSelectedInstOperands,
     /*  4719 */     // GIR_Coverage, 2462,
     /*  4719 */     GIR_EraseRootFromParent_Done,
     /*  4720 */   // Label 250: @4720
     /*  4720 */   GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(4747), // Rule ID 51 //
     /*  4725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  4728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4732 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4740 */     // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4740 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND),
     /*  4745 */     GIR_RootConstrainSelectedInstOperands,
     /*  4746 */     // GIR_Coverage, 51,
     /*  4746 */     GIR_Done,
     /*  4747 */   // Label 251: @4747
     /*  4747 */   GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(4774), // Rule ID 1136 //
     /*  4752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  4755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4759 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4763 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  4767 */     // (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  4767 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND16_MM),
     /*  4772 */     GIR_RootConstrainSelectedInstOperands,
     /*  4773 */     // GIR_Coverage, 1136,
     /*  4773 */     GIR_Done,
     /*  4774 */   // Label 252: @4774
     /*  4774 */   GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(4801), // Rule ID 1152 //
     /*  4779 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  4782 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4786 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4790 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4794 */     // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4794 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MM),
     /*  4799 */     GIR_RootConstrainSelectedInstOperands,
     /*  4800 */     // GIR_Coverage, 1152,
     /*  4800 */     GIR_Done,
     /*  4801 */   // Label 253: @4801
     /*  4801 */   GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(4828), // Rule ID 1245 //
     /*  4806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  4809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4813 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  4821 */     // (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  4821 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_MMR6),
     /*  4826 */     GIR_RootConstrainSelectedInstOperands,
     /*  4827 */     // GIR_Coverage, 1245,
     /*  4827 */     GIR_Done,
     /*  4828 */   // Label 254: @4828
     /*  4828 */   GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(4855), // Rule ID 1955 //
     /*  4833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  4836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  4840 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  4844 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  4848 */     // (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  4848 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AndRxRxRy16),
     /*  4853 */     GIR_RootConstrainSelectedInstOperands,
     /*  4854 */     // GIR_Coverage, 1955,
     /*  4854 */     GIR_Done,
     /*  4855 */   // Label 255: @4855
     /*  4855 */   GIM_Reject,
     /*  4856 */ // Label 247: @4856
     /*  4856 */ GIM_Reject,
     /*  4857 */ // Label 241: @4857
     /*  4857 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(4958),
     /*  4862 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  4865 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  4868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4872 */   GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(4934), // Rule ID 344 //
     /*  4877 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /*  4880 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  4884 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /*  4888 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  4892 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  4896 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4901 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4906 */     GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
     /*  4917 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  4919 */     // (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] })  =>  (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  4919 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BADDu),
     /*  4922 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  4924 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  4928 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
     /*  4932 */     GIR_RootConstrainSelectedInstOperands,
     /*  4933 */     // GIR_Coverage, 344,
     /*  4933 */     GIR_EraseRootFromParent_Done,
     /*  4934 */   // Label 257: @4934
     /*  4934 */   GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(4957), // Rule ID 281 //
     /*  4939 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /*  4942 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4946 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  4950 */     // (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  4950 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND64),
     /*  4955 */     GIR_RootConstrainSelectedInstOperands,
     /*  4956 */     // GIR_Coverage, 281,
     /*  4956 */     GIR_Done,
     /*  4957 */   // Label 258: @4957
     /*  4957 */   GIM_Reject,
     /*  4958 */ // Label 256: @4958
     /*  4958 */ GIM_Reject,
     /*  4959 */ // Label 242: @4959
     /*  4959 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(4992), // Rule ID 593 //
     /*  4964 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  4967 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  4970 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  4973 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4977 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4981 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  4985 */   // (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  4985 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_D_PSEUDO),
     /*  4990 */   GIR_RootConstrainSelectedInstOperands,
     /*  4991 */   // GIR_Coverage, 593,
     /*  4991 */   GIR_Done,
     /*  4992 */ // Label 259: @4992
     /*  4992 */ GIM_Reject,
     /*  4993 */ // Label 243: @4993
     /*  4993 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(5026), // Rule ID 592 //
     /*  4998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5001 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  5004 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  5007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5011 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5015 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5019 */   // (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  5019 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_W_PSEUDO),
     /*  5024 */   GIR_RootConstrainSelectedInstOperands,
     /*  5025 */   // GIR_Coverage, 592,
     /*  5025 */   GIR_Done,
     /*  5026 */ // Label 260: @5026
     /*  5026 */ GIM_Reject,
     /*  5027 */ // Label 244: @5027
     /*  5027 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(5060), // Rule ID 591 //
     /*  5032 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5035 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  5038 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  5041 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5045 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5049 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5053 */   // (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  5053 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V_H_PSEUDO),
     /*  5058 */   GIR_RootConstrainSelectedInstOperands,
     /*  5059 */   // GIR_Coverage, 591,
     /*  5059 */   GIR_Done,
     /*  5060 */ // Label 261: @5060
     /*  5060 */ GIM_Reject,
     /*  5061 */ // Label 245: @5061
     /*  5061 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(5094), // Rule ID 590 //
     /*  5066 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5069 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  5072 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  5075 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5079 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5083 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5087 */   // (and:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AND_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  5087 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::AND_V),
     /*  5092 */   GIR_RootConstrainSelectedInstOperands,
     /*  5093 */   // GIR_Coverage, 590,
     /*  5093 */   GIR_Done,
     /*  5094 */ // Label 262: @5094
     /*  5094 */ GIM_Reject,
     /*  5095 */ // Label 246: @5095
     /*  5095 */ GIM_Reject,
     /*  5096 */ // Label 8: @5096
     /*  5096 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 269*/ GIMT_Encode4(5499),
     /*  5107 */ /*GILLT_s32*//*Label 263*/ GIMT_Encode4(5139),
     /*  5111 */ /*GILLT_s64*//*Label 264*/ GIMT_Encode4(5329), GIMT_Encode4(0),
     /*  5119 */ /*GILLT_v2s64*//*Label 265*/ GIMT_Encode4(5363), GIMT_Encode4(0),
     /*  5127 */ /*GILLT_v4s32*//*Label 266*/ GIMT_Encode4(5397),
     /*  5131 */ /*GILLT_v8s16*//*Label 267*/ GIMT_Encode4(5431),
     /*  5135 */ /*GILLT_v16s8*//*Label 268*/ GIMT_Encode4(5465),
     /*  5139 */ // Label 263: @5139
     /*  5139 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(5328),
     /*  5144 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  5147 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  5150 */   GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(5192), // Rule ID 42 //
     /*  5155 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  5158 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5162 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5166 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  5170 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  5174 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
     /*  5178 */     // MIs[1] Operand 1
     /*  5178 */     // No operand predicates
     /*  5178 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  5180 */     // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (ORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
     /*  5180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ORi),
     /*  5183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  5185 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  5187 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
     /*  5190 */     GIR_RootConstrainSelectedInstOperands,
     /*  5191 */     // GIR_Coverage, 42,
     /*  5191 */     GIR_EraseRootFromParent_Done,
     /*  5192 */   // Label 271: @5192
     /*  5192 */   GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(5219), // Rule ID 52 //
     /*  5197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  5200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5204 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5212 */     // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5212 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR),
     /*  5217 */     GIR_RootConstrainSelectedInstOperands,
     /*  5218 */     // GIR_Coverage, 52,
     /*  5218 */     GIR_Done,
     /*  5219 */   // Label 272: @5219
     /*  5219 */   GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(5246), // Rule ID 1138 //
     /*  5224 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  5227 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5231 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5235 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5239 */     // (or:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (OR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  5239 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR16_MM),
     /*  5244 */     GIR_RootConstrainSelectedInstOperands,
     /*  5245 */     // GIR_Coverage, 1138,
     /*  5245 */     GIR_Done,
     /*  5246 */   // Label 273: @5246
     /*  5246 */   GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(5273), // Rule ID 1153 //
     /*  5251 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  5254 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5258 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5262 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5266 */     // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5266 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
     /*  5271 */     GIR_RootConstrainSelectedInstOperands,
     /*  5272 */     // GIR_Coverage, 1153,
     /*  5272 */     GIR_Done,
     /*  5273 */   // Label 274: @5273
     /*  5273 */   GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(5300), // Rule ID 1258 //
     /*  5278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  5281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5285 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5293 */     // (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (OR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5293 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_MMR6),
     /*  5298 */     GIR_RootConstrainSelectedInstOperands,
     /*  5299 */     // GIR_Coverage, 1258,
     /*  5299 */     GIR_Done,
     /*  5300 */   // Label 275: @5300
     /*  5300 */   GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(5327), // Rule ID 1957 //
     /*  5305 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  5308 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  5312 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  5316 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  5320 */     // (or:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (OrRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  5320 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OrRxRxRy16),
     /*  5325 */     GIR_RootConstrainSelectedInstOperands,
     /*  5326 */     // GIR_Coverage, 1957,
     /*  5326 */     GIR_Done,
     /*  5327 */   // Label 276: @5327
     /*  5327 */   GIM_Reject,
     /*  5328 */ // Label 270: @5328
     /*  5328 */ GIM_Reject,
     /*  5329 */ // Label 264: @5329
     /*  5329 */ GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(5362), // Rule ID 282 //
     /*  5334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /*  5337 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  5340 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  5343 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  5347 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  5351 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  5355 */   // (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (OR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  5355 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR64),
     /*  5360 */   GIR_RootConstrainSelectedInstOperands,
     /*  5361 */   // GIR_Coverage, 282,
     /*  5361 */   GIR_Done,
     /*  5362 */ // Label 277: @5362
     /*  5362 */ GIM_Reject,
     /*  5363 */ // Label 265: @5363
     /*  5363 */ GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(5396), // Rule ID 999 //
     /*  5368 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5371 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  5374 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  5377 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  5381 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  5385 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  5389 */   // (or:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (OR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  5389 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_D_PSEUDO),
     /*  5394 */   GIR_RootConstrainSelectedInstOperands,
     /*  5395 */   // GIR_Coverage, 999,
     /*  5395 */   GIR_Done,
     /*  5396 */ // Label 278: @5396
     /*  5396 */ GIM_Reject,
     /*  5397 */ // Label 266: @5397
     /*  5397 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(5430), // Rule ID 998 //
     /*  5402 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5405 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  5408 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  5411 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5415 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5419 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  5423 */   // (or:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (OR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  5423 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_W_PSEUDO),
     /*  5428 */   GIR_RootConstrainSelectedInstOperands,
     /*  5429 */   // GIR_Coverage, 998,
     /*  5429 */   GIR_Done,
     /*  5430 */ // Label 279: @5430
     /*  5430 */ GIM_Reject,
     /*  5431 */ // Label 267: @5431
     /*  5431 */ GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(5464), // Rule ID 997 //
     /*  5436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5439 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  5442 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  5445 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5449 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5453 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  5457 */   // (or:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (OR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  5457 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V_H_PSEUDO),
     /*  5462 */   GIR_RootConstrainSelectedInstOperands,
     /*  5463 */   // GIR_Coverage, 997,
     /*  5463 */   GIR_Done,
     /*  5464 */ // Label 280: @5464
     /*  5464 */ GIM_Reject,
     /*  5465 */ // Label 268: @5465
     /*  5465 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(5498), // Rule ID 996 //
     /*  5470 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  5473 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  5476 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  5479 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5483 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5487 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  5491 */   // (or:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (OR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  5491 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::OR_V),
     /*  5496 */   GIR_RootConstrainSelectedInstOperands,
     /*  5497 */   // GIR_Coverage, 996,
     /*  5497 */   GIR_Done,
     /*  5498 */ // Label 281: @5498
     /*  5498 */ GIM_Reject,
     /*  5499 */ // Label 269: @5499
     /*  5499 */ GIM_Reject,
     /*  5500 */ // Label 9: @5500
     /*  5500 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 288*/ GIMT_Encode4(6391),
     /*  5511 */ /*GILLT_s32*//*Label 282*/ GIMT_Encode4(5543),
     /*  5515 */ /*GILLT_s64*//*Label 283*/ GIMT_Encode4(6160), GIMT_Encode4(0),
     /*  5523 */ /*GILLT_v2s64*//*Label 284*/ GIMT_Encode4(6255), GIMT_Encode4(0),
     /*  5531 */ /*GILLT_v4s32*//*Label 285*/ GIMT_Encode4(6289),
     /*  5535 */ /*GILLT_v8s16*//*Label 286*/ GIMT_Encode4(6323),
     /*  5539 */ /*GILLT_v16s8*//*Label 287*/ GIMT_Encode4(6357),
     /*  5543 */ // Label 282: @5543
     /*  5543 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(6159),
     /*  5548 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  5551 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  5554 */   GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(5613), // Rule ID 54 //
     /*  5559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  5562 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5566 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  5570 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  5574 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  5578 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  5582 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5587 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5592 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5596 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  5598 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5598 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
     /*  5601 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  5607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
     /*  5611 */     GIR_RootConstrainSelectedInstOperands,
     /*  5612 */     // GIR_Coverage, 54,
     /*  5612 */     GIR_EraseRootFromParent_Done,
     /*  5613 */   // Label 290: @5613
     /*  5613 */   GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(5672), // Rule ID 1155 //
     /*  5618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  5621 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5625 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  5629 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  5633 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  5637 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  5641 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5646 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5651 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5655 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  5657 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5657 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
     /*  5660 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5662 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  5666 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
     /*  5670 */     GIR_RootConstrainSelectedInstOperands,
     /*  5671 */     // GIR_Coverage, 1155,
     /*  5671 */     GIR_EraseRootFromParent_Done,
     /*  5672 */   // Label 291: @5672
     /*  5672 */   GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(5731), // Rule ID 1257 //
     /*  5677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  5680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5684 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  5688 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  5692 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /*  5696 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /*  5700 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5705 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5710 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5714 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  5716 */     // (xor:{ *:[i32] } (or:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt), -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  5716 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
     /*  5719 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5721 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  5725 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
     /*  5729 */     GIR_RootConstrainSelectedInstOperands,
     /*  5730 */     // GIR_Coverage, 1257,
     /*  5730 */     GIR_EraseRootFromParent_Done,
     /*  5731 */   // Label 292: @5731
     /*  5731 */   GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(5760), // Rule ID 1284 //
     /*  5736 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  5739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5743 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5747 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5751 */     // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
     /*  5751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
     /*  5754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  5756 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  5758 */     GIR_RootConstrainSelectedInstOperands,
     /*  5759 */     // GIR_Coverage, 1284,
     /*  5759 */     GIR_EraseRootFromParent_Done,
     /*  5760 */   // Label 293: @5760
     /*  5760 */   GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(5789), // Rule ID 1137 //
     /*  5765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  5768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5772 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5776 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5780 */     // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs)
     /*  5780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
     /*  5783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  5785 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  5787 */     GIR_RootConstrainSelectedInstOperands,
     /*  5788 */     // GIR_Coverage, 1137,
     /*  5788 */     GIR_EraseRootFromParent_Done,
     /*  5789 */   // Label 294: @5789
     /*  5789 */   GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(5824), // Rule ID 1472 //
     /*  5794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  5797 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5801 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5805 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5809 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
     /*  5809 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR),
     /*  5812 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5814 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /*  5816 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  5822 */     GIR_RootConstrainSelectedInstOperands,
     /*  5823 */     // GIR_Coverage, 1472,
     /*  5823 */     GIR_EraseRootFromParent_Done,
     /*  5824 */   // Label 295: @5824
     /*  5824 */   GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(5853), // Rule ID 1952 //
     /*  5829 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  5832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  5836 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  5840 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5844 */     // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, -1:{ *:[i32] })  =>  (NotRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
     /*  5844 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NotRxRy16),
     /*  5847 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /*  5849 */     GIR_RootToRootCopy, /*OpIdx*/1, // r
     /*  5851 */     GIR_RootConstrainSelectedInstOperands,
     /*  5852 */     // GIR_Coverage, 1952,
     /*  5852 */     GIR_EraseRootFromParent_Done,
     /*  5853 */   // Label 296: @5853
     /*  5853 */   GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(5882), // Rule ID 2294 //
     /*  5858 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /*  5861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5865 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5869 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5873 */     // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
     /*  5873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MM),
     /*  5876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  5878 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /*  5880 */     GIR_RootConstrainSelectedInstOperands,
     /*  5881 */     // GIR_Coverage, 2294,
     /*  5881 */     GIR_EraseRootFromParent_Done,
     /*  5882 */   // Label 297: @5882
     /*  5882 */   GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(5917), // Rule ID 2295 //
     /*  5887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /*  5890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5894 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5898 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5902 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
     /*  5902 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MM),
     /*  5905 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5907 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /*  5909 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  5915 */     GIR_RootConstrainSelectedInstOperands,
     /*  5916 */     // GIR_Coverage, 2295,
     /*  5916 */     GIR_EraseRootFromParent_Done,
     /*  5917 */   // Label 298: @5917
     /*  5917 */   GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(5946), // Rule ID 2465 //
     /*  5922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  5925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5929 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  5933 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5937 */     // (xor:{ *:[i32] } GPRMM16:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOT16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$in)
     /*  5937 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOT16_MMR6),
     /*  5940 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  5942 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /*  5944 */     GIR_RootConstrainSelectedInstOperands,
     /*  5945 */     // GIR_Coverage, 2465,
     /*  5945 */     GIR_EraseRootFromParent_Done,
     /*  5946 */   // Label 299: @5946
     /*  5946 */   GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(5981), // Rule ID 2466 //
     /*  5951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  5954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5958 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5962 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  5966 */     // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$in, -1:{ *:[i32] })  =>  (NOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$in, ZERO:{ *:[i32] })
     /*  5966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR_MMR6),
     /*  5969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  5971 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /*  5973 */     GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /*  5979 */     GIR_RootConstrainSelectedInstOperands,
     /*  5980 */     // GIR_Coverage, 2466,
     /*  5980 */     GIR_EraseRootFromParent_Done,
     /*  5981 */   // Label 300: @5981
     /*  5981 */   GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(6023), // Rule ID 43 //
     /*  5986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  5989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5993 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  5997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /*  6001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /*  6005 */     GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_imm32ZExt16),
     /*  6009 */     // MIs[1] Operand 1
     /*  6009 */     // No operand predicates
     /*  6009 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  6011 */     // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16)  =>  (XORi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
     /*  6011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /*  6014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /*  6016 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  6018 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
     /*  6021 */     GIR_RootConstrainSelectedInstOperands,
     /*  6022 */     // GIR_Coverage, 43,
     /*  6022 */     GIR_EraseRootFromParent_Done,
     /*  6023 */   // Label 301: @6023
     /*  6023 */   GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(6050), // Rule ID 53 //
     /*  6028 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /*  6031 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6035 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6043 */     // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  6043 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /*  6048 */     GIR_RootConstrainSelectedInstOperands,
     /*  6049 */     // GIR_Coverage, 53,
     /*  6049 */     GIR_Done,
     /*  6050 */   // Label 302: @6050
     /*  6050 */   GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(6077), // Rule ID 1140 //
     /*  6055 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  6058 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  6062 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  6066 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /*  6070 */     // (xor:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)  =>  (XOR16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
     /*  6070 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR16_MM),
     /*  6075 */     GIR_RootConstrainSelectedInstOperands,
     /*  6076 */     // GIR_Coverage, 1140,
     /*  6076 */     GIR_Done,
     /*  6077 */   // Label 303: @6077
     /*  6077 */   GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(6104), // Rule ID 1154 //
     /*  6082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /*  6085 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6089 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6093 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6097 */     // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  6097 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /*  6102 */     GIR_RootConstrainSelectedInstOperands,
     /*  6103 */     // GIR_Coverage, 1154,
     /*  6103 */     GIR_Done,
     /*  6104 */   // Label 304: @6104
     /*  6104 */   GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(6131), // Rule ID 1261 //
     /*  6109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /*  6112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6116 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6120 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6124 */     // (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (XOR_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /*  6124 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_MMR6),
     /*  6129 */     GIR_RootConstrainSelectedInstOperands,
     /*  6130 */     // GIR_Coverage, 1261,
     /*  6130 */     GIR_Done,
     /*  6131 */   // Label 305: @6131
     /*  6131 */   GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(6158), // Rule ID 1959 //
     /*  6136 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /*  6139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  6143 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  6147 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /*  6151 */     // (xor:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)  =>  (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
     /*  6151 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /*  6156 */     GIR_RootConstrainSelectedInstOperands,
     /*  6157 */     // GIR_Coverage, 1959,
     /*  6157 */     GIR_Done,
     /*  6158 */   // Label 306: @6158
     /*  6158 */   GIM_Reject,
     /*  6159 */ // Label 289: @6159
     /*  6159 */ GIM_Reject,
     /*  6160 */ // Label 283: @6160
     /*  6160 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(6254),
     /*  6165 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  6168 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /*  6171 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6175 */   GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(6230), // Rule ID 284 //
     /*  6180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /*  6183 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /*  6187 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
     /*  6191 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /*  6195 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /*  6199 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6204 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6209 */     GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
     /*  6213 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /*  6215 */     // (xor:{ *:[i64] } (or:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), -1:{ *:[i64] })  =>  (NOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  6215 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NOR64),
     /*  6218 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /*  6220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /*  6224 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
     /*  6228 */     GIR_RootConstrainSelectedInstOperands,
     /*  6229 */     // GIR_Coverage, 284,
     /*  6229 */     GIR_EraseRootFromParent_Done,
     /*  6230 */   // Label 308: @6230
     /*  6230 */   GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(6253), // Rule ID 283 //
     /*  6235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /*  6238 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6242 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6246 */     // (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (XOR64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /*  6246 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /*  6251 */     GIR_RootConstrainSelectedInstOperands,
     /*  6252 */     // GIR_Coverage, 283,
     /*  6252 */     GIR_Done,
     /*  6253 */   // Label 309: @6253
     /*  6253 */   GIM_Reject,
     /*  6254 */ // Label 307: @6254
     /*  6254 */ GIM_Reject,
     /*  6255 */ // Label 284: @6255
     /*  6255 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(6288), // Rule ID 1115 //
     /*  6260 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6263 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  6266 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /*  6269 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  6273 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  6277 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  6281 */   // (xor:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (XOR_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /*  6281 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_D_PSEUDO),
     /*  6286 */   GIR_RootConstrainSelectedInstOperands,
     /*  6287 */   // GIR_Coverage, 1115,
     /*  6287 */   GIR_Done,
     /*  6288 */ // Label 310: @6288
     /*  6288 */ GIM_Reject,
     /*  6289 */ // Label 285: @6289
     /*  6289 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(6322), // Rule ID 1114 //
     /*  6294 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6297 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  6300 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /*  6303 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  6307 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  6311 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  6315 */   // (xor:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (XOR_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /*  6315 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_W_PSEUDO),
     /*  6320 */   GIR_RootConstrainSelectedInstOperands,
     /*  6321 */   // GIR_Coverage, 1114,
     /*  6321 */   GIR_Done,
     /*  6322 */ // Label 311: @6322
     /*  6322 */ GIM_Reject,
     /*  6323 */ // Label 286: @6323
     /*  6323 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(6356), // Rule ID 1113 //
     /*  6328 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6331 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  6334 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /*  6337 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  6341 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  6345 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  6349 */   // (xor:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (XOR_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /*  6349 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V_H_PSEUDO),
     /*  6354 */   GIR_RootConstrainSelectedInstOperands,
     /*  6355 */   // GIR_Coverage, 1113,
     /*  6355 */   GIR_Done,
     /*  6356 */ // Label 312: @6356
     /*  6356 */ GIM_Reject,
     /*  6357 */ // Label 287: @6357
     /*  6357 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(6390), // Rule ID 1112 //
     /*  6362 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6365 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  6368 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /*  6371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  6375 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  6379 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  6383 */   // (xor:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (XOR_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /*  6383 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::XOR_V),
     /*  6388 */   GIR_RootConstrainSelectedInstOperands,
     /*  6389 */   // GIR_Coverage, 1112,
     /*  6389 */   GIR_Done,
     /*  6390 */ // Label 313: @6390
     /*  6390 */ GIM_Reject,
     /*  6391 */ // Label 288: @6391
     /*  6391 */ GIM_Reject,
     /*  6392 */ // Label 10: @6392
     /*  6392 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(6464),
     /*  6397 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  6400 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /*  6403 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6406 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /*  6409 */   GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(6436), // Rule ID 255 //
     /*  6414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode),
     /*  6417 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /*  6421 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6425 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6429 */     // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
     /*  6429 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64),
     /*  6434 */     GIR_RootConstrainSelectedInstOperands,
     /*  6435 */     // GIR_Coverage, 255,
     /*  6435 */     GIR_Done,
     /*  6436 */   // Label 315: @6436
     /*  6436 */   GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(6463), // Rule ID 256 //
     /*  6441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode),
     /*  6444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /*  6448 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6452 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6456 */     // (MipsBuildPairF64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)  =>  (BuildPairF64_64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$lo, GPR32Opnd:{ *:[i32] }:$hi)
     /*  6456 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BuildPairF64_64),
     /*  6461 */     GIR_RootConstrainSelectedInstOperands,
     /*  6462 */     // GIR_Coverage, 256,
     /*  6462 */     GIR_Done,
     /*  6463 */   // Label 316: @6463
     /*  6463 */   GIM_Reject,
     /*  6464 */ // Label 314: @6464
     /*  6464 */ GIM_Reject,
     /*  6465 */ // Label 11: @6465
     /*  6465 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(6536),
     /*  6470 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /*  6473 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /*  6476 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  6479 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  6483 */   GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(6509), // Rule ID 794 //
     /*  6488 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasMips64_HasStdEnc),
     /*  6491 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  6495 */     // MIs[0] rs
     /*  6495 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6500 */     // (build_vector:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rs)  =>  (FILL_D:{ *:[v2i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /*  6500 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_D),
     /*  6503 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6505 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  6507 */     GIR_RootConstrainSelectedInstOperands,
     /*  6508 */     // GIR_Coverage, 794,
     /*  6508 */     GIR_EraseRootFromParent_Done,
     /*  6509 */   // Label 318: @6509
     /*  6509 */   GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(6535), // Rule ID 796 //
     /*  6514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6517 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /*  6521 */     // MIs[0] fs
     /*  6521 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6526 */     // (build_vector:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs, FGR64:{ *:[f64] }:$fs)  =>  (FILL_FD_PSEUDO:{ *:[v2f64] } FGR64:{ *:[f64] }:$fs)
     /*  6526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FD_PSEUDO),
     /*  6529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6531 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /*  6533 */     GIR_RootConstrainSelectedInstOperands,
     /*  6534 */     // GIR_Coverage, 796,
     /*  6534 */     GIR_EraseRootFromParent_Done,
     /*  6535 */   // Label 319: @6535
     /*  6535 */   GIM_Reject,
     /*  6536 */ // Label 317: @6536
     /*  6536 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(6627),
     /*  6541 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /*  6544 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /*  6547 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6550 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  6554 */   GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(6590), // Rule ID 793 //
     /*  6559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6562 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6566 */     // MIs[0] rs
     /*  6566 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6571 */     // MIs[0] rs
     /*  6571 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6576 */     // MIs[0] rs
     /*  6576 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6581 */     // (build_vector:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_W:{ *:[v4i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /*  6581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_W),
     /*  6584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6586 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  6588 */     GIR_RootConstrainSelectedInstOperands,
     /*  6589 */     // GIR_Coverage, 793,
     /*  6589 */     GIR_EraseRootFromParent_Done,
     /*  6590 */   // Label 321: @6590
     /*  6590 */   GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(6626), // Rule ID 795 //
     /*  6595 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6598 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6602 */     // MIs[0] fs
     /*  6602 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6607 */     // MIs[0] fs
     /*  6607 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6612 */     // MIs[0] fs
     /*  6612 */     GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6617 */     // (build_vector:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs, FGR32:{ *:[f32] }:$fs)  =>  (FILL_FW_PSEUDO:{ *:[v4f32] } FGR32:{ *:[f32] }:$fs)
     /*  6617 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_FW_PSEUDO),
     /*  6620 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6622 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /*  6624 */     GIR_RootConstrainSelectedInstOperands,
     /*  6625 */     // GIR_Coverage, 795,
     /*  6625 */     GIR_EraseRootFromParent_Done,
     /*  6626 */   // Label 322: @6626
     /*  6626 */   GIM_Reject,
     /*  6627 */ // Label 320: @6627
     /*  6627 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(6696), // Rule ID 792 //
     /*  6632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6635 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
     /*  6638 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /*  6641 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6644 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  6648 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6652 */   // MIs[0] rs
     /*  6652 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6657 */   // MIs[0] rs
     /*  6657 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6662 */   // MIs[0] rs
     /*  6662 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6667 */   // MIs[0] rs
     /*  6667 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6672 */   // MIs[0] rs
     /*  6672 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6677 */   // MIs[0] rs
     /*  6677 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6682 */   // MIs[0] rs
     /*  6682 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6687 */   // (build_vector:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_H:{ *:[v8i16] } GPR32Opnd:{ *:[i32] }:$rs)
     /*  6687 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_H),
     /*  6690 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6692 */   GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  6694 */   GIR_RootConstrainSelectedInstOperands,
     /*  6695 */   // GIR_Coverage, 792,
     /*  6695 */   GIR_EraseRootFromParent_Done,
     /*  6696 */ // Label 323: @6696
     /*  6696 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(6805), // Rule ID 791 //
     /*  6701 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /*  6704 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/17,
     /*  6707 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /*  6710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  6717 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6721 */   // MIs[0] rs
     /*  6721 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6726 */   // MIs[0] rs
     /*  6726 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6731 */   // MIs[0] rs
     /*  6731 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/4, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6736 */   // MIs[0] rs
     /*  6736 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/5, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6741 */   // MIs[0] rs
     /*  6741 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/6, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6746 */   // MIs[0] rs
     /*  6746 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/7, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6751 */   // MIs[0] rs
     /*  6751 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/8, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6756 */   // MIs[0] rs
     /*  6756 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/9, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6761 */   // MIs[0] rs
     /*  6761 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/10, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6766 */   // MIs[0] rs
     /*  6766 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/11, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6771 */   // MIs[0] rs
     /*  6771 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/12, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6776 */   // MIs[0] rs
     /*  6776 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/13, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6781 */   // MIs[0] rs
     /*  6781 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/14, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6786 */   // MIs[0] rs
     /*  6786 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/15, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6791 */   // MIs[0] rs
     /*  6791 */   GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/16, /*OtherMI*/0, /*OtherOpIdx*/1,
     /*  6796 */   // (build_vector:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rs)  =>  (FILL_B:{ *:[v16i8] } GPR32Opnd:{ *:[i32] }:$rs)
     /*  6796 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FILL_B),
     /*  6799 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /*  6801 */   GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /*  6803 */   GIR_RootConstrainSelectedInstOperands,
     /*  6804 */   // GIR_Coverage, 791,
     /*  6804 */   GIR_EraseRootFromParent_Done,
     /*  6805 */ // Label 324: @6805
     /*  6805 */ GIM_Reject,
     /*  6806 */ // Label 12: @6806
     /*  6806 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 333*/ GIMT_Encode4(11116),
     /*  6817 */ /*GILLT_s32*//*Label 325*/ GIMT_Encode4(6849),
     /*  6821 */ /*GILLT_s64*//*Label 326*/ GIMT_Encode4(7126),
     /*  6825 */ /*GILLT_v2s16*//*Label 327*/ GIMT_Encode4(7182),
     /*  6829 */ /*GILLT_v2s64*//*Label 328*/ GIMT_Encode4(7242),
     /*  6833 */ /*GILLT_v4s8*//*Label 329*/ GIMT_Encode4(8377),
     /*  6837 */ /*GILLT_v4s32*//*Label 330*/ GIMT_Encode4(8437),
     /*  6841 */ /*GILLT_v8s16*//*Label 331*/ GIMT_Encode4(9506),
     /*  6845 */ /*GILLT_v16s8*//*Label 332*/ GIMT_Encode4(10431),
     /*  6849 */ // Label 325: @6849
     /*  6849 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(6875), // Rule ID 138 //
     /*  6854 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /*  6857 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6860 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6864 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6868 */   // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
     /*  6868 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1),
     /*  6873 */   GIR_RootConstrainSelectedInstOperands,
     /*  6874 */   // GIR_Coverage, 138,
     /*  6874 */   GIR_Done,
     /*  6875 */ // Label 334: @6875
     /*  6875 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(6901), // Rule ID 139 //
     /*  6880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /*  6883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6886 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6890 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6894 */   // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
     /*  6894 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1),
     /*  6899 */   GIR_RootConstrainSelectedInstOperands,
     /*  6900 */   // GIR_Coverage, 139,
     /*  6900 */   GIR_Done,
     /*  6901 */ // Label 335: @6901
     /*  6901 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(6927), // Rule ID 1235 //
     /*  6906 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /*  6909 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6916 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6920 */   // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MM:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
     /*  6920 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MM),
     /*  6925 */   GIR_RootConstrainSelectedInstOperands,
     /*  6926 */   // GIR_Coverage, 1235,
     /*  6926 */   GIR_Done,
     /*  6927 */ // Label 336: @6927
     /*  6927 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(6953), // Rule ID 1236 //
     /*  6932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /*  6935 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6942 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6946 */   // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MM:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
     /*  6946 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MM),
     /*  6951 */   GIR_RootConstrainSelectedInstOperands,
     /*  6952 */   // GIR_Coverage, 1236,
     /*  6952 */   GIR_Done,
     /*  6953 */ // Label 337: @6953
     /*  6953 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(6979), // Rule ID 1250 //
     /*  6958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /*  6961 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6964 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6968 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6972 */   // (bitconvert:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)  =>  (MTC1_MMR6:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$rt)
     /*  6972 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MTC1_MMR6),
     /*  6977 */   GIR_RootConstrainSelectedInstOperands,
     /*  6978 */   // GIR_Coverage, 1250,
     /*  6978 */   GIR_Done,
     /*  6979 */ // Label 338: @6979
     /*  6979 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(7005), // Rule ID 1251 //
     /*  6984 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /*  6987 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  6990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  6994 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  6998 */   // (bitconvert:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MFC1_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs)
     /*  6998 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MFC1_MMR6),
     /*  7003 */   GIR_RootConstrainSelectedInstOperands,
     /*  7004 */   // GIR_Coverage, 1251,
     /*  7004 */   GIR_Done,
     /*  7005 */ // Label 339: @7005
     /*  7005 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(7035), // Rule ID 2040 //
     /*  7010 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7013 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*  7016 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  7020 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7024 */   // (bitconvert:{ *:[i32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v2i16] }:$src, GPR32:{ *:[i32] })
     /*  7024 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7029 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
     /*  7034 */   // GIR_Coverage, 2040,
     /*  7034 */   GIR_Done,
     /*  7035 */ // Label 340: @7035
     /*  7035 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(7065), // Rule ID 2041 //
     /*  7040 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /*  7046 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  7050 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7054 */   // (bitconvert:{ *:[i32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[i32] } DSPR:{ *:[v4i8] }:$src, GPR32:{ *:[i32] })
     /*  7054 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7059 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR32RegClassID),
     /*  7064 */   // GIR_Coverage, 2041,
     /*  7064 */   GIR_Done,
     /*  7065 */ // Label 341: @7065
     /*  7065 */ GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(7095), // Rule ID 2044 //
     /*  7070 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7073 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /*  7076 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  7080 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7084 */   // (bitconvert:{ *:[f32] } DSPR:{ *:[v2i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v2i16] }:$src, FGR32:{ *:[i32] })
     /*  7084 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7089 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
     /*  7094 */   // GIR_Coverage, 2044,
     /*  7094 */   GIR_Done,
     /*  7095 */ // Label 342: @7095
     /*  7095 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(7125), // Rule ID 2045 //
     /*  7100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7103 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /*  7106 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  7110 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7114 */   // (bitconvert:{ *:[f32] } DSPR:{ *:[v4i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[f32] } DSPR:{ *:[v4i8] }:$src, FGR32:{ *:[i32] })
     /*  7114 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7119 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
     /*  7124 */   // GIR_Coverage, 2045,
     /*  7124 */   GIR_Done,
     /*  7125 */ // Label 343: @7125
     /*  7125 */ GIM_Reject,
     /*  7126 */ // Label 326: @7126
     /*  7126 */ GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(7181),
     /*  7131 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /*  7134 */   GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(7157), // Rule ID 140 //
     /*  7139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /*  7142 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /*  7146 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  7150 */     // (bitconvert:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMTC1:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$rt)
     /*  7150 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMTC1),
     /*  7155 */     GIR_RootConstrainSelectedInstOperands,
     /*  7156 */     // GIR_Coverage, 140,
     /*  7156 */     GIR_Done,
     /*  7157 */   // Label 345: @7157
     /*  7157 */   GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(7180), // Rule ID 141 //
     /*  7162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /*  7165 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /*  7169 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /*  7173 */     // (bitconvert:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (DMFC1:{ *:[i64] } FGR64Opnd:{ *:[f64] }:$fs)
     /*  7173 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMFC1),
     /*  7178 */     GIR_RootConstrainSelectedInstOperands,
     /*  7179 */     // GIR_Coverage, 141,
     /*  7179 */     GIR_Done,
     /*  7180 */   // Label 346: @7180
     /*  7180 */   GIM_Reject,
     /*  7181 */ // Label 344: @7181
     /*  7181 */ GIM_Reject,
     /*  7182 */ // Label 327: @7182
     /*  7182 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(7241),
     /*  7187 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  7190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7194 */   GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(7217), // Rule ID 2042 //
     /*  7199 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7202 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  7206 */     // (bitconvert:{ *:[v2i16] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
     /*  7206 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7211 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7216 */     // GIR_Coverage, 2042,
     /*  7216 */     GIR_Done,
     /*  7217 */   // Label 348: @7217
     /*  7217 */   GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(7240), // Rule ID 2046 //
     /*  7222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  7225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  7229 */     // (bitconvert:{ *:[v2i16] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
     /*  7229 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7234 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /*  7239 */     // GIR_Coverage, 2046,
     /*  7239 */     GIR_Done,
     /*  7240 */   // Label 349: @7240
     /*  7240 */   GIM_Reject,
     /*  7241 */ // Label 347: @7241
     /*  7241 */ GIM_Reject,
     /*  7242 */ // Label 328: @7242
     /*  7242 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(7268), // Rule ID 2127 //
     /*  7247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  7250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  7253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7257 */   // (bitconvert:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v2f64:{ *:[v2f64] }:$src, MSA128D:{ *:[i32] })
     /*  7257 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7262 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7267 */   // GIR_Coverage, 2127,
     /*  7267 */   GIR_Done,
     /*  7268 */ // Label 350: @7268
     /*  7268 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(7294), // Rule ID 2130 //
     /*  7273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  7276 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  7279 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7283 */   // (bitconvert:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v2i64:{ *:[v2i64] }:$src, MSA128D:{ *:[i32] })
     /*  7283 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7288 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7293 */   // GIR_Coverage, 2130,
     /*  7293 */   GIR_Done,
     /*  7294 */ // Label 351: @7294
     /*  7294 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(7320), // Rule ID 2147 //
     /*  7299 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7302 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  7305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7309 */   // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
     /*  7309 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7314 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7319 */   // GIR_Coverage, 2147,
     /*  7319 */   GIR_Done,
     /*  7320 */ // Label 352: @7320
     /*  7320 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(7346), // Rule ID 2148 //
     /*  7325 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7328 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7331 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7335 */   // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
     /*  7335 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7340 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7345 */   // GIR_Coverage, 2148,
     /*  7345 */   GIR_Done,
     /*  7346 */ // Label 353: @7346
     /*  7346 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(7372), // Rule ID 2149 //
     /*  7351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  7357 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7361 */   // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
     /*  7361 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7366 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7371 */   // GIR_Coverage, 2149,
     /*  7371 */   GIR_Done,
     /*  7372 */ // Label 354: @7372
     /*  7372 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(7398), // Rule ID 2150 //
     /*  7377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7380 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7387 */   // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
     /*  7387 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7392 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7397 */   // GIR_Coverage, 2150,
     /*  7397 */   GIR_Done,
     /*  7398 */ // Label 355: @7398
     /*  7398 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(7424), // Rule ID 2151 //
     /*  7403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7406 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  7409 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7413 */   // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
     /*  7413 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7418 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7423 */   // GIR_Coverage, 2151,
     /*  7423 */   GIR_Done,
     /*  7424 */ // Label 356: @7424
     /*  7424 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(7450), // Rule ID 2157 //
     /*  7429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7432 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  7435 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7439 */   // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src, MSA128D:{ *:[i32] })
     /*  7439 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7444 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7449 */   // GIR_Coverage, 2157,
     /*  7449 */   GIR_Done,
     /*  7450 */ // Label 357: @7450
     /*  7450 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(7476), // Rule ID 2158 //
     /*  7455 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7458 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7465 */   // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src, MSA128D:{ *:[i32] })
     /*  7465 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7470 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7475 */   // GIR_Coverage, 2158,
     /*  7475 */   GIR_Done,
     /*  7476 */ // Label 358: @7476
     /*  7476 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(7502), // Rule ID 2159 //
     /*  7481 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7484 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  7487 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7491 */   // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src, MSA128D:{ *:[i32] })
     /*  7491 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7496 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7501 */   // GIR_Coverage, 2159,
     /*  7501 */   GIR_Done,
     /*  7502 */ // Label 359: @7502
     /*  7502 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(7528), // Rule ID 2160 //
     /*  7507 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7513 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7517 */   // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src, MSA128D:{ *:[i32] })
     /*  7517 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7522 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7527 */   // GIR_Coverage, 2160,
     /*  7527 */   GIR_Done,
     /*  7528 */ // Label 360: @7528
     /*  7528 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(7554), // Rule ID 2161 //
     /*  7533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  7536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  7539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7543 */   // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src, MSA128D:{ *:[i32] })
     /*  7543 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7548 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7553 */   // GIR_Coverage, 2161,
     /*  7553 */   GIR_Done,
     /*  7554 */ // Label 361: @7554
     /*  7554 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(7671), // Rule ID 2166 //
     /*  7559 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  7562 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  7565 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7569 */   // (bitconvert:{ *:[v2i64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  7569 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /*  7572 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7576 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7581 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  7585 */   GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  7590 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /*  7593 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  7597 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7602 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /*  7605 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
     /*  7608 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  7610 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  7613 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7617 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7622 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  7625 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  7630 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  7633 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  7637 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7642 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  7645 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  7655 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  7657 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7660 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  7662 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  7665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7670 */   // GIR_Coverage, 2166,
     /*  7670 */   GIR_EraseRootFromParent_Done,
     /*  7671 */ // Label 362: @7671
     /*  7671 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(7788), // Rule ID 2167 //
     /*  7676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  7679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  7682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7686 */   // (bitconvert:{ *:[v2f64] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  7686 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /*  7689 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7693 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7698 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  7702 */   GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  7707 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /*  7710 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  7714 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7719 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /*  7722 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
     /*  7725 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /*  7727 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  7730 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7734 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7739 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /*  7742 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  7747 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  7750 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  7754 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7759 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  7762 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  7772 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  7774 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7777 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  7779 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  7782 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7787 */   // GIR_Coverage, 2167,
     /*  7787 */   GIR_EraseRootFromParent_Done,
     /*  7788 */ // Label 363: @7788
     /*  7788 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(7858), // Rule ID 2171 //
     /*  7793 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  7796 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7803 */   // (bitconvert:{ *:[v2i64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  7803 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  7806 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7810 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7815 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  7819 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  7824 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  7827 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  7831 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7836 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  7839 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  7842 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  7844 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7847 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  7849 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  7852 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7857 */   // GIR_Coverage, 2171,
     /*  7857 */   GIR_EraseRootFromParent_Done,
     /*  7858 */ // Label 364: @7858
     /*  7858 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(7928), // Rule ID 2172 //
     /*  7863 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  7866 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7873 */   // (bitconvert:{ *:[v2f64] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  7873 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  7876 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7880 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7885 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  7889 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  7894 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  7897 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  7901 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7906 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  7909 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  7912 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  7914 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7917 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  7919 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  7922 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7927 */   // GIR_Coverage, 2172,
     /*  7927 */   GIR_EraseRootFromParent_Done,
     /*  7928 */ // Label 365: @7928
     /*  7928 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(7998), // Rule ID 2176 //
     /*  7933 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  7936 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  7939 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7943 */   // (bitconvert:{ *:[v2i64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  7943 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  7946 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7950 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7955 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  7959 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  7964 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  7967 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  7971 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  7976 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  7979 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  7982 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  7984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  7987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  7989 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  7992 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  7997 */   // GIR_Coverage, 2176,
     /*  7997 */   GIR_EraseRootFromParent_Done,
     /*  7998 */ // Label 366: @7998
     /*  7998 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(8068), // Rule ID 2177 //
     /*  8003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8013 */   // (bitconvert:{ *:[v2f64] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  8013 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  8016 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8020 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8025 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8029 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  8034 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  8037 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  8041 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8046 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8049 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  8052 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8054 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8057 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8059 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8062 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8067 */   // GIR_Coverage, 2177,
     /*  8067 */   GIR_EraseRootFromParent_Done,
     /*  8068 */ // Label 367: @8068
     /*  8068 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(8145), // Rule ID 2181 //
     /*  8073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8076 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8079 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8083 */   // (bitconvert:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  8083 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  8086 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8090 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8095 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8099 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8104 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  8107 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  8111 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8116 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8119 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  8129 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8131 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8134 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8136 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8139 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8144 */   // GIR_Coverage, 2181,
     /*  8144 */   GIR_EraseRootFromParent_Done,
     /*  8145 */ // Label 368: @8145
     /*  8145 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(8222), // Rule ID 2182 //
     /*  8150 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8153 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8156 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8160 */   // (bitconvert:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  8160 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  8163 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8167 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8172 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8176 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8181 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  8184 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  8188 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8193 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8196 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  8206 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8208 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8211 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8213 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8216 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8221 */   // GIR_Coverage, 2182,
     /*  8221 */   GIR_EraseRootFromParent_Done,
     /*  8222 */ // Label 369: @8222
     /*  8222 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(8299), // Rule ID 2186 //
     /*  8227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8233 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8237 */   // (bitconvert:{ *:[v2i64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2i64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  8237 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  8240 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8244 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8249 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8253 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8258 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  8261 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  8265 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8270 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8273 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  8283 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8285 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8288 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8290 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8293 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8298 */   // GIR_Coverage, 2186,
     /*  8298 */   GIR_EraseRootFromParent_Done,
     /*  8299 */ // Label 370: @8299
     /*  8299 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(8376), // Rule ID 2187 //
     /*  8304 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8307 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8310 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8314 */   // (bitconvert:{ *:[v2f64] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v2f64] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128D:{ *:[i32] })
     /*  8314 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  8317 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8321 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8326 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8330 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8335 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  8338 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  8342 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8347 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8350 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  8360 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8367 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8370 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128DRegClassID),
     /*  8375 */   // GIR_Coverage, 2187,
     /*  8375 */   GIR_EraseRootFromParent_Done,
     /*  8376 */ // Label 371: @8376
     /*  8376 */ GIM_Reject,
     /*  8377 */ // Label 329: @8377
     /*  8377 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(8436),
     /*  8382 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /*  8385 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /*  8389 */   GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(8412), // Rule ID 2043 //
     /*  8394 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  8397 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /*  8401 */     // (bitconvert:{ *:[v4i8] } GPR32:{ *:[i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } GPR32:{ *:[i32] }:$src, DSPR:{ *:[i32] })
     /*  8401 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8406 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /*  8411 */     // GIR_Coverage, 2043,
     /*  8411 */     GIR_Done,
     /*  8412 */   // Label 373: @8412
     /*  8412 */   GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(8435), // Rule ID 2047 //
     /*  8417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /*  8420 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /*  8424 */     // (bitconvert:{ *:[v4i8] } FGR32:{ *:[f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i8] } FGR32:{ *:[f32] }:$src, DSPR:{ *:[i32] })
     /*  8424 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8429 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /*  8434 */     // GIR_Coverage, 2047,
     /*  8434 */     GIR_Done,
     /*  8435 */   // Label 374: @8435
     /*  8435 */   GIM_Reject,
     /*  8436 */ // Label 372: @8436
     /*  8436 */ GIM_Reject,
     /*  8437 */ // Label 330: @8437
     /*  8437 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(8463), // Rule ID 2126 //
     /*  8442 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  8445 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8448 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8452 */   // (bitconvert:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, MSA128W:{ *:[i32] })
     /*  8452 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8457 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8462 */   // GIR_Coverage, 2126,
     /*  8462 */   GIR_Done,
     /*  8463 */ // Label 375: @8463
     /*  8463 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(8489), // Rule ID 2129 //
     /*  8468 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  8471 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  8474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8478 */   // (bitconvert:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$src, MSA128W:{ *:[i32] })
     /*  8478 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8483 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8488 */   // GIR_Coverage, 2129,
     /*  8488 */   GIR_Done,
     /*  8489 */ // Label 376: @8489
     /*  8489 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(8515), // Rule ID 2142 //
     /*  8494 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8497 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  8500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8504 */   // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
     /*  8504 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8509 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8514 */   // GIR_Coverage, 2142,
     /*  8514 */   GIR_Done,
     /*  8515 */ // Label 377: @8515
     /*  8515 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(8541), // Rule ID 2143 //
     /*  8520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8523 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8526 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8530 */   // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
     /*  8530 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8535 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8540 */   // GIR_Coverage, 2143,
     /*  8540 */   GIR_Done,
     /*  8541 */ // Label 378: @8541
     /*  8541 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(8567), // Rule ID 2144 //
     /*  8546 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8549 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  8552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8556 */   // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
     /*  8556 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8561 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8566 */   // GIR_Coverage, 2144,
     /*  8566 */   GIR_Done,
     /*  8567 */ // Label 379: @8567
     /*  8567 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(8593), // Rule ID 2145 //
     /*  8572 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8575 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8578 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8582 */   // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
     /*  8582 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8587 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8592 */   // GIR_Coverage, 2145,
     /*  8592 */   GIR_Done,
     /*  8593 */ // Label 380: @8593
     /*  8593 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(8619), // Rule ID 2146 //
     /*  8598 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8601 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  8604 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8608 */   // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
     /*  8608 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8613 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8618 */   // GIR_Coverage, 2146,
     /*  8618 */   GIR_Done,
     /*  8619 */ // Label 381: @8619
     /*  8619 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(8645), // Rule ID 2152 //
     /*  8624 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8627 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  8630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8634 */   // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src, MSA128W:{ *:[i32] })
     /*  8634 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8639 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8644 */   // GIR_Coverage, 2152,
     /*  8644 */   GIR_Done,
     /*  8645 */ // Label 382: @8645
     /*  8645 */ GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(8671), // Rule ID 2153 //
     /*  8650 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8653 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8656 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8660 */   // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src, MSA128W:{ *:[i32] })
     /*  8660 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8665 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8670 */   // GIR_Coverage, 2153,
     /*  8670 */   GIR_Done,
     /*  8671 */ // Label 383: @8671
     /*  8671 */ GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(8697), // Rule ID 2154 //
     /*  8676 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8679 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  8682 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8686 */   // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] })
     /*  8686 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8691 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8696 */   // GIR_Coverage, 2154,
     /*  8696 */   GIR_Done,
     /*  8697 */ // Label 384: @8697
     /*  8697 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(8723), // Rule ID 2155 //
     /*  8702 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8705 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8708 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8712 */   // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src, MSA128W:{ *:[i32] })
     /*  8712 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8717 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8722 */   // GIR_Coverage, 2155,
     /*  8722 */   GIR_Done,
     /*  8723 */ // Label 385: @8723
     /*  8723 */ GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(8749), // Rule ID 2156 //
     /*  8728 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  8731 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  8734 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8738 */   // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] })
     /*  8738 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8743 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8748 */   // GIR_Coverage, 2156,
     /*  8748 */   GIR_Done,
     /*  8749 */ // Label 386: @8749
     /*  8749 */ GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(8819), // Rule ID 2164 //
     /*  8754 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8757 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  8760 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8764 */   // (bitconvert:{ *:[v4i32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  8764 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /*  8767 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8771 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8776 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8780 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  8785 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /*  8788 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  8792 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8797 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8800 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  8803 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8805 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8808 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8810 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8813 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8818 */   // GIR_Coverage, 2164,
     /*  8818 */   GIR_EraseRootFromParent_Done,
     /*  8819 */ // Label 387: @8819
     /*  8819 */ GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(8889), // Rule ID 2165 //
     /*  8824 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8827 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  8830 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8834 */   // (bitconvert:{ *:[v4f32] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  8834 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /*  8837 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8841 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8846 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8850 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  8855 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /*  8858 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  8862 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8867 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8870 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /*  8873 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8875 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8878 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8880 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8883 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8888 */   // GIR_Coverage, 2165,
     /*  8888 */   GIR_EraseRootFromParent_Done,
     /*  8889 */ // Label 388: @8889
     /*  8889 */ GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(8966), // Rule ID 2169 //
     /*  8894 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8897 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8904 */   // (bitconvert:{ *:[v4i32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  8904 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  8907 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8911 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8916 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8920 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  8925 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  8928 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  8932 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8937 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  8940 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  8950 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  8952 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8955 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  8957 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  8960 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8965 */   // GIR_Coverage, 2169,
     /*  8965 */   GIR_EraseRootFromParent_Done,
     /*  8966 */ // Label 389: @8966
     /*  8966 */ GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(9043), // Rule ID 2170 //
     /*  8971 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  8974 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  8977 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  8981 */   // (bitconvert:{ *:[v4f32] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  8981 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  8984 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  8988 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  8993 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  8997 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9002 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  9005 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  9009 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9014 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9017 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9027 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9032 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9034 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9037 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9042 */   // GIR_Coverage, 2170,
     /*  9042 */   GIR_EraseRootFromParent_Done,
     /*  9043 */ // Label 390: @9043
     /*  9043 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(9120), // Rule ID 2174 //
     /*  9048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9051 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  9054 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9058 */   // (bitconvert:{ *:[v4i32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9058 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  9061 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9065 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9070 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9074 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9079 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  9082 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  9086 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9091 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9094 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9104 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9106 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9109 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9111 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9114 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9119 */   // GIR_Coverage, 2174,
     /*  9119 */   GIR_EraseRootFromParent_Done,
     /*  9120 */ // Label 391: @9120
     /*  9120 */ GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(9197), // Rule ID 2175 //
     /*  9125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  9131 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9135 */   // (bitconvert:{ *:[v4f32] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9135 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  9138 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9142 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9147 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9151 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9156 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  9159 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  9163 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9168 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9171 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9181 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9183 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9186 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9188 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9191 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9196 */   // GIR_Coverage, 2175,
     /*  9196 */   GIR_EraseRootFromParent_Done,
     /*  9197 */ // Label 392: @9197
     /*  9197 */ GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(9274), // Rule ID 2191 //
     /*  9202 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9205 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9208 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9212 */   // (bitconvert:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9212 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  9215 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9219 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9224 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9228 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9233 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  9236 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  9240 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9245 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9248 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9258 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9260 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9263 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9265 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9268 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9273 */   // GIR_Coverage, 2191,
     /*  9273 */   GIR_EraseRootFromParent_Done,
     /*  9274 */ // Label 393: @9274
     /*  9274 */ GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(9351), // Rule ID 2192 //
     /*  9279 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9282 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9289 */   // (bitconvert:{ *:[v4f32] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2i64:{ *:[v2i64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9289 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  9292 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9296 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9301 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9305 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9310 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  9313 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  9317 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9322 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9325 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9335 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9337 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9340 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9342 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9345 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9350 */   // GIR_Coverage, 2192,
     /*  9350 */   GIR_EraseRootFromParent_Done,
     /*  9351 */ // Label 394: @9351
     /*  9351 */ GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(9428), // Rule ID 2196 //
     /*  9356 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9359 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9362 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9366 */   // (bitconvert:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9366 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  9369 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9373 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9378 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9382 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9387 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  9390 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  9394 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9399 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9402 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9412 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9414 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9417 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9419 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9422 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9427 */   // GIR_Coverage, 2196,
     /*  9427 */   GIR_EraseRootFromParent_Done,
     /*  9428 */ // Label 395: @9428
     /*  9428 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(9505), // Rule ID 2197 //
     /*  9433 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9436 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9439 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9443 */   // (bitconvert:{ *:[v4f32] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v4f32] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } v2f64:{ *:[v2f64] }:$src, MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128W:{ *:[i32] })
     /*  9443 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /*  9446 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9450 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9455 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9459 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9464 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /*  9467 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /*  9471 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9476 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9479 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9489 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9496 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9499 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /*  9504 */   // GIR_Coverage, 2197,
     /*  9504 */   GIR_EraseRootFromParent_Done,
     /*  9505 */ // Label 396: @9505
     /*  9505 */ GIM_Reject,
     /*  9506 */ // Label 331: @9506
     /*  9506 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(9532), // Rule ID 2125 //
     /*  9511 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  9514 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  9517 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9521 */   // (bitconvert:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, MSA128H:{ *:[i32] })
     /*  9521 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9526 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9531 */   // GIR_Coverage, 2125,
     /*  9531 */   GIR_Done,
     /*  9532 */ // Label 397: @9532
     /*  9532 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(9558), // Rule ID 2128 //
     /*  9537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /*  9540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /*  9543 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9547 */   // (bitconvert:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } v8i16:{ *:[v8i16] }:$src, MSA128H:{ *:[i32] })
     /*  9547 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9552 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9557 */   // GIR_Coverage, 2128,
     /*  9557 */   GIR_Done,
     /*  9558 */ // Label 398: @9558
     /*  9558 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(9584), // Rule ID 2137 //
     /*  9563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  9566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  9569 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9573 */   // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src, MSA128H:{ *:[i32] })
     /*  9573 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9578 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9583 */   // GIR_Coverage, 2137,
     /*  9583 */   GIR_Done,
     /*  9584 */ // Label 399: @9584
     /*  9584 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(9610), // Rule ID 2138 //
     /*  9589 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  9592 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  9595 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9599 */   // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] })
     /*  9599 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9604 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9609 */   // GIR_Coverage, 2138,
     /*  9609 */   GIR_Done,
     /*  9610 */ // Label 400: @9610
     /*  9610 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(9636), // Rule ID 2139 //
     /*  9615 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  9618 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9625 */   // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] })
     /*  9625 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9630 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9635 */   // GIR_Coverage, 2139,
     /*  9635 */   GIR_Done,
     /*  9636 */ // Label 401: @9636
     /*  9636 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(9662), // Rule ID 2140 //
     /*  9641 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  9644 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  9647 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9651 */   // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] })
     /*  9651 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9656 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9661 */   // GIR_Coverage, 2140,
     /*  9661 */   GIR_Done,
     /*  9662 */ // Label 402: @9662
     /*  9662 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(9688), // Rule ID 2141 //
     /*  9667 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /*  9670 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /*  9673 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9677 */   // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] })
     /*  9677 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9682 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9687 */   // GIR_Coverage, 2141,
     /*  9687 */   GIR_Done,
     /*  9688 */ // Label 403: @9688
     /*  9688 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(9765), // Rule ID 2162 //
     /*  9693 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9696 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  9699 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9703 */   // (bitconvert:{ *:[v8i16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /*  9703 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /*  9706 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9710 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9715 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9719 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  9724 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /*  9727 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  9731 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9736 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9739 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9749 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9751 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9754 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9756 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9759 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9764 */   // GIR_Coverage, 2162,
     /*  9764 */   GIR_EraseRootFromParent_Done,
     /*  9765 */ // Label 404: @9765
     /*  9765 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(9842), // Rule ID 2163 //
     /*  9770 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9773 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /*  9776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9780 */   // (bitconvert:{ *:[v8f16] } v16i8:{ *:[v16i8] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /*  9780 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /*  9783 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9787 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9792 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9796 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /*  9801 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /*  9804 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /*  9808 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9813 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9816 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9826 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9831 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9833 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9836 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9841 */   // GIR_Coverage, 2163,
     /*  9841 */   GIR_EraseRootFromParent_Done,
     /*  9842 */ // Label 405: @9842
     /*  9842 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(9919), // Rule ID 2179 //
     /*  9847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9850 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  9853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9857 */   // (bitconvert:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /*  9857 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  9860 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9864 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9869 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9873 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9878 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  9881 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  9885 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9890 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9893 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9903 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9908 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9910 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9913 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9918 */   // GIR_Coverage, 2179,
     /*  9918 */   GIR_EraseRootFromParent_Done,
     /*  9919 */ // Label 406: @9919
     /*  9919 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(9996), // Rule ID 2180 //
     /*  9924 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /*  9927 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /*  9930 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9934 */   // (bitconvert:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /*  9934 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /*  9937 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9941 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9946 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /*  9950 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9955 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /*  9958 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /*  9962 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /*  9967 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /*  9970 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /*  9980 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /*  9982 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /*  9985 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /*  9987 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /*  9990 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /*  9995 */   // GIR_Coverage, 2180,
     /*  9995 */   GIR_EraseRootFromParent_Done,
     /*  9996 */ // Label 407: @9996
     /*  9996 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(10073), // Rule ID 2184 //
     /* 10001 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10004 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10007 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10011 */   // (bitconvert:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10011 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10014 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10018 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10023 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10027 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10032 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10035 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10039 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10044 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10047 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 10057 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10059 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10062 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10064 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10067 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10072 */   // GIR_Coverage, 2184,
     /* 10072 */   GIR_EraseRootFromParent_Done,
     /* 10073 */ // Label 408: @10073
     /* 10073 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(10150), // Rule ID 2185 //
     /* 10078 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10081 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10084 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10088 */   // (bitconvert:{ *:[v8f16] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v4f32:{ *:[v4f32] }:$src, MSA128H:{ *:[i32] }), 177:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10088 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10091 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10095 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10100 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10104 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10109 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10112 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10116 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10121 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10124 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 10134 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10136 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10139 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10141 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10144 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10149 */   // GIR_Coverage, 2185,
     /* 10149 */   GIR_EraseRootFromParent_Done,
     /* 10150 */ // Label 409: @10150
     /* 10150 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(10220), // Rule ID 2189 //
     /* 10155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10158 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10161 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10165 */   // (bitconvert:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10165 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10168 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10172 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10177 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10181 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10186 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10189 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10193 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10198 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10201 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10204 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10206 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10209 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10211 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10214 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10219 */   // GIR_Coverage, 2189,
     /* 10219 */   GIR_EraseRootFromParent_Done,
     /* 10220 */ // Label 410: @10220
     /* 10220 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(10290), // Rule ID 2190 //
     /* 10225 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10228 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10231 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10235 */   // (bitconvert:{ *:[v8f16] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2i64:{ *:[v2i64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10235 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10238 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10242 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10247 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10251 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10256 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10259 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10263 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10268 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10271 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10274 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10276 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10279 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10281 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10284 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10289 */   // GIR_Coverage, 2190,
     /* 10289 */   GIR_EraseRootFromParent_Done,
     /* 10290 */ // Label 411: @10290
     /* 10290 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(10360), // Rule ID 2194 //
     /* 10295 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10298 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10301 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10305 */   // (bitconvert:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8i16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10305 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10308 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10312 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10317 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10321 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10326 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10329 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10333 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10338 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10341 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10344 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10346 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10349 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10351 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10354 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10359 */   // GIR_Coverage, 2194,
     /* 10359 */   GIR_EraseRootFromParent_Done,
     /* 10360 */ // Label 412: @10360
     /* 10360 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(10430), // Rule ID 2195 //
     /* 10365 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10368 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10371 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10375 */   // (bitconvert:{ *:[v8f16] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v8f16] } (SHF_H:{ *:[v8i16] } (COPY_TO_REGCLASS:{ *:[v8i16] } v2f64:{ *:[v2f64] }:$src, MSA128H:{ *:[i32] }), 27:{ *:[i32] }), MSA128H:{ *:[i32] })
     /* 10375 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
     /* 10378 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10382 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10387 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10391 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10396 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
     /* 10399 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_H),
     /* 10403 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10408 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10411 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10414 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10416 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10419 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10421 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10424 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 10429 */   // GIR_Coverage, 2195,
     /* 10429 */   GIR_EraseRootFromParent_Done,
     /* 10430 */ // Label 413: @10430
     /* 10430 */ GIM_Reject,
     /* 10431 */ // Label 332: @10431
     /* 10431 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(10457), // Rule ID 2131 //
     /* 10436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10439 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 10442 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10446 */   // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] })
     /* 10446 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10451 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10456 */   // GIR_Coverage, 2131,
     /* 10456 */   GIR_Done,
     /* 10457 */ // Label 414: @10457
     /* 10457 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(10483), // Rule ID 2132 //
     /* 10462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10465 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10468 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10472 */   // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] })
     /* 10472 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10477 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10482 */   // GIR_Coverage, 2132,
     /* 10482 */   GIR_Done,
     /* 10483 */ // Label 415: @10483
     /* 10483 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(10509), // Rule ID 2133 //
     /* 10488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10491 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10494 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10498 */   // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] })
     /* 10498 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10503 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10508 */   // GIR_Coverage, 2133,
     /* 10508 */   GIR_Done,
     /* 10509 */ // Label 416: @10509
     /* 10509 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(10535), // Rule ID 2134 //
     /* 10514 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10517 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 10520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10524 */   // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] })
     /* 10524 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10529 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10534 */   // GIR_Coverage, 2134,
     /* 10534 */   GIR_Done,
     /* 10535 */ // Label 417: @10535
     /* 10535 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(10561), // Rule ID 2135 //
     /* 10540 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10550 */   // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] })
     /* 10550 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10555 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10560 */   // GIR_Coverage, 2135,
     /* 10560 */   GIR_Done,
     /* 10561 */ // Label 418: @10561
     /* 10561 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(10587), // Rule ID 2136 //
     /* 10566 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsLE),
     /* 10569 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10576 */   // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] })
     /* 10576 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10581 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10586 */   // GIR_Coverage, 2136,
     /* 10586 */   GIR_Done,
     /* 10587 */ // Label 419: @10587
     /* 10587 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(10664), // Rule ID 2168 //
     /* 10592 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10595 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 10598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10602 */   // (bitconvert:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8i16:{ *:[v8i16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 10602 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 10605 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10609 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10614 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10618 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10623 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 10626 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 10630 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10635 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10638 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 10648 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10650 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10653 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10655 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10658 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10663 */   // GIR_Coverage, 2168,
     /* 10663 */   GIR_EraseRootFromParent_Done,
     /* 10664 */ // Label 420: @10664
     /* 10664 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(10741), // Rule ID 2173 //
     /* 10669 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10672 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 10675 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10679 */   // (bitconvert:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v8f16:{ *:[v8f16] }:$src, MSA128B:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 10679 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 10682 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10686 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10691 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10695 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10700 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 10703 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 10707 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10712 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10715 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 10725 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10727 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10730 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10732 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10735 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10740 */   // GIR_Coverage, 2173,
     /* 10740 */   GIR_EraseRootFromParent_Done,
     /* 10741 */ // Label 421: @10741
     /* 10741 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(10811), // Rule ID 2178 //
     /* 10746 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10749 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10752 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10756 */   // (bitconvert:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4i32:{ *:[v4i32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 10756 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 10759 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10763 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10768 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10772 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10777 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 10780 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 10784 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10789 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10792 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10795 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10797 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10800 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10802 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10805 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10810 */   // GIR_Coverage, 2178,
     /* 10810 */   GIR_EraseRootFromParent_Done,
     /* 10811 */ // Label 422: @10811
     /* 10811 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(10881), // Rule ID 2183 //
     /* 10816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10819 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 10822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10826 */   // (bitconvert:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v4f32:{ *:[v4f32] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 10826 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
     /* 10829 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10833 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10838 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10842 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10847 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
     /* 10850 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 10854 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10859 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10862 */   GIR_AddImm8, /*InsnID*/1, /*Imm*/27,
     /* 10865 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10867 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10870 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10872 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10875 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10880 */   // GIR_Coverage, 2183,
     /* 10880 */   GIR_EraseRootFromParent_Done,
     /* 10881 */ // Label 423: @10881
     /* 10881 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(10998), // Rule ID 2188 //
     /* 10886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 10889 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 10892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10896 */   // (bitconvert:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2i64:{ *:[v2i64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 10896 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /* 10899 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10903 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10908 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 10912 */   GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10917 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 10920 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 10924 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10929 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 10932 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
     /* 10935 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 10937 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 10940 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10944 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10949 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 10952 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 10957 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 10960 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /* 10964 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 10969 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 10972 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 10982 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 10984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 10987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 10989 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 10992 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 10997 */   // GIR_Coverage, 2188,
     /* 10997 */   GIR_EraseRootFromParent_Done,
     /* 10998 */ // Label 424: @10998
     /* 10998 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(11115), // Rule ID 2193 //
     /* 11003 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_IsBE),
     /* 11006 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 11009 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 11013 */   // (bitconvert:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src)  =>  (COPY_TO_REGCLASS:{ *:[v16i8] } (SHF_W:{ *:[v4i32] } (COPY_TO_REGCLASS:{ *:[v4i32] } (SHF_B:{ *:[v16i8] } (COPY_TO_REGCLASS:{ *:[v16i8] } v2f64:{ *:[v2f64] }:$src, MSA128B:{ *:[i32] }), 27:{ *:[i32] }), MSA128W:{ *:[i32] }), 177:{ *:[i32] }), MSA128B:{ *:[i32] })
     /* 11013 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
     /* 11016 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 11020 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 11025 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 11029 */   GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 11034 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
     /* 11037 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SHF_B),
     /* 11041 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 11046 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 11049 */   GIR_AddImm8, /*InsnID*/3, /*Imm*/27,
     /* 11052 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 11054 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
     /* 11057 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 11061 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 11066 */   GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
     /* 11069 */   GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 11074 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
     /* 11077 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SHF_W),
     /* 11081 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 11086 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 11089 */   GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(177),
     /* 11099 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 11101 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 11104 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 11106 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 11109 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 11114 */   // GIR_Coverage, 2193,
     /* 11114 */   GIR_EraseRootFromParent_Done,
     /* 11115 */ // Label 425: @11115
     /* 11115 */ GIM_Reject,
     /* 11116 */ // Label 333: @11116
     /* 11116 */ GIM_Reject,
     /* 11117 */ // Label 13: @11117
     /* 11117 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(11181), // Rule ID 2116 //
     /* 11122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 11125 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 11128 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 11131 */   GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
     /* 11135 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11139 */   // MIs[0] Operand 1
     /* 11139 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
     /* 11143 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 11147 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 11151 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 11155 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 11159 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 11161 */   // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_load>>  =>  (LWX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
     /* 11161 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
     /* 11164 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 11166 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
     /* 11170 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
     /* 11174 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 11179 */   GIR_RootConstrainSelectedInstOperands,
     /* 11180 */   // GIR_Coverage, 2116,
     /* 11180 */   GIR_EraseRootFromParent_Done,
     /* 11181 */ // Label 426: @11181
     /* 11181 */ GIM_Reject,
     /* 11182 */ // Label 14: @11182
     /* 11182 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(11249), // Rule ID 2115 //
     /* 11187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 11190 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 11193 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 11196 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 11203 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11207 */   // MIs[0] Operand 1
     /* 11207 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
     /* 11211 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 11215 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 11219 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 11223 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 11227 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 11229 */   // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>>  =>  (LHX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
     /* 11229 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
     /* 11232 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 11234 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
     /* 11238 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
     /* 11242 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 11247 */   GIR_RootConstrainSelectedInstOperands,
     /* 11248 */   // GIR_Coverage, 2115,
     /* 11248 */   GIR_EraseRootFromParent_Done,
     /* 11249 */ // Label 427: @11249
     /* 11249 */ GIM_Reject,
     /* 11250 */ // Label 15: @11250
     /* 11250 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(11317), // Rule ID 2114 //
     /* 11255 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 11258 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 11261 */   GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
     /* 11264 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 11271 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11275 */   // MIs[0] Operand 1
     /* 11275 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
     /* 11279 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 11283 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 11287 */   GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 11291 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 11295 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 11297 */   // (ld:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>>  =>  (LBUX:{ *:[i32] } i32:{ *:[i32] }:$base, i32:{ *:[i32] }:$index)
     /* 11297 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
     /* 11300 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 11302 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // base
     /* 11306 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // index
     /* 11310 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 11315 */   GIR_RootConstrainSelectedInstOperands,
     /* 11316 */   // GIR_Coverage, 2114,
     /* 11316 */   GIR_EraseRootFromParent_Done,
     /* 11317 */ // Label 428: @11317
     /* 11317 */ GIM_Reject,
     /* 11318 */ // Label 16: @11318
     /* 11318 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 431*/ GIMT_Encode4(11509),
     /* 11329 */ /*GILLT_s32*//*Label 429*/ GIMT_Encode4(11337),
     /* 11333 */ /*GILLT_s64*//*Label 430*/ GIMT_Encode4(11464),
     /* 11337 */ // Label 429: @11337
     /* 11337 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(11463),
     /* 11342 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 11345 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 11348 */   GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(11386), // Rule ID 25 //
     /* 11353 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11356 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 11363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11367 */     // MIs[0] ptr
     /* 11367 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11371 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11375 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11379 */     // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i8>>  =>  (ATOMIC_CMP_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
     /* 11379 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I8),
     /* 11384 */     GIR_RootConstrainSelectedInstOperands,
     /* 11385 */     // GIR_Coverage, 25,
     /* 11385 */     GIR_Done,
     /* 11386 */   // Label 433: @11386
     /* 11386 */   GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(11424), // Rule ID 26 //
     /* 11391 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11394 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 11401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11405 */     // MIs[0] ptr
     /* 11405 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11413 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11417 */     // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i16>>  =>  (ATOMIC_CMP_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
     /* 11417 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I16),
     /* 11422 */     GIR_RootConstrainSelectedInstOperands,
     /* 11423 */     // GIR_Coverage, 26,
     /* 11423 */     GIR_Done,
     /* 11424 */   // Label 434: @11424
     /* 11424 */   GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(11462), // Rule ID 27 //
     /* 11429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11432 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 11439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11443 */     // MIs[0] ptr
     /* 11443 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11447 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11451 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11455 */     // (atomic_cmp_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_i32>>  =>  (ATOMIC_CMP_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$cmp, GPR32:{ *:[i32] }:$swap)
     /* 11455 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I32),
     /* 11460 */     GIR_RootConstrainSelectedInstOperands,
     /* 11461 */     // GIR_Coverage, 27,
     /* 11461 */     GIR_Done,
     /* 11462 */   // Label 435: @11462
     /* 11462 */   GIM_Reject,
     /* 11463 */ // Label 432: @11463
     /* 11463 */ GIM_Reject,
     /* 11464 */ // Label 430: @11464
     /* 11464 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(11508), // Rule ID 266 //
     /* 11469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11472 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 11475 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 11478 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 11485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11489 */   // MIs[0] ptr
     /* 11489 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11493 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11497 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11501 */   // (atomic_cmp_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_i64>>  =>  (ATOMIC_CMP_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$cmp, GPR64:{ *:[i64] }:$swap)
     /* 11501 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_CMP_SWAP_I64),
     /* 11506 */   GIR_RootConstrainSelectedInstOperands,
     /* 11507 */   // GIR_Coverage, 266,
     /* 11507 */   GIR_Done,
     /* 11508 */ // Label 436: @11508
     /* 11508 */ GIM_Reject,
     /* 11509 */ // Label 431: @11509
     /* 11509 */ GIM_Reject,
     /* 11510 */ // Label 17: @11510
     /* 11510 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 439*/ GIMT_Encode4(11679),
     /* 11521 */ /*GILLT_s32*//*Label 437*/ GIMT_Encode4(11529),
     /* 11525 */ /*GILLT_s64*//*Label 438*/ GIMT_Encode4(11641),
     /* 11529 */ // Label 437: @11529
     /* 11529 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(11640),
     /* 11534 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 11537 */   GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(11571), // Rule ID 22 //
     /* 11542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11545 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 11552 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11556 */     // MIs[0] ptr
     /* 11556 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11560 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11564 */     // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i8>>  =>  (ATOMIC_SWAP_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11564 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I8),
     /* 11569 */     GIR_RootConstrainSelectedInstOperands,
     /* 11570 */     // GIR_Coverage, 22,
     /* 11570 */     GIR_Done,
     /* 11571 */   // Label 441: @11571
     /* 11571 */   GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(11605), // Rule ID 23 //
     /* 11576 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11579 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 11586 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11590 */     // MIs[0] ptr
     /* 11590 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11594 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11598 */     // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i16>>  =>  (ATOMIC_SWAP_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11598 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I16),
     /* 11603 */     GIR_RootConstrainSelectedInstOperands,
     /* 11604 */     // GIR_Coverage, 23,
     /* 11604 */     GIR_Done,
     /* 11605 */   // Label 442: @11605
     /* 11605 */   GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(11639), // Rule ID 24 //
     /* 11610 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11613 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 11620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11624 */     // MIs[0] ptr
     /* 11624 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11628 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11632 */     // (atomic_swap:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_swap_i32>>  =>  (ATOMIC_SWAP_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11632 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I32),
     /* 11637 */     GIR_RootConstrainSelectedInstOperands,
     /* 11638 */     // GIR_Coverage, 24,
     /* 11638 */     GIR_Done,
     /* 11639 */   // Label 443: @11639
     /* 11639 */   GIM_Reject,
     /* 11640 */ // Label 440: @11640
     /* 11640 */ GIM_Reject,
     /* 11641 */ // Label 438: @11641
     /* 11641 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(11678), // Rule ID 265 //
     /* 11646 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11649 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 11652 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 11659 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11663 */   // MIs[0] ptr
     /* 11663 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11667 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11671 */   // (atomic_swap:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_swap_i64>>  =>  (ATOMIC_SWAP_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 11671 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_SWAP_I64),
     /* 11676 */   GIR_RootConstrainSelectedInstOperands,
     /* 11677 */   // GIR_Coverage, 265,
     /* 11677 */   GIR_Done,
     /* 11678 */ // Label 444: @11678
     /* 11678 */ GIM_Reject,
     /* 11679 */ // Label 439: @11679
     /* 11679 */ GIM_Reject,
     /* 11680 */ // Label 18: @11680
     /* 11680 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 447*/ GIMT_Encode4(11849),
     /* 11691 */ /*GILLT_s32*//*Label 445*/ GIMT_Encode4(11699),
     /* 11695 */ /*GILLT_s64*//*Label 446*/ GIMT_Encode4(11811),
     /* 11699 */ // Label 445: @11699
     /* 11699 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(11810),
     /* 11704 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 11707 */   GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(11741), // Rule ID 4 //
     /* 11712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11715 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 11722 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11726 */     // MIs[0] ptr
     /* 11726 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11734 */     // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i8>>  =>  (ATOMIC_LOAD_ADD_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11734 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I8),
     /* 11739 */     GIR_RootConstrainSelectedInstOperands,
     /* 11740 */     // GIR_Coverage, 4,
     /* 11740 */     GIR_Done,
     /* 11741 */   // Label 449: @11741
     /* 11741 */   GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(11775), // Rule ID 5 //
     /* 11746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11749 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 11756 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11760 */     // MIs[0] ptr
     /* 11760 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11768 */     // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i16>>  =>  (ATOMIC_LOAD_ADD_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11768 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I16),
     /* 11773 */     GIR_RootConstrainSelectedInstOperands,
     /* 11774 */     // GIR_Coverage, 5,
     /* 11774 */     GIR_Done,
     /* 11775 */   // Label 450: @11775
     /* 11775 */   GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(11809), // Rule ID 6 //
     /* 11780 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11783 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 11790 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11794 */     // MIs[0] ptr
     /* 11794 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11798 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11802 */     // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_add_i32>>  =>  (ATOMIC_LOAD_ADD_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11802 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I32),
     /* 11807 */     GIR_RootConstrainSelectedInstOperands,
     /* 11808 */     // GIR_Coverage, 6,
     /* 11808 */     GIR_Done,
     /* 11809 */   // Label 451: @11809
     /* 11809 */   GIM_Reject,
     /* 11810 */ // Label 448: @11810
     /* 11810 */ GIM_Reject,
     /* 11811 */ // Label 446: @11811
     /* 11811 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(11848), // Rule ID 259 //
     /* 11816 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11819 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 11822 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 11829 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11833 */   // MIs[0] ptr
     /* 11833 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11837 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 11841 */   // (atomic_load_add:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_add_i64>>  =>  (ATOMIC_LOAD_ADD_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 11841 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_ADD_I64),
     /* 11846 */   GIR_RootConstrainSelectedInstOperands,
     /* 11847 */   // GIR_Coverage, 259,
     /* 11847 */   GIR_Done,
     /* 11848 */ // Label 452: @11848
     /* 11848 */ GIM_Reject,
     /* 11849 */ // Label 447: @11849
     /* 11849 */ GIM_Reject,
     /* 11850 */ // Label 19: @11850
     /* 11850 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 455*/ GIMT_Encode4(12019),
     /* 11861 */ /*GILLT_s32*//*Label 453*/ GIMT_Encode4(11869),
     /* 11865 */ /*GILLT_s64*//*Label 454*/ GIMT_Encode4(11981),
     /* 11869 */ // Label 453: @11869
     /* 11869 */ GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(11980),
     /* 11874 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 11877 */   GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(11911), // Rule ID 7 //
     /* 11882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11885 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 11892 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11896 */     // MIs[0] ptr
     /* 11896 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11904 */     // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i8>>  =>  (ATOMIC_LOAD_SUB_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11904 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I8),
     /* 11909 */     GIR_RootConstrainSelectedInstOperands,
     /* 11910 */     // GIR_Coverage, 7,
     /* 11910 */     GIR_Done,
     /* 11911 */   // Label 457: @11911
     /* 11911 */   GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(11945), // Rule ID 8 //
     /* 11916 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11919 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 11926 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11930 */     // MIs[0] ptr
     /* 11930 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11934 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11938 */     // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i16>>  =>  (ATOMIC_LOAD_SUB_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11938 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I16),
     /* 11943 */     GIR_RootConstrainSelectedInstOperands,
     /* 11944 */     // GIR_Coverage, 8,
     /* 11944 */     GIR_Done,
     /* 11945 */   // Label 458: @11945
     /* 11945 */   GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(11979), // Rule ID 9 //
     /* 11950 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11953 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 11960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11964 */     // MIs[0] ptr
     /* 11964 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 11968 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 11972 */     // (atomic_load_sub:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_i32>>  =>  (ATOMIC_LOAD_SUB_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 11972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I32),
     /* 11977 */     GIR_RootConstrainSelectedInstOperands,
     /* 11978 */     // GIR_Coverage, 9,
     /* 11978 */     GIR_Done,
     /* 11979 */   // Label 459: @11979
     /* 11979 */   GIM_Reject,
     /* 11980 */ // Label 456: @11980
     /* 11980 */ GIM_Reject,
     /* 11981 */ // Label 454: @11981
     /* 11981 */ GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(12018), // Rule ID 260 //
     /* 11986 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 11989 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 11992 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 11999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12003 */   // MIs[0] ptr
     /* 12003 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12007 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12011 */   // (atomic_load_sub:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_i64>>  =>  (ATOMIC_LOAD_SUB_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12011 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_SUB_I64),
     /* 12016 */   GIR_RootConstrainSelectedInstOperands,
     /* 12017 */   // GIR_Coverage, 260,
     /* 12017 */   GIR_Done,
     /* 12018 */ // Label 460: @12018
     /* 12018 */ GIM_Reject,
     /* 12019 */ // Label 455: @12019
     /* 12019 */ GIM_Reject,
     /* 12020 */ // Label 20: @12020
     /* 12020 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 463*/ GIMT_Encode4(12189),
     /* 12031 */ /*GILLT_s32*//*Label 461*/ GIMT_Encode4(12039),
     /* 12035 */ /*GILLT_s64*//*Label 462*/ GIMT_Encode4(12151),
     /* 12039 */ // Label 461: @12039
     /* 12039 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(12150),
     /* 12044 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12047 */   GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(12081), // Rule ID 10 //
     /* 12052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12055 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12062 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12066 */     // MIs[0] ptr
     /* 12066 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12074 */     // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i8>>  =>  (ATOMIC_LOAD_AND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12074 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I8),
     /* 12079 */     GIR_RootConstrainSelectedInstOperands,
     /* 12080 */     // GIR_Coverage, 10,
     /* 12080 */     GIR_Done,
     /* 12081 */   // Label 465: @12081
     /* 12081 */   GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(12115), // Rule ID 11 //
     /* 12086 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12089 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12100 */     // MIs[0] ptr
     /* 12100 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12104 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12108 */     // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i16>>  =>  (ATOMIC_LOAD_AND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12108 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I16),
     /* 12113 */     GIR_RootConstrainSelectedInstOperands,
     /* 12114 */     // GIR_Coverage, 11,
     /* 12114 */     GIR_Done,
     /* 12115 */   // Label 466: @12115
     /* 12115 */   GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(12149), // Rule ID 12 //
     /* 12120 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12123 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12130 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12134 */     // MIs[0] ptr
     /* 12134 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12138 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12142 */     // (atomic_load_and:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_and_i32>>  =>  (ATOMIC_LOAD_AND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12142 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I32),
     /* 12147 */     GIR_RootConstrainSelectedInstOperands,
     /* 12148 */     // GIR_Coverage, 12,
     /* 12148 */     GIR_Done,
     /* 12149 */   // Label 467: @12149
     /* 12149 */   GIM_Reject,
     /* 12150 */ // Label 464: @12150
     /* 12150 */ GIM_Reject,
     /* 12151 */ // Label 462: @12151
     /* 12151 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(12188), // Rule ID 261 //
     /* 12156 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12159 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 12162 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 12169 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12173 */   // MIs[0] ptr
     /* 12173 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12177 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12181 */   // (atomic_load_and:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_and_i64>>  =>  (ATOMIC_LOAD_AND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12181 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_AND_I64),
     /* 12186 */   GIR_RootConstrainSelectedInstOperands,
     /* 12187 */   // GIR_Coverage, 261,
     /* 12187 */   GIR_Done,
     /* 12188 */ // Label 468: @12188
     /* 12188 */ GIM_Reject,
     /* 12189 */ // Label 463: @12189
     /* 12189 */ GIM_Reject,
     /* 12190 */ // Label 21: @12190
     /* 12190 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 471*/ GIMT_Encode4(12359),
     /* 12201 */ /*GILLT_s32*//*Label 469*/ GIMT_Encode4(12209),
     /* 12205 */ /*GILLT_s64*//*Label 470*/ GIMT_Encode4(12321),
     /* 12209 */ // Label 469: @12209
     /* 12209 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(12320),
     /* 12214 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12217 */   GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(12251), // Rule ID 19 //
     /* 12222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12225 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12236 */     // MIs[0] ptr
     /* 12236 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12240 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12244 */     // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i8>>  =>  (ATOMIC_LOAD_NAND_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12244 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I8),
     /* 12249 */     GIR_RootConstrainSelectedInstOperands,
     /* 12250 */     // GIR_Coverage, 19,
     /* 12250 */     GIR_Done,
     /* 12251 */   // Label 473: @12251
     /* 12251 */   GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(12285), // Rule ID 20 //
     /* 12256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12259 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12270 */     // MIs[0] ptr
     /* 12270 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12274 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12278 */     // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i16>>  =>  (ATOMIC_LOAD_NAND_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12278 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I16),
     /* 12283 */     GIR_RootConstrainSelectedInstOperands,
     /* 12284 */     // GIR_Coverage, 20,
     /* 12284 */     GIR_Done,
     /* 12285 */   // Label 474: @12285
     /* 12285 */   GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(12319), // Rule ID 21 //
     /* 12290 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12293 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12304 */     // MIs[0] ptr
     /* 12304 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12312 */     // (atomic_load_nand:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_nand_i32>>  =>  (ATOMIC_LOAD_NAND_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12312 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I32),
     /* 12317 */     GIR_RootConstrainSelectedInstOperands,
     /* 12318 */     // GIR_Coverage, 21,
     /* 12318 */     GIR_Done,
     /* 12319 */   // Label 475: @12319
     /* 12319 */   GIM_Reject,
     /* 12320 */ // Label 472: @12320
     /* 12320 */ GIM_Reject,
     /* 12321 */ // Label 470: @12321
     /* 12321 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(12358), // Rule ID 264 //
     /* 12326 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12329 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 12332 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 12339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12343 */   // MIs[0] ptr
     /* 12343 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12347 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12351 */   // (atomic_load_nand:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_nand_i64>>  =>  (ATOMIC_LOAD_NAND_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12351 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_NAND_I64),
     /* 12356 */   GIR_RootConstrainSelectedInstOperands,
     /* 12357 */   // GIR_Coverage, 264,
     /* 12357 */   GIR_Done,
     /* 12358 */ // Label 476: @12358
     /* 12358 */ GIM_Reject,
     /* 12359 */ // Label 471: @12359
     /* 12359 */ GIM_Reject,
     /* 12360 */ // Label 22: @12360
     /* 12360 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 479*/ GIMT_Encode4(12529),
     /* 12371 */ /*GILLT_s32*//*Label 477*/ GIMT_Encode4(12379),
     /* 12375 */ /*GILLT_s64*//*Label 478*/ GIMT_Encode4(12491),
     /* 12379 */ // Label 477: @12379
     /* 12379 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(12490),
     /* 12384 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12387 */   GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(12421), // Rule ID 13 //
     /* 12392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12395 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12406 */     // MIs[0] ptr
     /* 12406 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12410 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12414 */     // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i8>>  =>  (ATOMIC_LOAD_OR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12414 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I8),
     /* 12419 */     GIR_RootConstrainSelectedInstOperands,
     /* 12420 */     // GIR_Coverage, 13,
     /* 12420 */     GIR_Done,
     /* 12421 */   // Label 481: @12421
     /* 12421 */   GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(12455), // Rule ID 14 //
     /* 12426 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12429 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12440 */     // MIs[0] ptr
     /* 12440 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12444 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12448 */     // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i16>>  =>  (ATOMIC_LOAD_OR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12448 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I16),
     /* 12453 */     GIR_RootConstrainSelectedInstOperands,
     /* 12454 */     // GIR_Coverage, 14,
     /* 12454 */     GIR_Done,
     /* 12455 */   // Label 482: @12455
     /* 12455 */   GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(12489), // Rule ID 15 //
     /* 12460 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12463 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12470 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12474 */     // MIs[0] ptr
     /* 12474 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12478 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12482 */     // (atomic_load_or:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_or_i32>>  =>  (ATOMIC_LOAD_OR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12482 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I32),
     /* 12487 */     GIR_RootConstrainSelectedInstOperands,
     /* 12488 */     // GIR_Coverage, 15,
     /* 12488 */     GIR_Done,
     /* 12489 */   // Label 483: @12489
     /* 12489 */   GIM_Reject,
     /* 12490 */ // Label 480: @12490
     /* 12490 */ GIM_Reject,
     /* 12491 */ // Label 478: @12491
     /* 12491 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(12528), // Rule ID 262 //
     /* 12496 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12499 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 12502 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 12509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12513 */   // MIs[0] ptr
     /* 12513 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12517 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12521 */   // (atomic_load_or:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_or_i64>>  =>  (ATOMIC_LOAD_OR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12521 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_OR_I64),
     /* 12526 */   GIR_RootConstrainSelectedInstOperands,
     /* 12527 */   // GIR_Coverage, 262,
     /* 12527 */   GIR_Done,
     /* 12528 */ // Label 484: @12528
     /* 12528 */ GIM_Reject,
     /* 12529 */ // Label 479: @12529
     /* 12529 */ GIM_Reject,
     /* 12530 */ // Label 23: @12530
     /* 12530 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 487*/ GIMT_Encode4(12699),
     /* 12541 */ /*GILLT_s32*//*Label 485*/ GIMT_Encode4(12549),
     /* 12545 */ /*GILLT_s64*//*Label 486*/ GIMT_Encode4(12661),
     /* 12549 */ // Label 485: @12549
     /* 12549 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(12660),
     /* 12554 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12557 */   GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(12591), // Rule ID 16 //
     /* 12562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12565 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12576 */     // MIs[0] ptr
     /* 12576 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12584 */     // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i8>>  =>  (ATOMIC_LOAD_XOR_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12584 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I8),
     /* 12589 */     GIR_RootConstrainSelectedInstOperands,
     /* 12590 */     // GIR_Coverage, 16,
     /* 12590 */     GIR_Done,
     /* 12591 */   // Label 489: @12591
     /* 12591 */   GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(12625), // Rule ID 17 //
     /* 12596 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12599 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12610 */     // MIs[0] ptr
     /* 12610 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12618 */     // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i16>>  =>  (ATOMIC_LOAD_XOR_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12618 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I16),
     /* 12623 */     GIR_RootConstrainSelectedInstOperands,
     /* 12624 */     // GIR_Coverage, 17,
     /* 12624 */     GIR_Done,
     /* 12625 */   // Label 490: @12625
     /* 12625 */   GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(12659), // Rule ID 18 //
     /* 12630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12633 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12640 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12644 */     // MIs[0] ptr
     /* 12644 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12652 */     // (atomic_load_xor:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_xor_i32>>  =>  (ATOMIC_LOAD_XOR_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12652 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I32),
     /* 12657 */     GIR_RootConstrainSelectedInstOperands,
     /* 12658 */     // GIR_Coverage, 18,
     /* 12658 */     GIR_Done,
     /* 12659 */   // Label 491: @12659
     /* 12659 */   GIM_Reject,
     /* 12660 */ // Label 488: @12660
     /* 12660 */ GIM_Reject,
     /* 12661 */ // Label 486: @12661
     /* 12661 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(12698), // Rule ID 263 //
     /* 12666 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12669 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 12672 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 12679 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12683 */   // MIs[0] ptr
     /* 12683 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12687 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12691 */   // (atomic_load_xor:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_xor_i64>>  =>  (ATOMIC_LOAD_XOR_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12691 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_XOR_I64),
     /* 12696 */   GIR_RootConstrainSelectedInstOperands,
     /* 12697 */   // GIR_Coverage, 263,
     /* 12697 */   GIR_Done,
     /* 12698 */ // Label 492: @12698
     /* 12698 */ GIM_Reject,
     /* 12699 */ // Label 487: @12699
     /* 12699 */ GIM_Reject,
     /* 12700 */ // Label 24: @12700
     /* 12700 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 495*/ GIMT_Encode4(12869),
     /* 12711 */ /*GILLT_s32*//*Label 493*/ GIMT_Encode4(12719),
     /* 12715 */ /*GILLT_s64*//*Label 494*/ GIMT_Encode4(12831),
     /* 12719 */ // Label 493: @12719
     /* 12719 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(12830),
     /* 12724 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12727 */   GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(12761), // Rule ID 31 //
     /* 12732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12735 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12742 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12746 */     // MIs[0] ptr
     /* 12746 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12754 */     // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i8>>  =>  (ATOMIC_LOAD_MAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12754 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I8),
     /* 12759 */     GIR_RootConstrainSelectedInstOperands,
     /* 12760 */     // GIR_Coverage, 31,
     /* 12760 */     GIR_Done,
     /* 12761 */   // Label 497: @12761
     /* 12761 */   GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(12795), // Rule ID 32 //
     /* 12766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12769 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12776 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12780 */     // MIs[0] ptr
     /* 12780 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12784 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12788 */     // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i16>>  =>  (ATOMIC_LOAD_MAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12788 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I16),
     /* 12793 */     GIR_RootConstrainSelectedInstOperands,
     /* 12794 */     // GIR_Coverage, 32,
     /* 12794 */     GIR_Done,
     /* 12795 */   // Label 498: @12795
     /* 12795 */   GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(12829), // Rule ID 33 //
     /* 12800 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12803 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12810 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12814 */     // MIs[0] ptr
     /* 12814 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12822 */     // (atomic_load_max:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_max_i32>>  =>  (ATOMIC_LOAD_MAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12822 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I32),
     /* 12827 */     GIR_RootConstrainSelectedInstOperands,
     /* 12828 */     // GIR_Coverage, 33,
     /* 12828 */     GIR_Done,
     /* 12829 */   // Label 499: @12829
     /* 12829 */   GIM_Reject,
     /* 12830 */ // Label 496: @12830
     /* 12830 */ GIM_Reject,
     /* 12831 */ // Label 494: @12831
     /* 12831 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(12868), // Rule ID 268 //
     /* 12836 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12839 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 12842 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 12849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12853 */   // MIs[0] ptr
     /* 12853 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12857 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 12861 */   // (atomic_load_max:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_max_i64>>  =>  (ATOMIC_LOAD_MAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 12861 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MAX_I64),
     /* 12866 */   GIR_RootConstrainSelectedInstOperands,
     /* 12867 */   // GIR_Coverage, 268,
     /* 12867 */   GIR_Done,
     /* 12868 */ // Label 500: @12868
     /* 12868 */ GIM_Reject,
     /* 12869 */ // Label 495: @12869
     /* 12869 */ GIM_Reject,
     /* 12870 */ // Label 25: @12870
     /* 12870 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 503*/ GIMT_Encode4(13039),
     /* 12881 */ /*GILLT_s32*//*Label 501*/ GIMT_Encode4(12889),
     /* 12885 */ /*GILLT_s64*//*Label 502*/ GIMT_Encode4(13001),
     /* 12889 */ // Label 501: @12889
     /* 12889 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(13000),
     /* 12894 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 12897 */   GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(12931), // Rule ID 28 //
     /* 12902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12905 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 12912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12916 */     // MIs[0] ptr
     /* 12916 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12920 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12924 */     // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i8>>  =>  (ATOMIC_LOAD_MIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12924 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I8),
     /* 12929 */     GIR_RootConstrainSelectedInstOperands,
     /* 12930 */     // GIR_Coverage, 28,
     /* 12930 */     GIR_Done,
     /* 12931 */   // Label 505: @12931
     /* 12931 */   GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(12965), // Rule ID 29 //
     /* 12936 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12939 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 12946 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12950 */     // MIs[0] ptr
     /* 12950 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12954 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12958 */     // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i16>>  =>  (ATOMIC_LOAD_MIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12958 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I16),
     /* 12963 */     GIR_RootConstrainSelectedInstOperands,
     /* 12964 */     // GIR_Coverage, 29,
     /* 12964 */     GIR_Done,
     /* 12965 */   // Label 506: @12965
     /* 12965 */   GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(12999), // Rule ID 30 //
     /* 12970 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 12973 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 12980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12984 */     // MIs[0] ptr
     /* 12984 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 12988 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 12992 */     // (atomic_load_min:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_min_i32>>  =>  (ATOMIC_LOAD_MIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 12992 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I32),
     /* 12997 */     GIR_RootConstrainSelectedInstOperands,
     /* 12998 */     // GIR_Coverage, 30,
     /* 12998 */     GIR_Done,
     /* 12999 */   // Label 507: @12999
     /* 12999 */   GIM_Reject,
     /* 13000 */ // Label 504: @13000
     /* 13000 */ GIM_Reject,
     /* 13001 */ // Label 502: @13001
     /* 13001 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(13038), // Rule ID 267 //
     /* 13006 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13009 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 13012 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 13019 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13023 */   // MIs[0] ptr
     /* 13023 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13027 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13031 */   // (atomic_load_min:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_min_i64>>  =>  (ATOMIC_LOAD_MIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 13031 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_MIN_I64),
     /* 13036 */   GIR_RootConstrainSelectedInstOperands,
     /* 13037 */   // GIR_Coverage, 267,
     /* 13037 */   GIR_Done,
     /* 13038 */ // Label 508: @13038
     /* 13038 */ GIM_Reject,
     /* 13039 */ // Label 503: @13039
     /* 13039 */ GIM_Reject,
     /* 13040 */ // Label 26: @13040
     /* 13040 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 511*/ GIMT_Encode4(13209),
     /* 13051 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(13059),
     /* 13055 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(13171),
     /* 13059 */ // Label 509: @13059
     /* 13059 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(13170),
     /* 13064 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 13067 */   GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(13101), // Rule ID 37 //
     /* 13072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13075 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 13082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13086 */     // MIs[0] ptr
     /* 13086 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13094 */     // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i8>>  =>  (ATOMIC_LOAD_UMAX_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13094 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I8),
     /* 13099 */     GIR_RootConstrainSelectedInstOperands,
     /* 13100 */     // GIR_Coverage, 37,
     /* 13100 */     GIR_Done,
     /* 13101 */   // Label 513: @13101
     /* 13101 */   GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(13135), // Rule ID 38 //
     /* 13106 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13109 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 13116 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13120 */     // MIs[0] ptr
     /* 13120 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13124 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13128 */     // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i16>>  =>  (ATOMIC_LOAD_UMAX_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13128 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I16),
     /* 13133 */     GIR_RootConstrainSelectedInstOperands,
     /* 13134 */     // GIR_Coverage, 38,
     /* 13134 */     GIR_Done,
     /* 13135 */   // Label 514: @13135
     /* 13135 */   GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(13169), // Rule ID 39 //
     /* 13140 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13143 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 13150 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13154 */     // MIs[0] ptr
     /* 13154 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13158 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13162 */     // (atomic_load_umax:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umax_i32>>  =>  (ATOMIC_LOAD_UMAX_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13162 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I32),
     /* 13167 */     GIR_RootConstrainSelectedInstOperands,
     /* 13168 */     // GIR_Coverage, 39,
     /* 13168 */     GIR_Done,
     /* 13169 */   // Label 515: @13169
     /* 13169 */   GIM_Reject,
     /* 13170 */ // Label 512: @13170
     /* 13170 */ GIM_Reject,
     /* 13171 */ // Label 510: @13171
     /* 13171 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(13208), // Rule ID 270 //
     /* 13176 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13179 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 13182 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 13189 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13193 */   // MIs[0] ptr
     /* 13193 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13197 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13201 */   // (atomic_load_umax:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umax_i64>>  =>  (ATOMIC_LOAD_UMAX_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 13201 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMAX_I64),
     /* 13206 */   GIR_RootConstrainSelectedInstOperands,
     /* 13207 */   // GIR_Coverage, 270,
     /* 13207 */   GIR_Done,
     /* 13208 */ // Label 516: @13208
     /* 13208 */ GIM_Reject,
     /* 13209 */ // Label 511: @13209
     /* 13209 */ GIM_Reject,
     /* 13210 */ // Label 27: @13210
     /* 13210 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 519*/ GIMT_Encode4(13379),
     /* 13221 */ /*GILLT_s32*//*Label 517*/ GIMT_Encode4(13229),
     /* 13225 */ /*GILLT_s64*//*Label 518*/ GIMT_Encode4(13341),
     /* 13229 */ // Label 517: @13229
     /* 13229 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(13340),
     /* 13234 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 13237 */   GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(13271), // Rule ID 34 //
     /* 13242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13245 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
     /* 13252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13256 */     // MIs[0] ptr
     /* 13256 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13264 */     // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i8>>  =>  (ATOMIC_LOAD_UMIN_I8:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13264 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I8),
     /* 13269 */     GIR_RootConstrainSelectedInstOperands,
     /* 13270 */     // GIR_Coverage, 34,
     /* 13270 */     GIR_Done,
     /* 13271 */   // Label 521: @13271
     /* 13271 */   GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(13305), // Rule ID 35 //
     /* 13276 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13279 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
     /* 13286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13290 */     // MIs[0] ptr
     /* 13290 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13298 */     // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i16>>  =>  (ATOMIC_LOAD_UMIN_I16:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13298 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I16),
     /* 13303 */     GIR_RootConstrainSelectedInstOperands,
     /* 13304 */     // GIR_Coverage, 35,
     /* 13304 */     GIR_Done,
     /* 13305 */   // Label 522: @13305
     /* 13305 */   GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(13339), // Rule ID 36 //
     /* 13310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13313 */     GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
     /* 13320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13324 */     // MIs[0] ptr
     /* 13324 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 13332 */     // (atomic_load_umin:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_umin_i32>>  =>  (ATOMIC_LOAD_UMIN_I32:{ *:[i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$incr)
     /* 13332 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I32),
     /* 13337 */     GIR_RootConstrainSelectedInstOperands,
     /* 13338 */     // GIR_Coverage, 36,
     /* 13338 */     GIR_Done,
     /* 13339 */   // Label 523: @13339
     /* 13339 */   GIM_Reject,
     /* 13340 */ // Label 520: @13340
     /* 13340 */ GIM_Reject,
     /* 13341 */ // Label 518: @13341
     /* 13341 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(13378), // Rule ID 269 //
     /* 13346 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 13349 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 13352 */   GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
     /* 13359 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13363 */   // MIs[0] ptr
     /* 13363 */   GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
     /* 13367 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13371 */   // (atomic_load_umin:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_umin_i64>>  =>  (ATOMIC_LOAD_UMIN_I64:{ *:[i64] } iPTR:{ *:[iPTR] }:$ptr, GPR64:{ *:[i64] }:$incr)
     /* 13371 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ATOMIC_LOAD_UMIN_I64),
     /* 13376 */   GIR_RootConstrainSelectedInstOperands,
     /* 13377 */   // GIR_Coverage, 269,
     /* 13377 */   GIR_Done,
     /* 13378 */ // Label 524: @13378
     /* 13378 */ GIM_Reject,
     /* 13379 */ // Label 519: @13379
     /* 13379 */ GIM_Reject,
     /* 13380 */ // Label 28: @13380
     /* 13380 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 527*/ GIMT_Encode4(19924),
     /* 13391 */ /*GILLT_s32*//*Label 525*/ GIMT_Encode4(13399),
     /* 13395 */ /*GILLT_s64*//*Label 526*/ GIMT_Encode4(19890),
     /* 13399 */ // Label 525: @13399
     /* 13399 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(13507), // Rule ID 2526 //
     /* 13404 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13407 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13411 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13415 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13419 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13423 */   // MIs[1] Operand 1
     /* 13423 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 13428 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13432 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13436 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13440 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13444 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 13448 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 13452 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 13456 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 13460 */   GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
     /* 13464 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 13468 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 13472 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 13476 */   // MIs[4] Operand 1
     /* 13476 */   // No operand predicates
     /* 13476 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13481 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 13485 */   // MIs[0] offset
     /* 13485 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 13488 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 13490 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 13490 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
     /* 13493 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
     /* 13497 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 13500 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 13502 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 13505 */   GIR_RootConstrainSelectedInstOperands,
     /* 13506 */   // GIR_Coverage, 2526,
     /* 13506 */   GIR_EraseRootFromParent_Done,
     /* 13507 */ // Label 528: @13507
     /* 13507 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(13622), // Rule ID 2527 //
     /* 13512 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13515 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13519 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13523 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13527 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13531 */   // MIs[1] Operand 1
     /* 13531 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 13536 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13540 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13544 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13548 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13552 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 13556 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 13560 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 13564 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 13568 */   GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
     /* 13579 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 13583 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 13587 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 13591 */   // MIs[4] Operand 1
     /* 13591 */   // No operand predicates
     /* 13591 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13596 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 13600 */   // MIs[0] offset
     /* 13600 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 13603 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 13605 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 13605 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
     /* 13608 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
     /* 13612 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 13615 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 13617 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 13620 */   GIR_RootConstrainSelectedInstOperands,
     /* 13621 */   // GIR_Coverage, 2527,
     /* 13621 */   GIR_EraseRootFromParent_Done,
     /* 13622 */ // Label 529: @13622
     /* 13622 */ GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(13730), // Rule ID 2528 //
     /* 13627 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13630 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13634 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13638 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13642 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13646 */   // MIs[1] Operand 1
     /* 13646 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 13651 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13655 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13659 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13663 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13667 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 13671 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 13675 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 13679 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 13683 */   GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
     /* 13687 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 13691 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 13695 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 13699 */   // MIs[4] Operand 1
     /* 13699 */   // No operand predicates
     /* 13699 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13704 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 13708 */   // MIs[0] offset
     /* 13708 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 13711 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 13713 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 13713 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
     /* 13716 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
     /* 13720 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 13723 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 13725 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 13728 */   GIR_RootConstrainSelectedInstOperands,
     /* 13729 */   // GIR_Coverage, 2528,
     /* 13729 */   GIR_EraseRootFromParent_Done,
     /* 13730 */ // Label 530: @13730
     /* 13730 */ GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(13845), // Rule ID 2529 //
     /* 13735 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13738 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13742 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13746 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13750 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13754 */   // MIs[1] Operand 1
     /* 13754 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 13759 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13763 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13767 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13771 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13775 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 13779 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 13783 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 13787 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 13791 */   GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
     /* 13802 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 13806 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 13810 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 13814 */   // MIs[4] Operand 1
     /* 13814 */   // No operand predicates
     /* 13814 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13819 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 13823 */   // MIs[0] offset
     /* 13823 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 13826 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 13828 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p), GPR64Opnd:{ *:[i64] }:$rs), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 13828 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
     /* 13831 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // rs
     /* 13835 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 13838 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 13840 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 13843 */   GIR_RootConstrainSelectedInstOperands,
     /* 13844 */   // GIR_Coverage, 2529,
     /* 13844 */   GIR_EraseRootFromParent_Done,
     /* 13845 */ // Label 531: @13845
     /* 13845 */ GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(13953), // Rule ID 345 //
     /* 13850 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13853 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13857 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13861 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13865 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13869 */   // MIs[1] Operand 1
     /* 13869 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 13874 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13878 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13882 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13886 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13890 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 13895 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 13899 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 13903 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 13907 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 13911 */   GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
     /* 13915 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 13919 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 13923 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 13927 */   // MIs[4] Operand 1
     /* 13927 */   // No operand predicates
     /* 13927 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 13931 */   // MIs[0] offset
     /* 13931 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 13934 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 13936 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT0 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 13936 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT0),
     /* 13939 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
     /* 13943 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 13946 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 13948 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 13951 */   GIR_RootConstrainSelectedInstOperands,
     /* 13952 */   // GIR_Coverage, 345,
     /* 13952 */   GIR_EraseRootFromParent_Done,
     /* 13953 */ // Label 532: @13953
     /* 13953 */ GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(14068), // Rule ID 346 //
     /* 13958 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 13961 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 13965 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 13969 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 13973 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 13977 */   // MIs[1] Operand 1
     /* 13977 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 13982 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 13986 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 13990 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 13994 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 13998 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14003 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 14007 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 14011 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 14015 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 14019 */   GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
     /* 14030 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 14034 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 14038 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 14042 */   // MIs[4] Operand 1
     /* 14042 */   // No operand predicates
     /* 14042 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14046 */   // MIs[0] offset
     /* 14046 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14049 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 14051 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT032 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 14051 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT032),
     /* 14054 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
     /* 14058 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 14061 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14063 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14066 */   GIR_RootConstrainSelectedInstOperands,
     /* 14067 */   // GIR_Coverage, 346,
     /* 14067 */   GIR_EraseRootFromParent_Done,
     /* 14068 */ // Label 533: @14068
     /* 14068 */ GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(14176), // Rule ID 347 //
     /* 14073 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 14076 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14080 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14084 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14088 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14092 */   // MIs[1] Operand 1
     /* 14092 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 14097 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 14101 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 14105 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 14109 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 14113 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14118 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 14122 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 14126 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 14130 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 14134 */   GIM_CheckConstantInt8, /*MI*/3, /*Op*/1, 1,
     /* 14138 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 14142 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 14146 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 14150 */   // MIs[4] Operand 1
     /* 14150 */   // No operand predicates
     /* 14150 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14154 */   // MIs[0] offset
     /* 14154 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14157 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 14159 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 1:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT1 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 14159 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT1),
     /* 14162 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
     /* 14166 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 14169 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14171 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14174 */   GIR_RootConstrainSelectedInstOperands,
     /* 14175 */   // GIR_Coverage, 347,
     /* 14175 */   GIR_EraseRootFromParent_Done,
     /* 14176 */ // Label 534: @14176
     /* 14176 */ GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(14291), // Rule ID 348 //
     /* 14181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 14184 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14188 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14192 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14196 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14200 */   // MIs[1] Operand 1
     /* 14200 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 14205 */   GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 14209 */   GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
     /* 14213 */   GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 14217 */   GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 14221 */   GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14226 */   GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
     /* 14230 */   GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 14234 */   GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
     /* 14238 */   GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
     /* 14242 */   GIM_CheckConstantInt, /*MI*/3, /*Op*/1, GIMT_Encode8(4294967296),
     /* 14253 */   GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
     /* 14257 */   GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 14261 */   GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5_64),
     /* 14265 */   // MIs[4] Operand 1
     /* 14265 */   // No operand predicates
     /* 14265 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14269 */   // MIs[0] offset
     /* 14269 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14272 */   GIM_CheckIsSafeToFold, /*NumInsns*/4,
     /* 14274 */   // (brcond (setcc:{ *:[i32] } (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (shl:{ *:[i64] } 4294967296:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_immZExt5_64>>:$p)), 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BBIT132 GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i64] }):$p, (bb:{ *:[Other] }):$offset)
     /* 14274 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BBIT132),
     /* 14277 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs
     /* 14281 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // p
     /* 14284 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14286 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14289 */   GIR_RootConstrainSelectedInstOperands,
     /* 14290 */   // GIR_Coverage, 348,
     /* 14290 */   GIR_EraseRootFromParent_Done,
     /* 14291 */ // Label 535: @14291
     /* 14291 */ GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(14348), // Rule ID 94 //
     /* 14296 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 14299 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14303 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14307 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14311 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14315 */   // MIs[1] Operand 1
     /* 14315 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 14320 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14325 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14329 */   // MIs[0] offset
     /* 14329 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14332 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14334 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14334 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
     /* 14337 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14341 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14343 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14346 */   GIR_RootConstrainSelectedInstOperands,
     /* 14347 */   // GIR_Coverage, 94,
     /* 14347 */   GIR_EraseRootFromParent_Done,
     /* 14348 */ // Label 536: @14348
     /* 14348 */ GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(14405), // Rule ID 95 //
     /* 14353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 14356 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14360 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14364 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14368 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14372 */   // MIs[1] Operand 1
     /* 14372 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 14377 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14382 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14386 */   // MIs[0] offset
     /* 14386 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14389 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14391 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ),
     /* 14394 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14398 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14400 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14403 */   GIR_RootConstrainSelectedInstOperands,
     /* 14404 */   // GIR_Coverage, 95,
     /* 14404 */   GIR_EraseRootFromParent_Done,
     /* 14405 */ // Label 537: @14405
     /* 14405 */ GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(14462), // Rule ID 96 //
     /* 14410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 14413 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14417 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14421 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14425 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14429 */   // MIs[1] Operand 1
     /* 14429 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 14434 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14439 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14443 */   // MIs[0] offset
     /* 14443 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14446 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14448 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14448 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
     /* 14451 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14455 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14457 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14460 */   GIR_RootConstrainSelectedInstOperands,
     /* 14461 */   // GIR_Coverage, 96,
     /* 14461 */   GIR_EraseRootFromParent_Done,
     /* 14462 */ // Label 538: @14462
     /* 14462 */ GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(14519), // Rule ID 97 //
     /* 14467 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 14470 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14474 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14478 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14482 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14486 */   // MIs[1] Operand 1
     /* 14486 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 14491 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14496 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14500 */   // MIs[0] offset
     /* 14500 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14503 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14505 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14505 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ),
     /* 14508 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14512 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14514 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14517 */   GIR_RootConstrainSelectedInstOperands,
     /* 14518 */   // GIR_Coverage, 97,
     /* 14518 */   GIR_EraseRootFromParent_Done,
     /* 14519 */ // Label 539: @14519
     /* 14519 */ GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(14576), // Rule ID 320 //
     /* 14524 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 14527 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14531 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14535 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14539 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14543 */   // MIs[1] Operand 1
     /* 14543 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 14548 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14553 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14557 */   // MIs[0] offset
     /* 14557 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14560 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14562 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14562 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
     /* 14565 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14569 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14571 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14574 */   GIR_RootConstrainSelectedInstOperands,
     /* 14575 */   // GIR_Coverage, 320,
     /* 14575 */   GIR_EraseRootFromParent_Done,
     /* 14576 */ // Label 540: @14576
     /* 14576 */ GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(14633), // Rule ID 321 //
     /* 14581 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 14584 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14588 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14592 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14596 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14600 */   // MIs[1] Operand 1
     /* 14600 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 14605 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14610 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14614 */   // MIs[0] offset
     /* 14614 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14617 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14619 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14619 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ64),
     /* 14622 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14626 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14628 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14631 */   GIR_RootConstrainSelectedInstOperands,
     /* 14632 */   // GIR_Coverage, 321,
     /* 14632 */   GIR_EraseRootFromParent_Done,
     /* 14633 */ // Label 541: @14633
     /* 14633 */ GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(14690), // Rule ID 322 //
     /* 14638 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 14641 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14645 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14649 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14653 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14657 */   // MIs[1] Operand 1
     /* 14657 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 14662 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14667 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14671 */   // MIs[0] offset
     /* 14671 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14674 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14676 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14676 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
     /* 14679 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14683 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14685 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14688 */   GIR_RootConstrainSelectedInstOperands,
     /* 14689 */   // GIR_Coverage, 322,
     /* 14689 */   GIR_EraseRootFromParent_Done,
     /* 14690 */ // Label 542: @14690
     /* 14690 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(14747), // Rule ID 323 //
     /* 14695 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 14698 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14702 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14706 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 14710 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 14714 */   // MIs[1] Operand 1
     /* 14714 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 14719 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 14724 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14728 */   // MIs[0] offset
     /* 14728 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14731 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14733 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14733 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ64),
     /* 14736 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14740 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14742 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14745 */   GIR_RootConstrainSelectedInstOperands,
     /* 14746 */   // GIR_Coverage, 323,
     /* 14746 */   GIR_EraseRootFromParent_Done,
     /* 14747 */ // Label 543: @14747
     /* 14747 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(14804), // Rule ID 1184 //
     /* 14752 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 14755 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14759 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14763 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14767 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14771 */   // MIs[1] Operand 1
     /* 14771 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 14776 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14781 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14785 */   // MIs[0] offset
     /* 14785 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14788 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14790 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14790 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
     /* 14793 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14797 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14799 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14802 */   GIR_RootConstrainSelectedInstOperands,
     /* 14803 */   // GIR_Coverage, 1184,
     /* 14803 */   GIR_EraseRootFromParent_Done,
     /* 14804 */ // Label 544: @14804
     /* 14804 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(14861), // Rule ID 1185 //
     /* 14809 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 14812 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14816 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14820 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14824 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14828 */   // MIs[1] Operand 1
     /* 14828 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 14833 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14838 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14842 */   // MIs[0] offset
     /* 14842 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14845 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14847 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14847 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZ_MM),
     /* 14850 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14854 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14856 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14859 */   GIR_RootConstrainSelectedInstOperands,
     /* 14860 */   // GIR_Coverage, 1185,
     /* 14860 */   GIR_EraseRootFromParent_Done,
     /* 14861 */ // Label 545: @14861
     /* 14861 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(14918), // Rule ID 1186 //
     /* 14866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 14869 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14873 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14877 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14881 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14885 */   // MIs[1] Operand 1
     /* 14885 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 14890 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14895 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14899 */   // MIs[0] offset
     /* 14899 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14902 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14904 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14904 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
     /* 14907 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14911 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14913 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14916 */   GIR_RootConstrainSelectedInstOperands,
     /* 14917 */   // GIR_Coverage, 1186,
     /* 14917 */   GIR_EraseRootFromParent_Done,
     /* 14918 */ // Label 546: @14918
     /* 14918 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(14975), // Rule ID 1187 //
     /* 14923 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 14926 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14930 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14934 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14938 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14942 */   // MIs[1] Operand 1
     /* 14942 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 14947 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 14952 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 14956 */   // MIs[0] offset
     /* 14956 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 14959 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 14961 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZ_MM GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 14961 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZ_MM),
     /* 14964 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 14968 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 14970 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 14973 */   GIR_RootConstrainSelectedInstOperands,
     /* 14974 */   // GIR_Coverage, 1187,
     /* 14974 */   GIR_EraseRootFromParent_Done,
     /* 14975 */ // Label 547: @14975
     /* 14975 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(15038), // Rule ID 1477 //
     /* 14980 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 14983 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 14987 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 14991 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 14995 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 14999 */   // MIs[1] Operand 1
     /* 14999 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 15004 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15009 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15013 */   // MIs[0] dst
     /* 15013 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15016 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15018 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 15018 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
     /* 15021 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15025 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15031 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15033 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15036 */   GIR_RootConstrainSelectedInstOperands,
     /* 15037 */   // GIR_Coverage, 1477,
     /* 15037 */   GIR_EraseRootFromParent_Done,
     /* 15038 */ // Label 548: @15038
     /* 15038 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(15101), // Rule ID 1478 //
     /* 15043 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 15046 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15050 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15054 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15058 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15062 */   // MIs[1] Operand 1
     /* 15062 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 15067 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15072 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15076 */   // MIs[0] dst
     /* 15076 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15079 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15081 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 15081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 15084 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15088 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15094 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15096 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15099 */   GIR_RootConstrainSelectedInstOperands,
     /* 15100 */   // GIR_Coverage, 1478,
     /* 15100 */   GIR_EraseRootFromParent_Done,
     /* 15101 */ // Label 549: @15101
     /* 15101 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(15164), // Rule ID 1651 //
     /* 15106 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 15109 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15113 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15117 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 15121 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 15125 */   // MIs[1] Operand 1
     /* 15125 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 15130 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 15135 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15139 */   // MIs[0] dst
     /* 15139 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15142 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15144 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
     /* 15144 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
     /* 15147 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15151 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15157 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15159 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15162 */   GIR_RootConstrainSelectedInstOperands,
     /* 15163 */   // GIR_Coverage, 1651,
     /* 15163 */   GIR_EraseRootFromParent_Done,
     /* 15164 */ // Label 550: @15164
     /* 15164 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(15227), // Rule ID 1652 //
     /* 15169 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 15172 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15176 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15180 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 15184 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 15188 */   // MIs[1] Operand 1
     /* 15188 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 15193 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 15198 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15202 */   // MIs[0] dst
     /* 15202 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15205 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15207 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ64 GPR64:{ *:[i64] }:$lhs, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
     /* 15207 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
     /* 15210 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15214 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15220 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15222 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15225 */   GIR_RootConstrainSelectedInstOperands,
     /* 15226 */   // GIR_Coverage, 1652,
     /* 15226 */   GIR_EraseRootFromParent_Done,
     /* 15227 */ // Label 551: @15227
     /* 15227 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(15281), // Rule ID 1983 //
     /* 15232 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 15235 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15239 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15243 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15247 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15251 */   // MIs[1] Operand 1
     /* 15251 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 15256 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 15261 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15265 */   // MIs[0] targ16
     /* 15265 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15268 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15270 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$targ16)  =>  (BeqzRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
     /* 15270 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BeqzRxImm16),
     /* 15273 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 15277 */   GIR_RootToRootCopy, /*OpIdx*/1, // targ16
     /* 15279 */   GIR_RootConstrainSelectedInstOperands,
     /* 15280 */   // GIR_Coverage, 1983,
     /* 15280 */   GIR_EraseRootFromParent_Done,
     /* 15281 */ // Label 552: @15281
     /* 15281 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(15335), // Rule ID 1992 //
     /* 15286 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 15289 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15293 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15297 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15301 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15305 */   // MIs[1] Operand 1
     /* 15305 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 15310 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 15315 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15319 */   // MIs[0] targ16
     /* 15319 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15322 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15324 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$targ16)  =>  (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
     /* 15324 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
     /* 15327 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 15331 */   GIR_RootToRootCopy, /*OpIdx*/1, // targ16
     /* 15333 */   GIR_RootConstrainSelectedInstOperands,
     /* 15334 */   // GIR_Coverage, 1992,
     /* 15334 */   GIR_EraseRootFromParent_Done,
     /* 15335 */ // Label 553: @15335
     /* 15335 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(15398), // Rule ID 2322 //
     /* 15340 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 15343 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15347 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15351 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15355 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15359 */   // MIs[1] Operand 1
     /* 15359 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 15364 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15369 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15373 */   // MIs[0] dst
     /* 15373 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15376 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15378 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNE_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 15378 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
     /* 15381 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15385 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15391 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15393 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15396 */   GIR_RootConstrainSelectedInstOperands,
     /* 15397 */   // GIR_Coverage, 2322,
     /* 15397 */   GIR_EraseRootFromParent_Done,
     /* 15398 */ // Label 554: @15398
     /* 15398 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(15461), // Rule ID 2323 //
     /* 15403 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 15406 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15410 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15414 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15418 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15422 */   // MIs[1] Operand 1
     /* 15422 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 15427 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15432 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15436 */   // MIs[0] dst
     /* 15436 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15439 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15441 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM GPR32:{ *:[i32] }:$lhs, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 15441 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 15444 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15448 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 15454 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15456 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15459 */   GIR_RootConstrainSelectedInstOperands,
     /* 15460 */   // GIR_Coverage, 2323,
     /* 15460 */   GIR_EraseRootFromParent_Done,
     /* 15461 */ // Label 555: @15461
     /* 15461 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(15518), // Rule ID 2473 //
     /* 15466 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 15469 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15473 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15477 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15481 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15485 */   // MIs[1] Operand 1
     /* 15485 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 15490 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15495 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15499 */   // MIs[0] dst
     /* 15499 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15502 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15504 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BNEZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15504 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
     /* 15507 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15511 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15513 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15516 */   GIR_RootConstrainSelectedInstOperands,
     /* 15517 */   // GIR_Coverage, 2473,
     /* 15517 */   GIR_EraseRootFromParent_Done,
     /* 15518 */ // Label 556: @15518
     /* 15518 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(15575), // Rule ID 2474 //
     /* 15523 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 15526 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15530 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15534 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15538 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15542 */   // MIs[1] Operand 1
     /* 15542 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 15547 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 15552 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15556 */   // MIs[0] dst
     /* 15556 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15559 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15561 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 GPR32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15561 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
     /* 15564 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15568 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15570 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15573 */   GIR_RootConstrainSelectedInstOperands,
     /* 15574 */   // GIR_Coverage, 2474,
     /* 15574 */   GIR_EraseRootFromParent_Done,
     /* 15575 */ // Label 557: @15575
     /* 15575 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(15627), // Rule ID 1488 //
     /* 15580 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 15583 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15587 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15591 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15595 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15599 */   // MIs[1] Operand 1
     /* 15599 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 15604 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 15608 */   // MIs[0] dst
     /* 15608 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15611 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15613 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15613 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ),
     /* 15616 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15620 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15622 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15625 */   GIR_RootConstrainSelectedInstOperands,
     /* 15626 */   // GIR_Coverage, 1488,
     /* 15626 */   GIR_EraseRootFromParent_Done,
     /* 15627 */ // Label 558: @15627
     /* 15627 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(15679), // Rule ID 1489 //
     /* 15632 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 15635 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15639 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15643 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15647 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15651 */   // MIs[1] Operand 1
     /* 15651 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 15656 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 15660 */   // MIs[0] dst
     /* 15660 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15663 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15665 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ),
     /* 15668 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15672 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15674 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15677 */   GIR_RootConstrainSelectedInstOperands,
     /* 15678 */   // GIR_Coverage, 1489,
     /* 15678 */   GIR_EraseRootFromParent_Done,
     /* 15679 */ // Label 559: @15679
     /* 15679 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(15731), // Rule ID 1662 //
     /* 15684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 15687 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15691 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15695 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 15699 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 15703 */   // MIs[1] Operand 1
     /* 15703 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 15708 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 15712 */   // MIs[0] dst
     /* 15712 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15715 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15717 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15717 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ64),
     /* 15720 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15724 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15726 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15729 */   GIR_RootConstrainSelectedInstOperands,
     /* 15730 */   // GIR_Coverage, 1662,
     /* 15730 */   GIR_EraseRootFromParent_Done,
     /* 15731 */ // Label 560: @15731
     /* 15731 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(15783), // Rule ID 1663 //
     /* 15736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 15739 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15743 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15747 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 15751 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 15755 */   // MIs[1] Operand 1
     /* 15755 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 15760 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 15764 */   // MIs[0] dst
     /* 15764 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15767 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15769 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$lhs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ64 i64:{ *:[i64] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 15769 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ64),
     /* 15772 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 15776 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 15778 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15781 */   GIR_RootConstrainSelectedInstOperands,
     /* 15782 */   // GIR_Coverage, 1663,
     /* 15782 */   GIR_EraseRootFromParent_Done,
     /* 15783 */ // Label 561: @15783
     /* 15783 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(15835), // Rule ID 1893 //
     /* 15788 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 15791 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15795 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15799 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15803 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15807 */   // MIs[1] Operand 1
     /* 15807 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 15812 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15816 */   // MIs[0] offset
     /* 15816 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15819 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15821 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 15821 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
     /* 15824 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 15828 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 15830 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15833 */   GIR_RootConstrainSelectedInstOperands,
     /* 15834 */   // GIR_Coverage, 1893,
     /* 15834 */   GIR_EraseRootFromParent_Done,
     /* 15835 */ // Label 562: @15835
     /* 15835 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(15887), // Rule ID 1894 //
     /* 15840 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 15843 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15847 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15851 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15855 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15859 */   // MIs[1] Operand 1
     /* 15859 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 15864 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 15868 */   // MIs[0] offset
     /* 15868 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15871 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15873 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 15873 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
     /* 15876 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 15880 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 15882 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15885 */   GIR_RootConstrainSelectedInstOperands,
     /* 15886 */   // GIR_Coverage, 1894,
     /* 15886 */   GIR_EraseRootFromParent_Done,
     /* 15887 */ // Label 563: @15887
     /* 15887 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(15939), // Rule ID 1895 //
     /* 15892 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 15895 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15899 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15903 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15907 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15911 */   // MIs[1] Operand 1
     /* 15911 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 15916 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 15920 */   // MIs[0] offset
     /* 15920 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15923 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15925 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 15925 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
     /* 15928 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 15932 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 15934 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15937 */   GIR_RootConstrainSelectedInstOperands,
     /* 15938 */   // GIR_Coverage, 1895,
     /* 15938 */   GIR_EraseRootFromParent_Done,
     /* 15939 */ // Label 564: @15939
     /* 15939 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(15991), // Rule ID 1896 //
     /* 15944 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 15947 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 15951 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 15955 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 15959 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 15963 */   // MIs[1] Operand 1
     /* 15963 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 15968 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 15972 */   // MIs[0] offset
     /* 15972 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 15975 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 15977 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 1:{ *:[i32] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 15977 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
     /* 15980 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 15984 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 15986 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 15989 */   GIR_RootConstrainSelectedInstOperands,
     /* 15990 */   // GIR_Coverage, 1896,
     /* 15990 */   GIR_EraseRootFromParent_Done,
     /* 15991 */ // Label 565: @15991
     /* 15991 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(16043), // Rule ID 1897 //
     /* 15996 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 15999 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16003 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16007 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16011 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16015 */   // MIs[1] Operand 1
     /* 16015 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 16020 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16024 */   // MIs[0] offset
     /* 16024 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16027 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16029 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16029 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC),
     /* 16032 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16036 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16038 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16041 */   GIR_RootConstrainSelectedInstOperands,
     /* 16042 */   // GIR_Coverage, 1897,
     /* 16042 */   GIR_EraseRootFromParent_Done,
     /* 16043 */ // Label 566: @16043
     /* 16043 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(16095), // Rule ID 1898 //
     /* 16048 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16051 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16055 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16059 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16063 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16067 */   // MIs[1] Operand 1
     /* 16067 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 16072 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 16076 */   // MIs[0] offset
     /* 16076 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16079 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16081 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16081 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC),
     /* 16084 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16088 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16090 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16093 */   GIR_RootConstrainSelectedInstOperands,
     /* 16094 */   // GIR_Coverage, 1898,
     /* 16094 */   GIR_EraseRootFromParent_Done,
     /* 16095 */ // Label 567: @16095
     /* 16095 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(16147), // Rule ID 1899 //
     /* 16100 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16103 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16107 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16111 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16115 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16119 */   // MIs[1] Operand 1
     /* 16119 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 16124 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16128 */   // MIs[0] offset
     /* 16128 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16131 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16133 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, 0:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16133 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC),
     /* 16136 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16140 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16142 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16145 */   GIR_RootConstrainSelectedInstOperands,
     /* 16146 */   // GIR_Coverage, 1899,
     /* 16146 */   GIR_EraseRootFromParent_Done,
     /* 16147 */ // Label 568: @16147
     /* 16147 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(16199), // Rule ID 1900 //
     /* 16152 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16155 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16159 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16163 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16167 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16171 */   // MIs[1] Operand 1
     /* 16171 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 16176 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 16180 */   // MIs[0] offset
     /* 16180 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16183 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16185 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$rs, -1:{ *:[i32] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZC GPR32Opnd:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16185 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC),
     /* 16188 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16192 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16194 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16197 */   GIR_RootConstrainSelectedInstOperands,
     /* 16198 */   // GIR_Coverage, 1900,
     /* 16198 */   GIR_EraseRootFromParent_Done,
     /* 16199 */ // Label 569: @16199
     /* 16199 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(16251), // Rule ID 1936 //
     /* 16204 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16207 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16211 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16215 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16219 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16223 */   // MIs[1] Operand 1
     /* 16223 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 16228 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16232 */   // MIs[0] offset
     /* 16232 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16235 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16237 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16237 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
     /* 16240 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16244 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16246 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16249 */   GIR_RootConstrainSelectedInstOperands,
     /* 16250 */   // GIR_Coverage, 1936,
     /* 16250 */   GIR_EraseRootFromParent_Done,
     /* 16251 */ // Label 570: @16251
     /* 16251 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(16303), // Rule ID 1937 //
     /* 16256 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16259 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16263 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16267 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16271 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16275 */   // MIs[1] Operand 1
     /* 16275 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 16280 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 16284 */   // MIs[0] offset
     /* 16284 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16287 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16289 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16289 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
     /* 16292 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16296 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16298 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16301 */   GIR_RootConstrainSelectedInstOperands,
     /* 16302 */   // GIR_Coverage, 1937,
     /* 16302 */   GIR_EraseRootFromParent_Done,
     /* 16303 */ // Label 571: @16303
     /* 16303 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(16355), // Rule ID 1938 //
     /* 16308 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16311 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16315 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16319 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16323 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16327 */   // MIs[1] Operand 1
     /* 16327 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 16332 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16336 */   // MIs[0] offset
     /* 16336 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16339 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16341 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16341 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
     /* 16344 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16348 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16350 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16353 */   GIR_RootConstrainSelectedInstOperands,
     /* 16354 */   // GIR_Coverage, 1938,
     /* 16354 */   GIR_EraseRootFromParent_Done,
     /* 16355 */ // Label 572: @16355
     /* 16355 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(16407), // Rule ID 1939 //
     /* 16360 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16363 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16367 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16371 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16375 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16379 */   // MIs[1] Operand 1
     /* 16379 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 16384 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 16388 */   // MIs[0] offset
     /* 16388 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16391 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16393 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 1:{ *:[i64] }, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16393 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
     /* 16396 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16400 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16402 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16405 */   GIR_RootConstrainSelectedInstOperands,
     /* 16406 */   // GIR_Coverage, 1939,
     /* 16406 */   GIR_EraseRootFromParent_Done,
     /* 16407 */ // Label 573: @16407
     /* 16407 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(16459), // Rule ID 1940 //
     /* 16412 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16415 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16419 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16423 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16427 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16431 */   // MIs[1] Operand 1
     /* 16431 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 16436 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16440 */   // MIs[0] offset
     /* 16440 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16443 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16445 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16445 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGTZC64),
     /* 16448 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16452 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16454 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16457 */   GIR_RootConstrainSelectedInstOperands,
     /* 16458 */   // GIR_Coverage, 1940,
     /* 16458 */   GIR_EraseRootFromParent_Done,
     /* 16459 */ // Label 574: @16459
     /* 16459 */ GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(16511), // Rule ID 1941 //
     /* 16464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16467 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16471 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16475 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16479 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16483 */   // MIs[1] Operand 1
     /* 16483 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 16488 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 16492 */   // MIs[0] offset
     /* 16492 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16495 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16497 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZC64),
     /* 16500 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16504 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16506 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16509 */   GIR_RootConstrainSelectedInstOperands,
     /* 16510 */   // GIR_Coverage, 1941,
     /* 16510 */   GIR_EraseRootFromParent_Done,
     /* 16511 */ // Label 575: @16511
     /* 16511 */ GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(16563), // Rule ID 1942 //
     /* 16516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16519 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16523 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16527 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16531 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16535 */   // MIs[1] Operand 1
     /* 16535 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 16540 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 16544 */   // MIs[0] offset
     /* 16544 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16547 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16549 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, 0:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLEZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16549 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZC64),
     /* 16552 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16556 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16558 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16561 */   GIR_RootConstrainSelectedInstOperands,
     /* 16562 */   // GIR_Coverage, 1942,
     /* 16562 */   GIR_EraseRootFromParent_Done,
     /* 16563 */ // Label 576: @16563
     /* 16563 */ GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(16615), // Rule ID 1943 //
     /* 16568 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 16571 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16575 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16579 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16583 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16587 */   // MIs[1] Operand 1
     /* 16587 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 16592 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 16596 */   // MIs[0] offset
     /* 16596 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16599 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16601 */   // (brcond (setcc:{ *:[i32] } i64:{ *:[i64] }:$rs, -1:{ *:[i64] }, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTZC64 GPR64Opnd:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 16601 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTZC64),
     /* 16604 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16608 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16610 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16613 */   GIR_RootConstrainSelectedInstOperands,
     /* 16614 */   // GIR_Coverage, 1943,
     /* 16614 */   GIR_EraseRootFromParent_Done,
     /* 16615 */ // Label 577: @16615
     /* 16615 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(16667), // Rule ID 2333 //
     /* 16620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 16623 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16627 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16631 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16635 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16639 */   // MIs[1] Operand 1
     /* 16639 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 16644 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 1,
     /* 16648 */   // MIs[0] dst
     /* 16648 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16651 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16653 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, 1:{ *:[i32] }, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BLEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 16653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLEZ_MM),
     /* 16656 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 16660 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 16662 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16665 */   GIR_RootConstrainSelectedInstOperands,
     /* 16666 */   // GIR_Coverage, 2333,
     /* 16666 */   GIR_EraseRootFromParent_Done,
     /* 16667 */ // Label 578: @16667
     /* 16667 */ GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(16719), // Rule ID 2334 //
     /* 16672 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 16675 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16679 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16683 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16687 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16691 */   // MIs[1] Operand 1
     /* 16691 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 16696 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 255,
     /* 16700 */   // MIs[0] dst
     /* 16700 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16703 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16705 */   // (brcond (setcc:{ *:[i32] } i32:{ *:[i32] }:$lhs, -1:{ *:[i32] }, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BGEZ_MM i32:{ *:[i32] }:$lhs, (bb:{ *:[Other] }):$dst)
     /* 16705 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEZ_MM),
     /* 16708 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 16712 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 16714 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16717 */   GIR_RootConstrainSelectedInstOperands,
     /* 16718 */   // GIR_Coverage, 2334,
     /* 16718 */   GIR_EraseRootFromParent_Done,
     /* 16719 */ // Label 579: @16719
     /* 16719 */ GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(16781), // Rule ID 92 //
     /* 16724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 16727 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16731 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16735 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16739 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16743 */   // MIs[1] Operand 1
     /* 16743 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 16748 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 16753 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 16758 */   // MIs[0] offset
     /* 16758 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16761 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16763 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 16763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 16766 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16770 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 16774 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16776 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16779 */   GIR_RootConstrainSelectedInstOperands,
     /* 16780 */   // GIR_Coverage, 92,
     /* 16780 */   GIR_EraseRootFromParent_Done,
     /* 16781 */ // Label 580: @16781
     /* 16781 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(16843), // Rule ID 93 //
     /* 16786 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 16789 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16793 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16797 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16801 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16805 */   // MIs[1] Operand 1
     /* 16805 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 16810 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 16815 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 16820 */   // MIs[0] offset
     /* 16820 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16823 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16825 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 16825 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
     /* 16828 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16832 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 16836 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16838 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16841 */   GIR_RootConstrainSelectedInstOperands,
     /* 16842 */   // GIR_Coverage, 93,
     /* 16842 */   GIR_EraseRootFromParent_Done,
     /* 16843 */ // Label 581: @16843
     /* 16843 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(16905), // Rule ID 318 //
     /* 16848 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 16851 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16855 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16859 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16863 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16867 */   // MIs[1] Operand 1
     /* 16867 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 16872 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 16877 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 16882 */   // MIs[0] offset
     /* 16882 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16885 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16887 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 16887 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ64),
     /* 16890 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16894 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 16898 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16900 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16903 */   GIR_RootConstrainSelectedInstOperands,
     /* 16904 */   // GIR_Coverage, 318,
     /* 16904 */   GIR_EraseRootFromParent_Done,
     /* 16905 */ // Label 582: @16905
     /* 16905 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(16967), // Rule ID 319 //
     /* 16910 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 16913 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16917 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16921 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 16925 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 16929 */   // MIs[1] Operand 1
     /* 16929 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 16934 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 16939 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 16944 */   // MIs[0] offset
     /* 16944 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 16947 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 16949 */   // (brcond (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE64 GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 16949 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
     /* 16952 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 16956 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 16960 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 16962 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 16965 */   GIR_RootConstrainSelectedInstOperands,
     /* 16966 */   // GIR_Coverage, 319,
     /* 16966 */   GIR_EraseRootFromParent_Done,
     /* 16967 */ // Label 583: @16967
     /* 16967 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(17029), // Rule ID 1182 //
     /* 16972 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 16975 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 16979 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 16983 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 16987 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 16991 */   // MIs[1] Operand 1
     /* 16991 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 16996 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17001 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17006 */   // MIs[0] offset
     /* 17006 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17009 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17011 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BEQ_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 17011 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 17014 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 17018 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 17022 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 17024 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17027 */   GIR_RootConstrainSelectedInstOperands,
     /* 17028 */   // GIR_Coverage, 1182,
     /* 17028 */   GIR_EraseRootFromParent_Done,
     /* 17029 */ // Label 584: @17029
     /* 17029 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(17091), // Rule ID 1183 //
     /* 17034 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 17037 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17041 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17045 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17049 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17053 */   // MIs[1] Operand 1
     /* 17053 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 17058 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17063 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17068 */   // MIs[0] offset
     /* 17068 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17071 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17073 */   // (brcond (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BNE_MM GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 17073 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
     /* 17076 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 17080 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 17084 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 17086 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17089 */   GIR_RootConstrainSelectedInstOperands,
     /* 17090 */   // GIR_Coverage, 1183,
     /* 17090 */   GIR_EraseRootFromParent_Done,
     /* 17091 */ // Label 585: @17091
     /* 17091 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(17176), // Rule ID 1479 //
     /* 17096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 17099 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17103 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17107 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17111 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17115 */   // MIs[1] Operand 1
     /* 17115 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 17120 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17125 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17130 */   // MIs[0] dst
     /* 17130 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17133 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17135 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17135 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17138 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 17142 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17147 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17151 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17155 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17157 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17160 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17163 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17169 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17171 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17174 */   GIR_RootConstrainSelectedInstOperands,
     /* 17175 */   // GIR_Coverage, 1479,
     /* 17175 */   GIR_EraseRootFromParent_Done,
     /* 17176 */ // Label 586: @17176
     /* 17176 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(17261), // Rule ID 1480 //
     /* 17181 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 17184 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17188 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17192 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17196 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17200 */   // MIs[1] Operand 1
     /* 17200 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 17205 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17210 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17215 */   // MIs[0] dst
     /* 17215 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17218 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17220 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17220 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17223 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 17227 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17232 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17236 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17240 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17242 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17245 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17248 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17254 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17256 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17259 */   GIR_RootConstrainSelectedInstOperands,
     /* 17260 */   // GIR_Coverage, 1480,
     /* 17260 */   GIR_EraseRootFromParent_Done,
     /* 17261 */ // Label 587: @17261
     /* 17261 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(17346), // Rule ID 1485 //
     /* 17266 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 17269 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17273 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17277 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17281 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17285 */   // MIs[1] Operand 1
     /* 17285 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 17290 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17295 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17300 */   // MIs[0] dst
     /* 17300 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17303 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17305 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17305 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17308 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 17312 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17317 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17321 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17325 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17327 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17330 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17333 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17339 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17341 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17344 */   GIR_RootConstrainSelectedInstOperands,
     /* 17345 */   // GIR_Coverage, 1485,
     /* 17345 */   GIR_EraseRootFromParent_Done,
     /* 17346 */ // Label 588: @17346
     /* 17346 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(17431), // Rule ID 1486 //
     /* 17351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 17354 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17358 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17362 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17366 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17370 */   // MIs[1] Operand 1
     /* 17370 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 17375 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17380 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17385 */   // MIs[0] dst
     /* 17385 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17388 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17390 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17390 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17393 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 17397 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17402 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17406 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17410 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17412 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17415 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17418 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17424 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17426 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17429 */   GIR_RootConstrainSelectedInstOperands,
     /* 17430 */   // GIR_Coverage, 1486,
     /* 17430 */   GIR_EraseRootFromParent_Done,
     /* 17431 */ // Label 589: @17431
     /* 17431 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(17516), // Rule ID 1653 //
     /* 17436 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 17439 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17443 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17447 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 17451 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 17455 */   // MIs[1] Operand 1
     /* 17455 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 17460 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17465 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17470 */   // MIs[0] dst
     /* 17470 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17473 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17475 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17475 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17478 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 17482 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17487 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17491 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17495 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17500 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17503 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17509 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17511 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17514 */   GIR_RootConstrainSelectedInstOperands,
     /* 17515 */   // GIR_Coverage, 1653,
     /* 17515 */   GIR_EraseRootFromParent_Done,
     /* 17516 */ // Label 590: @17516
     /* 17516 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(17601), // Rule ID 1654 //
     /* 17521 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 17524 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17528 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17532 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 17536 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 17540 */   // MIs[1] Operand 1
     /* 17540 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 17545 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17550 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17555 */   // MIs[0] dst
     /* 17555 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17558 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17560 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17560 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17563 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 17567 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17572 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17576 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17580 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17582 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17585 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17588 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17594 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17596 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17599 */   GIR_RootConstrainSelectedInstOperands,
     /* 17600 */   // GIR_Coverage, 1654,
     /* 17600 */   GIR_EraseRootFromParent_Done,
     /* 17601 */ // Label 591: @17601
     /* 17601 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(17686), // Rule ID 1659 //
     /* 17606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 17609 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17613 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17617 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 17621 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 17625 */   // MIs[1] Operand 1
     /* 17625 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 17630 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17635 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17640 */   // MIs[0] dst
     /* 17640 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17643 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17645 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17645 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17648 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 17652 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17657 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17661 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17665 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17667 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17670 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17673 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17679 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17681 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17684 */   GIR_RootConstrainSelectedInstOperands,
     /* 17685 */   // GIR_Coverage, 1659,
     /* 17685 */   GIR_EraseRootFromParent_Done,
     /* 17686 */ // Label 592: @17686
     /* 17686 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(17771), // Rule ID 1660 //
     /* 17691 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 17694 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17698 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17702 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 17706 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 17710 */   // MIs[1] Operand 1
     /* 17710 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 17715 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17720 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 17725 */   // MIs[0] dst
     /* 17725 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17728 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17730 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 17730 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 17733 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 17737 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 17742 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 17746 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 17750 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 17752 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ),
     /* 17755 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 17758 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 17764 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 17766 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17769 */   GIR_RootConstrainSelectedInstOperands,
     /* 17770 */   // GIR_Coverage, 1660,
     /* 17770 */   GIR_EraseRootFromParent_Done,
     /* 17771 */ // Label 593: @17771
     /* 17771 */ GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(17833), // Rule ID 1901 //
     /* 17776 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 17779 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17783 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17787 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17791 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17795 */   // MIs[1] Operand 1
     /* 17795 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 17800 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17805 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17810 */   // MIs[0] offset
     /* 17810 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17813 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17815 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 17815 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
     /* 17818 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 17822 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 17826 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 17828 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17831 */   GIR_RootConstrainSelectedInstOperands,
     /* 17832 */   // GIR_Coverage, 1901,
     /* 17832 */   GIR_EraseRootFromParent_Done,
     /* 17833 */ // Label 594: @17833
     /* 17833 */ GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(17895), // Rule ID 1902 //
     /* 17838 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 17841 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17845 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17849 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17853 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17857 */   // MIs[1] Operand 1
     /* 17857 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 17862 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17867 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17872 */   // MIs[0] offset
     /* 17872 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17875 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17877 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 17877 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
     /* 17880 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 17884 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 17888 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 17890 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17893 */   GIR_RootConstrainSelectedInstOperands,
     /* 17894 */   // GIR_Coverage, 1902,
     /* 17894 */   GIR_EraseRootFromParent_Done,
     /* 17895 */ // Label 595: @17895
     /* 17895 */ GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(17957), // Rule ID 1903 //
     /* 17900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 17903 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17907 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17911 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17915 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17919 */   // MIs[1] Operand 1
     /* 17919 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 17924 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17929 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17934 */   // MIs[0] offset
     /* 17934 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17937 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 17939 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 17939 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC),
     /* 17942 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 17946 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 17950 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 17952 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 17955 */   GIR_RootConstrainSelectedInstOperands,
     /* 17956 */   // GIR_Coverage, 1903,
     /* 17956 */   GIR_EraseRootFromParent_Done,
     /* 17957 */ // Label 596: @17957
     /* 17957 */ GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(18019), // Rule ID 1904 //
     /* 17962 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 17965 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 17969 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 17973 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 17977 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 17981 */   // MIs[1] Operand 1
     /* 17981 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 17986 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17991 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 17996 */   // MIs[0] offset
     /* 17996 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 17999 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18001 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18001 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC),
     /* 18004 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18008 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18012 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18014 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18017 */   GIR_RootConstrainSelectedInstOperands,
     /* 18018 */   // GIR_Coverage, 1904,
     /* 18018 */   GIR_EraseRootFromParent_Done,
     /* 18019 */ // Label 597: @18019
     /* 18019 */ GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(18081), // Rule ID 1905 //
     /* 18024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18027 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18031 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18035 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18039 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18043 */   // MIs[1] Operand 1
     /* 18043 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 18048 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18053 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18058 */   // MIs[0] offset
     /* 18058 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18061 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18063 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18063 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
     /* 18066 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18070 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18074 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18076 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18079 */   GIR_RootConstrainSelectedInstOperands,
     /* 18080 */   // GIR_Coverage, 1905,
     /* 18080 */   GIR_EraseRootFromParent_Done,
     /* 18081 */ // Label 598: @18081
     /* 18081 */ GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(18143), // Rule ID 1906 //
     /* 18086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18089 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18093 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18097 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18101 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18105 */   // MIs[1] Operand 1
     /* 18105 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 18110 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18115 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18120 */   // MIs[0] offset
     /* 18120 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18123 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18125 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEUC GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18125 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
     /* 18128 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18132 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18136 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18138 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18141 */   GIR_RootConstrainSelectedInstOperands,
     /* 18142 */   // GIR_Coverage, 1906,
     /* 18142 */   GIR_EraseRootFromParent_Done,
     /* 18143 */ // Label 599: @18143
     /* 18143 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(18205), // Rule ID 1907 //
     /* 18148 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18151 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18155 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18159 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18163 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18167 */   // MIs[1] Operand 1
     /* 18167 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 18172 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18177 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18182 */   // MIs[0] offset
     /* 18182 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18185 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18187 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18187 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC),
     /* 18190 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18194 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18198 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18200 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18203 */   GIR_RootConstrainSelectedInstOperands,
     /* 18204 */   // GIR_Coverage, 1907,
     /* 18204 */   GIR_EraseRootFromParent_Done,
     /* 18205 */ // Label 600: @18205
     /* 18205 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(18267), // Rule ID 1908 //
     /* 18210 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18213 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18217 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18221 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18225 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18229 */   // MIs[1] Operand 1
     /* 18229 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 18234 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18239 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 18244 */   // MIs[0] offset
     /* 18244 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18247 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18249 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$rs, GPR32:{ *:[i32] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEUC GPR32:{ *:[i32] }:$rt, GPR32:{ *:[i32] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18249 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC),
     /* 18252 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18256 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18260 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18262 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18265 */   GIR_RootConstrainSelectedInstOperands,
     /* 18266 */   // GIR_Coverage, 1908,
     /* 18266 */   GIR_EraseRootFromParent_Done,
     /* 18267 */ // Label 601: @18267
     /* 18267 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(18329), // Rule ID 1944 //
     /* 18272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18275 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18279 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18283 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18287 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18291 */   // MIs[1] Operand 1
     /* 18291 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 18296 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18301 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18306 */   // MIs[0] offset
     /* 18306 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18309 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18311 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18311 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
     /* 18314 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18318 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18322 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18324 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18327 */   GIR_RootConstrainSelectedInstOperands,
     /* 18328 */   // GIR_Coverage, 1944,
     /* 18328 */   GIR_EraseRootFromParent_Done,
     /* 18329 */ // Label 602: @18329
     /* 18329 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(18391), // Rule ID 1945 //
     /* 18334 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18337 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18341 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18345 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18349 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18353 */   // MIs[1] Operand 1
     /* 18353 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 18358 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18363 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18368 */   // MIs[0] offset
     /* 18368 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18371 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18373 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18373 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
     /* 18376 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18380 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18384 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18386 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18389 */   GIR_RootConstrainSelectedInstOperands,
     /* 18390 */   // GIR_Coverage, 1945,
     /* 18390 */   GIR_EraseRootFromParent_Done,
     /* 18391 */ // Label 603: @18391
     /* 18391 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(18453), // Rule ID 1946 //
     /* 18396 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18399 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18403 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18407 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18411 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18415 */   // MIs[1] Operand 1
     /* 18415 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 18420 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18425 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18430 */   // MIs[0] offset
     /* 18430 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18433 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18435 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18435 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTC64),
     /* 18438 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18442 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18446 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18448 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18451 */   GIR_RootConstrainSelectedInstOperands,
     /* 18452 */   // GIR_Coverage, 1946,
     /* 18452 */   GIR_EraseRootFromParent_Done,
     /* 18453 */ // Label 604: @18453
     /* 18453 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(18515), // Rule ID 1947 //
     /* 18458 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18461 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18465 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18469 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18473 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18477 */   // MIs[1] Operand 1
     /* 18477 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 18482 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18487 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18492 */   // MIs[0] offset
     /* 18492 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18495 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18497 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18497 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEC64),
     /* 18500 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18504 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18508 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18510 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18513 */   GIR_RootConstrainSelectedInstOperands,
     /* 18514 */   // GIR_Coverage, 1947,
     /* 18514 */   GIR_EraseRootFromParent_Done,
     /* 18515 */ // Label 605: @18515
     /* 18515 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(18577), // Rule ID 1948 //
     /* 18520 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18523 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18527 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18531 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18535 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18539 */   // MIs[1] Operand 1
     /* 18539 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 18544 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18549 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18554 */   // MIs[0] offset
     /* 18554 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18557 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18559 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18559 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
     /* 18562 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18566 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18570 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18572 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18575 */   GIR_RootConstrainSelectedInstOperands,
     /* 18576 */   // GIR_Coverage, 1948,
     /* 18576 */   GIR_EraseRootFromParent_Done,
     /* 18577 */ // Label 606: @18577
     /* 18577 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(18639), // Rule ID 1949 //
     /* 18582 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18585 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18589 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18593 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18597 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18601 */   // MIs[1] Operand 1
     /* 18601 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 18606 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18611 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18616 */   // MIs[0] offset
     /* 18616 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18619 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18621 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEUC64 GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, (bb:{ *:[Other] }):$offset)
     /* 18621 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
     /* 18624 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18628 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18632 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18634 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18637 */   GIR_RootConstrainSelectedInstOperands,
     /* 18638 */   // GIR_Coverage, 1949,
     /* 18638 */   GIR_EraseRootFromParent_Done,
     /* 18639 */ // Label 607: @18639
     /* 18639 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(18701), // Rule ID 1950 //
     /* 18644 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18647 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18651 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18655 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18659 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18663 */   // MIs[1] Operand 1
     /* 18663 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 18668 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18673 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18678 */   // MIs[0] offset
     /* 18678 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18681 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18683 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETUGT:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BLTUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18683 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BLTUC64),
     /* 18686 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18690 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18694 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18696 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18699 */   GIR_RootConstrainSelectedInstOperands,
     /* 18700 */   // GIR_Coverage, 1950,
     /* 18700 */   GIR_EraseRootFromParent_Done,
     /* 18701 */ // Label 608: @18701
     /* 18701 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(18763), // Rule ID 1951 //
     /* 18706 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips_UseCompactBranches),
     /* 18709 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18713 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18717 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 18721 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 18725 */   // MIs[1] Operand 1
     /* 18725 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 18730 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18735 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 18740 */   // MIs[0] offset
     /* 18740 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18743 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18745 */   // (brcond (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$rs, GPR64:{ *:[i64] }:$rt, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$offset)  =>  (BGEUC64 GPR64:{ *:[i64] }:$rt, GPR64:{ *:[i64] }:$rs, (bb:{ *:[Other] }):$offset)
     /* 18745 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BGEUC64),
     /* 18748 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 18752 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 18756 */   GIR_RootToRootCopy, /*OpIdx*/1, // offset
     /* 18758 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 18761 */   GIR_RootConstrainSelectedInstOperands,
     /* 18762 */   // GIR_Coverage, 1951,
     /* 18762 */   GIR_EraseRootFromParent_Done,
     /* 18763 */ // Label 609: @18763
     /* 18763 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(18822), // Rule ID 1981 //
     /* 18768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 18771 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18775 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18779 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18783 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18787 */   // MIs[1] Operand 1
     /* 18787 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 18792 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18797 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18802 */   // MIs[0] imm16
     /* 18802 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18805 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18807 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETEQ:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
     /* 18807 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8CmpX16),
     /* 18810 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 18814 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 18818 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 18820 */   GIR_RootConstrainSelectedInstOperands,
     /* 18821 */   // GIR_Coverage, 1981,
     /* 18821 */   GIR_EraseRootFromParent_Done,
     /* 18822 */ // Label 610: @18822
     /* 18822 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(18881), // Rule ID 1984 //
     /* 18827 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 18830 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18834 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18838 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18842 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18846 */   // MIs[1] Operand 1
     /* 18846 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 18851 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18856 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18861 */   // MIs[0] imm16
     /* 18861 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18864 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18866 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
     /* 18866 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
     /* 18869 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 18873 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 18877 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 18879 */   GIR_RootConstrainSelectedInstOperands,
     /* 18880 */   // GIR_Coverage, 1984,
     /* 18880 */   GIR_EraseRootFromParent_Done,
     /* 18881 */ // Label 611: @18881
     /* 18881 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(18940), // Rule ID 1985 //
     /* 18886 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 18889 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18893 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18897 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18901 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18905 */   // MIs[1] Operand 1
     /* 18905 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 18910 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18915 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18920 */   // MIs[0] imm16
     /* 18920 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18923 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18925 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
     /* 18925 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
     /* 18928 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 18932 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 18936 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 18938 */   GIR_RootConstrainSelectedInstOperands,
     /* 18939 */   // GIR_Coverage, 1985,
     /* 18939 */   GIR_EraseRootFromParent_Done,
     /* 18940 */ // Label 612: @18940
     /* 18940 */ GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(18999), // Rule ID 1987 //
     /* 18945 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 18948 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 18952 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 18956 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 18960 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 18964 */   // MIs[1] Operand 1
     /* 18964 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 18969 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18974 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 18979 */   // MIs[0] imm16
     /* 18979 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 18982 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 18984 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8SltX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
     /* 18984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8SltX16),
     /* 18987 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 18991 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 18995 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 18997 */   GIR_RootConstrainSelectedInstOperands,
     /* 18998 */   // GIR_Coverage, 1987,
     /* 18998 */   GIR_EraseRootFromParent_Done,
     /* 18999 */ // Label 613: @18999
     /* 18999 */ GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(19058), // Rule ID 1989 //
     /* 19004 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 19007 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19011 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19015 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19019 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19023 */   // MIs[1] Operand 1
     /* 19023 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 19028 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 19033 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 19038 */   // MIs[0] imm16
     /* 19038 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19041 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19043 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BteqzT8SltX16 CPU16Regs:{ *:[i32] }:$ry, CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$imm16)
     /* 19043 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BteqzT8SltX16),
     /* 19046 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 19050 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 19054 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 19056 */   GIR_RootConstrainSelectedInstOperands,
     /* 19057 */   // GIR_Coverage, 1989,
     /* 19057 */   GIR_EraseRootFromParent_Done,
     /* 19058 */ // Label 614: @19058
     /* 19058 */ GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(19117), // Rule ID 1990 //
     /* 19063 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 19066 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19070 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19074 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19078 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19082 */   // MIs[1] Operand 1
     /* 19082 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 19087 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 19092 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 19097 */   // MIs[0] imm16
     /* 19097 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19100 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19102 */   // (brcond (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETNE:{ *:[Other] }), (bb:{ *:[Other] }):$imm16)  =>  (BtnezT8CmpX16 CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, (bb:{ *:[Other] }):$imm16)
     /* 19102 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BtnezT8CmpX16),
     /* 19105 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rx
     /* 19109 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // ry
     /* 19113 */   GIR_RootToRootCopy, /*OpIdx*/1, // imm16
     /* 19115 */   GIR_RootConstrainSelectedInstOperands,
     /* 19116 */   // GIR_Coverage, 1990,
     /* 19116 */   GIR_EraseRootFromParent_Done,
     /* 19117 */ // Label 615: @19117
     /* 19117 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(19202), // Rule ID 2324 //
     /* 19122 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 19125 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19129 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19133 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19137 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19141 */   // MIs[1] Operand 1
     /* 19141 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 19146 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19151 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19156 */   // MIs[0] dst
     /* 19156 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19159 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19161 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19161 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19164 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 19168 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19173 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19177 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19181 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19183 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 19186 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19189 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19195 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19197 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19200 */   GIR_RootConstrainSelectedInstOperands,
     /* 19201 */   // GIR_Coverage, 2324,
     /* 19201 */   GIR_EraseRootFromParent_Done,
     /* 19202 */ // Label 616: @19202
     /* 19202 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(19287), // Rule ID 2325 //
     /* 19207 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 19210 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19214 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19218 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19222 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19226 */   // MIs[1] Operand 1
     /* 19226 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 19231 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19236 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19241 */   // MIs[0] dst
     /* 19241 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19244 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19246 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19246 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19249 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 19253 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19258 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19262 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19266 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19268 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 19271 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19274 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19280 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19282 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19285 */   GIR_RootConstrainSelectedInstOperands,
     /* 19286 */   // GIR_Coverage, 2325,
     /* 19286 */   GIR_EraseRootFromParent_Done,
     /* 19287 */ // Label 617: @19287
     /* 19287 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(19372), // Rule ID 2330 //
     /* 19292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 19295 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19299 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19303 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19307 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19311 */   // MIs[1] Operand 1
     /* 19311 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 19316 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19321 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19326 */   // MIs[0] dst
     /* 19326 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19329 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19331 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19331 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19334 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 19338 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19343 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19347 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19351 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19353 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 19356 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19359 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19365 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19367 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19370 */   GIR_RootConstrainSelectedInstOperands,
     /* 19371 */   // GIR_Coverage, 2330,
     /* 19371 */   GIR_EraseRootFromParent_Done,
     /* 19372 */ // Label 618: @19372
     /* 19372 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(19457), // Rule ID 2331 //
     /* 19377 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 19380 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19384 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19388 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19392 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19396 */   // MIs[1] Operand 1
     /* 19396 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 19401 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19406 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19411 */   // MIs[0] dst
     /* 19411 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19414 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19416 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQ_MM (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19416 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19419 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 19423 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19428 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19432 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19436 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19438 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQ_MM),
     /* 19441 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19444 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19450 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19452 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19455 */   GIR_RootConstrainSelectedInstOperands,
     /* 19456 */   // GIR_Coverage, 2331,
     /* 19456 */   GIR_EraseRootFromParent_Done,
     /* 19457 */ // Label 619: @19457
     /* 19457 */ GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(19536), // Rule ID 2475 //
     /* 19462 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 19465 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19469 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19473 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19477 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19481 */   // MIs[1] Operand 1
     /* 19481 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 19486 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19491 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19496 */   // MIs[0] dst
     /* 19496 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19499 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19501 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
     /* 19501 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19504 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 19508 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19513 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19517 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19521 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19523 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
     /* 19526 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19529 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19531 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19534 */   GIR_RootConstrainSelectedInstOperands,
     /* 19535 */   // GIR_Coverage, 2475,
     /* 19535 */   GIR_EraseRootFromParent_Done,
     /* 19536 */ // Label 620: @19536
     /* 19536 */ GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(19615), // Rule ID 2476 //
     /* 19541 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 19544 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19548 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19552 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19556 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19560 */   // MIs[1] Operand 1
     /* 19560 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 19565 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19570 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19575 */   // MIs[0] dst
     /* 19575 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19578 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19580 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), (bb:{ *:[Other] }):$dst)
     /* 19580 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19583 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 19587 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19592 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19596 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19600 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19602 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
     /* 19605 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19608 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19610 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19613 */   GIR_RootConstrainSelectedInstOperands,
     /* 19614 */   // GIR_Coverage, 2476,
     /* 19614 */   GIR_EraseRootFromParent_Done,
     /* 19615 */ // Label 621: @19615
     /* 19615 */ GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(19694), // Rule ID 2481 //
     /* 19620 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 19623 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19627 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19631 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19635 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19639 */   // MIs[1] Operand 1
     /* 19639 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 19644 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19649 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19654 */   // MIs[0] dst
     /* 19654 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19657 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19659 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
     /* 19659 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19662 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 19666 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19671 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19675 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19679 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19681 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
     /* 19684 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19687 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19689 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19692 */   GIR_RootConstrainSelectedInstOperands,
     /* 19693 */   // GIR_Coverage, 2481,
     /* 19693 */   GIR_EraseRootFromParent_Done,
     /* 19694 */ // Label 622: @19694
     /* 19694 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(19773), // Rule ID 2482 //
     /* 19699 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 19702 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
     /* 19706 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 19710 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 19714 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 19718 */   // MIs[1] Operand 1
     /* 19718 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 19723 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19728 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19733 */   // MIs[0] dst
     /* 19733 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19736 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19738 */   // (brcond (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), (bb:{ *:[Other] }):$dst)  =>  (BEQZC_MMR6 (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), (bb:{ *:[Other] }):$dst)
     /* 19738 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 19741 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 19745 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 19750 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 19754 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 19758 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 19760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BEQZC_MMR6),
     /* 19763 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 19766 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19768 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19771 */   GIR_RootConstrainSelectedInstOperands,
     /* 19772 */   // GIR_Coverage, 2482,
     /* 19772 */   GIR_EraseRootFromParent_Done,
     /* 19773 */ // Label 623: @19773
     /* 19773 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(19806), // Rule ID 1487 //
     /* 19778 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 19781 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19785 */   // MIs[0] dst
     /* 19785 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19788 */   // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19788 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE),
     /* 19791 */   GIR_RootToRootCopy, /*OpIdx*/0, // cond
     /* 19793 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19799 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19801 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19804 */   GIR_RootConstrainSelectedInstOperands,
     /* 19805 */   // GIR_Coverage, 1487,
     /* 19805 */   GIR_EraseRootFromParent_Done,
     /* 19806 */ // Label 624: @19806
     /* 19806 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(19828), // Rule ID 1993 //
     /* 19811 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 19814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 19818 */   // MIs[0] targ16
     /* 19818 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19821 */   // (brcond CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)  =>  (BnezRxImm16 CPU16Regs:{ *:[i32] }:$rx, (bb:{ *:[Other] }):$targ16)
     /* 19821 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BnezRxImm16),
     /* 19826 */   GIR_RootConstrainSelectedInstOperands,
     /* 19827 */   // GIR_Coverage, 1993,
     /* 19827 */   GIR_Done,
     /* 19828 */ // Label 625: @19828
     /* 19828 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(19861), // Rule ID 2332 //
     /* 19833 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 19836 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19840 */   // MIs[0] dst
     /* 19840 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19843 */   // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE_MM GPR32:{ *:[i32] }:$cond, ZERO:{ *:[i32] }, (bb:{ *:[Other] }):$dst)
     /* 19843 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE_MM),
     /* 19846 */   GIR_RootToRootCopy, /*OpIdx*/0, // cond
     /* 19848 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19854 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19856 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19859 */   GIR_RootConstrainSelectedInstOperands,
     /* 19860 */   // GIR_Coverage, 2332,
     /* 19860 */   GIR_EraseRootFromParent_Done,
     /* 19861 */ // Label 626: @19861
     /* 19861 */ GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(19889), // Rule ID 2483 //
     /* 19866 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 19869 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 19873 */   // MIs[0] dst
     /* 19873 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19876 */   // (brcond GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNEZC_MMR6 GPR32:{ *:[i32] }:$cond, (bb:{ *:[Other] }):$dst)
     /* 19876 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BNEZC_MMR6),
     /* 19881 */   GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
     /* 19887 */   GIR_RootConstrainSelectedInstOperands,
     /* 19888 */   // GIR_Coverage, 2483,
     /* 19888 */   GIR_Done,
     /* 19889 */ // Label 627: @19889
     /* 19889 */ GIM_Reject,
     /* 19890 */ // Label 526: @19890
     /* 19890 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(19923), // Rule ID 1661 //
     /* 19895 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 19898 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 19902 */   // MIs[0] dst
     /* 19902 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/1,
     /* 19905 */   // (brcond GPR64:{ *:[i64] }:$cond, (bb:{ *:[Other] }):$dst)  =>  (BNE64 GPR64:{ *:[i64] }:$cond, ZERO_64:{ *:[i64] }, (bb:{ *:[Other] }):$dst)
     /* 19905 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BNE64),
     /* 19908 */   GIR_RootToRootCopy, /*OpIdx*/0, // cond
     /* 19910 */   GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 19916 */   GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 19918 */   GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::AT*/0,
     /* 19921 */   GIR_RootConstrainSelectedInstOperands,
     /* 19922 */   // GIR_Coverage, 1661,
     /* 19922 */   GIR_EraseRootFromParent_Done,
     /* 19923 */ // Label 628: @19923
     /* 19923 */ GIM_Reject,
     /* 19924 */ // Label 527: @19924
     /* 19924 */ GIM_Reject,
     /* 19925 */ // Label 29: @19925
     /* 19925 */ GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(21922),
     /* 19930 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 19933 */   GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(19980), // Rule ID 503 //
     /* 19938 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 19941 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
     /* 19946 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 19949 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 19952 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 19956 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 19960 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 19964 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
     /* 19968 */     // MIs[1] Operand 1
     /* 19968 */     // No operand predicates
     /* 19968 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 19970 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8464:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
     /* 19970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB),
     /* 19973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 19975 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 19978 */     GIR_RootConstrainSelectedInstOperands,
     /* 19979 */     // GIR_Coverage, 503,
     /* 19979 */     GIR_EraseRootFromParent_Done,
     /* 19980 */   // Label 630: @19980
     /* 19980 */   GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(20027), // Rule ID 504 //
     /* 19985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 19988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
     /* 19993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 19996 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 19999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20003 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 20007 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 20011 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
     /* 20015 */     // MIs[1] Operand 1
     /* 20015 */     // No operand predicates
     /* 20015 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 20017 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8463:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
     /* 20017 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH),
     /* 20020 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20022 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 20025 */     GIR_RootConstrainSelectedInstOperands,
     /* 20026 */     // GIR_Coverage, 504,
     /* 20026 */     GIR_EraseRootFromParent_Done,
     /* 20027 */   // Label 631: @20027
     /* 20027 */   GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(20074), // Rule ID 1363 //
     /* 20032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 20035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
     /* 20040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 20046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20050 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 20054 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 20058 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immSExt10),
     /* 20062 */     // MIs[1] Operand 1
     /* 20062 */     // No operand predicates
     /* 20062 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 20064 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8463:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immSExt10>>:$imm)  =>  (REPL_PH_MM:{ *:[v2i16] } (imm:{ *:[i32] }):$imm)
     /* 20064 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_PH_MM),
     /* 20067 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20069 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 20072 */     GIR_RootConstrainSelectedInstOperands,
     /* 20073 */     // GIR_Coverage, 1363,
     /* 20073 */     GIR_EraseRootFromParent_Done,
     /* 20074 */   // Label 632: @20074
     /* 20074 */   GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(20121), // Rule ID 1364 //
     /* 20079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 20082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
     /* 20087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 20090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 20093 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20097 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 20101 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 20105 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt8),
     /* 20109 */     // MIs[1] Operand 1
     /* 20109 */     // No operand predicates
     /* 20109 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 20111 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8464:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_immZExt8>>:$imm)  =>  (REPL_QB_MM:{ *:[v4i8] } (imm:{ *:[i32] }):$imm)
     /* 20111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPL_QB_MM),
     /* 20114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 20116 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 20119 */     GIR_RootConstrainSelectedInstOperands,
     /* 20120 */     // GIR_Coverage, 1364,
     /* 20120 */     GIR_EraseRootFromParent_Done,
     /* 20121 */   // Label 633: @20121
     /* 20121 */   GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(20157), // Rule ID 437 //
     /* 20126 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20129 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
     /* 20134 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 20137 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20144 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20148 */     // (intrinsic_wo_chain:{ *:[i32] } 8461:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 20148 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB),
     /* 20151 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20153 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 20155 */     GIR_RootConstrainSelectedInstOperands,
     /* 20156 */     // GIR_Coverage, 437,
     /* 20156 */     GIR_EraseRootFromParent_Done,
     /* 20157 */   // Label 634: @20157
     /* 20157 */   GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(20193), // Rule ID 444 //
     /* 20162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
     /* 20170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 20173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 20176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20184 */     // (intrinsic_wo_chain:{ *:[i32] } 8443:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
     /* 20184 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL),
     /* 20187 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20189 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20191 */     GIR_RootConstrainSelectedInstOperands,
     /* 20192 */     // GIR_Coverage, 444,
     /* 20192 */     GIR_EraseRootFromParent_Done,
     /* 20193 */   // Label 635: @20193
     /* 20193 */   GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(20229), // Rule ID 445 //
     /* 20198 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20201 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
     /* 20206 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 20209 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 20212 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20216 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20220 */     // (intrinsic_wo_chain:{ *:[i32] } 8444:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECEQ_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rt)
     /* 20220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR),
     /* 20223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20225 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20227 */     GIR_RootConstrainSelectedInstOperands,
     /* 20228 */     // GIR_Coverage, 445,
     /* 20228 */     GIR_EraseRootFromParent_Done,
     /* 20229 */   // Label 636: @20229
     /* 20229 */   GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(20265), // Rule ID 446 //
     /* 20234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
     /* 20242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20245 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20248 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20252 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20256 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8445:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL),
     /* 20259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20261 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20263 */     GIR_RootConstrainSelectedInstOperands,
     /* 20264 */     // GIR_Coverage, 446,
     /* 20264 */     GIR_EraseRootFromParent_Done,
     /* 20265 */   // Label 637: @20265
     /* 20265 */   GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(20301), // Rule ID 447 //
     /* 20270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20273 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
     /* 20278 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20281 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20292 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8447:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR),
     /* 20295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20297 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20299 */     GIR_RootConstrainSelectedInstOperands,
     /* 20300 */     // GIR_Coverage, 447,
     /* 20300 */     GIR_EraseRootFromParent_Done,
     /* 20301 */   // Label 638: @20301
     /* 20301 */   GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(20337), // Rule ID 448 //
     /* 20306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
     /* 20314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20320 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20324 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20328 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8446:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20328 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA),
     /* 20331 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20333 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20335 */     GIR_RootConstrainSelectedInstOperands,
     /* 20336 */     // GIR_Coverage, 448,
     /* 20336 */     GIR_EraseRootFromParent_Done,
     /* 20337 */   // Label 639: @20337
     /* 20337 */   GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(20373), // Rule ID 449 //
     /* 20342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
     /* 20350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20364 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8448:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEQU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20364 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA),
     /* 20367 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20369 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20371 */     GIR_RootConstrainSelectedInstOperands,
     /* 20372 */     // GIR_Coverage, 449,
     /* 20372 */     GIR_EraseRootFromParent_Done,
     /* 20373 */   // Label 640: @20373
     /* 20373 */   GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(20409), // Rule ID 450 //
     /* 20378 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20381 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
     /* 20386 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20389 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20392 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20396 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20400 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20400 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL),
     /* 20403 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20405 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20407 */     GIR_RootConstrainSelectedInstOperands,
     /* 20408 */     // GIR_Coverage, 450,
     /* 20408 */     GIR_EraseRootFromParent_Done,
     /* 20409 */   // Label 641: @20409
     /* 20409 */   GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(20445), // Rule ID 451 //
     /* 20414 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20417 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
     /* 20422 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20425 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20428 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20432 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20436 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8451:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR),
     /* 20439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20441 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20443 */     GIR_RootConstrainSelectedInstOperands,
     /* 20444 */     // GIR_Coverage, 451,
     /* 20444 */     GIR_EraseRootFromParent_Done,
     /* 20445 */   // Label 642: @20445
     /* 20445 */   GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(20481), // Rule ID 452 //
     /* 20450 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20453 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
     /* 20458 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20461 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20468 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20472 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8450:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBLA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20472 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA),
     /* 20475 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20477 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20479 */     GIR_RootConstrainSelectedInstOperands,
     /* 20480 */     // GIR_Coverage, 452,
     /* 20480 */     GIR_EraseRootFromParent_Done,
     /* 20481 */   // Label 643: @20481
     /* 20481 */   GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(20517), // Rule ID 453 //
     /* 20486 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20489 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
     /* 20494 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20497 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 20500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20504 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20508 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PRECEU_PH_QBRA:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 20508 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA),
     /* 20511 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20513 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20515 */     GIR_RootConstrainSelectedInstOperands,
     /* 20516 */     // GIR_Coverage, 453,
     /* 20516 */     GIR_EraseRootFromParent_Done,
     /* 20517 */   // Label 644: @20517
     /* 20517 */   GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(20553), // Rule ID 501 //
     /* 20522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
     /* 20530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 20533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 20536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20540 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20544 */     // (intrinsic_wo_chain:{ *:[i32] } 8017:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (BITREV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 20544 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV),
     /* 20547 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20549 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20551 */     GIR_RootConstrainSelectedInstOperands,
     /* 20552 */     // GIR_Coverage, 501,
     /* 20552 */     GIR_EraseRootFromParent_Done,
     /* 20553 */   // Label 645: @20553
     /* 20553 */   GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(20589), // Rule ID 505 //
     /* 20558 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20561 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
     /* 20566 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 20569 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 20572 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20576 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20580 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8464:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_QB:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 20580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB),
     /* 20583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20585 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20587 */     GIR_RootConstrainSelectedInstOperands,
     /* 20588 */     // GIR_Coverage, 505,
     /* 20588 */     GIR_EraseRootFromParent_Done,
     /* 20589 */   // Label 646: @20589
     /* 20589 */   GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(20625), // Rule ID 506 //
     /* 20594 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 20597 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
     /* 20602 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 20605 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 20608 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 20612 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 20616 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (REPLV_PH:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 20616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH),
     /* 20619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 20621 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 20623 */     GIR_RootConstrainSelectedInstOperands,
     /* 20624 */     // GIR_Coverage, 506,
     /* 20624 */     GIR_EraseRootFromParent_Done,
     /* 20625 */   // Label 647: @20625
     /* 20625 */   GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(20661), // Rule ID 755 //
     /* 20630 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20633 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_w),
     /* 20638 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 20641 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 20644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20652 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8169:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FCLASS_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 20652 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_W),
     /* 20655 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20657 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20659 */     GIR_RootConstrainSelectedInstOperands,
     /* 20660 */     // GIR_Coverage, 755,
     /* 20660 */     GIR_EraseRootFromParent_Done,
     /* 20661 */   // Label 648: @20661
     /* 20661 */   GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(20697), // Rule ID 756 //
     /* 20666 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20669 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fclass_d),
     /* 20674 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 20677 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 20680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20688 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8168:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FCLASS_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 20688 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCLASS_D),
     /* 20691 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20693 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20695 */     GIR_RootConstrainSelectedInstOperands,
     /* 20696 */     // GIR_Coverage, 756,
     /* 20696 */     GIR_EraseRootFromParent_Done,
     /* 20697 */   // Label 649: @20697
     /* 20697 */   GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(20733), // Rule ID 779 //
     /* 20702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_w),
     /* 20710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 20713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 20716 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20720 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 20724 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8195:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
     /* 20724 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_W),
     /* 20727 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20729 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20731 */     GIR_RootConstrainSelectedInstOperands,
     /* 20732 */     // GIR_Coverage, 779,
     /* 20732 */     GIR_EraseRootFromParent_Done,
     /* 20733 */   // Label 650: @20733
     /* 20733 */   GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(20769), // Rule ID 780 //
     /* 20738 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20741 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupl_d),
     /* 20746 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 20749 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 20752 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20756 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20760 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8194:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 20760 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPL_D),
     /* 20763 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20765 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20767 */     GIR_RootConstrainSelectedInstOperands,
     /* 20768 */     // GIR_Coverage, 780,
     /* 20768 */     GIR_EraseRootFromParent_Done,
     /* 20769 */   // Label 651: @20769
     /* 20769 */   GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(20805), // Rule ID 781 //
     /* 20774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20777 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_w),
     /* 20782 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 20785 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 20788 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20792 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 20796 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8197:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8f16] }:$ws)  =>  (FEXUPR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8f16] }:$ws)
     /* 20796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_W),
     /* 20799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20801 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20803 */     GIR_RootConstrainSelectedInstOperands,
     /* 20804 */     // GIR_Coverage, 781,
     /* 20804 */     GIR_EraseRootFromParent_Done,
     /* 20805 */   // Label 652: @20805
     /* 20805 */   GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(20841), // Rule ID 782 //
     /* 20810 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20813 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexupr_d),
     /* 20818 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 20821 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 20824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20832 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8196:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXUPR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 20832 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXUPR_D),
     /* 20835 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20837 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20839 */     GIR_RootConstrainSelectedInstOperands,
     /* 20840 */     // GIR_Coverage, 782,
     /* 20840 */     GIR_EraseRootFromParent_Done,
     /* 20841 */   // Label 653: @20841
     /* 20841 */   GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(20877), // Rule ID 787 //
     /* 20846 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20849 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_w),
     /* 20854 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 20857 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 20860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20864 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 20868 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8203:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQL_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
     /* 20868 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_W),
     /* 20871 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20873 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20875 */     GIR_RootConstrainSelectedInstOperands,
     /* 20876 */     // GIR_Coverage, 787,
     /* 20876 */     GIR_EraseRootFromParent_Done,
     /* 20877 */   // Label 654: @20877
     /* 20877 */   GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(20913), // Rule ID 788 //
     /* 20882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20885 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffql_d),
     /* 20890 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 20893 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 20896 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20900 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20904 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8202:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQL_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 20904 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQL_D),
     /* 20907 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20909 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20911 */     GIR_RootConstrainSelectedInstOperands,
     /* 20912 */     // GIR_Coverage, 788,
     /* 20912 */     GIR_EraseRootFromParent_Done,
     /* 20913 */   // Label 655: @20913
     /* 20913 */   GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(20949), // Rule ID 789 //
     /* 20918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20921 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_w),
     /* 20926 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 20929 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 20932 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20936 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 20940 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8205:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (FFQR_W:{ *:[v4f32] } MSA128HOpnd:{ *:[v8i16] }:$ws)
     /* 20940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_W),
     /* 20943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20945 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20947 */     GIR_RootConstrainSelectedInstOperands,
     /* 20948 */     // GIR_Coverage, 789,
     /* 20948 */     GIR_EraseRootFromParent_Done,
     /* 20949 */   // Label 656: @20949
     /* 20949 */   GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(20985), // Rule ID 790 //
     /* 20954 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20957 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ffqr_d),
     /* 20962 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 20965 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 20968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 20972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 20976 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8204:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFQR_D:{ *:[v2f64] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 20976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FFQR_D),
     /* 20979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 20981 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 20983 */     GIR_RootConstrainSelectedInstOperands,
     /* 20984 */     // GIR_Coverage, 790,
     /* 20984 */     GIR_EraseRootFromParent_Done,
     /* 20985 */   // Label 657: @20985
     /* 20985 */   GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(21021), // Rule ID 815 //
     /* 20990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 20993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_w),
     /* 20998 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 21001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 21004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21012 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8227:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRCP_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 21012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_W),
     /* 21015 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21017 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21019 */     GIR_RootConstrainSelectedInstOperands,
     /* 21020 */     // GIR_Coverage, 815,
     /* 21020 */     GIR_EraseRootFromParent_Done,
     /* 21021 */   // Label 658: @21021
     /* 21021 */   GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(21057), // Rule ID 816 //
     /* 21026 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21029 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frcp_d),
     /* 21034 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 21037 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 21040 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21044 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21048 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8226:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRCP_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 21048 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRCP_D),
     /* 21051 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21053 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21055 */     GIR_RootConstrainSelectedInstOperands,
     /* 21056 */     // GIR_Coverage, 816,
     /* 21056 */     GIR_EraseRootFromParent_Done,
     /* 21057 */   // Label 659: @21057
     /* 21057 */   GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(21093), // Rule ID 817 //
     /* 21062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_w),
     /* 21070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 21073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 21076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21080 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21084 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8231:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 21084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_W),
     /* 21087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21089 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21091 */     GIR_RootConstrainSelectedInstOperands,
     /* 21092 */     // GIR_Coverage, 817,
     /* 21092 */     GIR_EraseRootFromParent_Done,
     /* 21093 */   // Label 660: @21093
     /* 21093 */   GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(21129), // Rule ID 818 //
     /* 21098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_frsqrt_d),
     /* 21106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 21109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 21112 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21116 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21120 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8230:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 21120 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FRSQRT_D),
     /* 21123 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21125 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21127 */     GIR_RootConstrainSelectedInstOperands,
     /* 21128 */     // GIR_Coverage, 818,
     /* 21128 */     GIR_EraseRootFromParent_Done,
     /* 21129 */   // Label 661: @21129
     /* 21129 */   GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(21165), // Rule ID 845 //
     /* 21134 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21137 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_w),
     /* 21142 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 21145 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 21148 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21152 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21156 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8259:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 21156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_W),
     /* 21159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21161 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21163 */     GIR_RootConstrainSelectedInstOperands,
     /* 21164 */     // GIR_Coverage, 845,
     /* 21164 */     GIR_EraseRootFromParent_Done,
     /* 21165 */   // Label 662: @21165
     /* 21165 */   GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(21201), // Rule ID 846 //
     /* 21170 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21173 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_s_d),
     /* 21178 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 21181 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 21184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21192 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8258:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 21192 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_S_D),
     /* 21195 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21197 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21199 */     GIR_RootConstrainSelectedInstOperands,
     /* 21200 */     // GIR_Coverage, 846,
     /* 21200 */     GIR_EraseRootFromParent_Done,
     /* 21201 */   // Label 663: @21201
     /* 21201 */   GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(21237), // Rule ID 847 //
     /* 21206 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21209 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_w),
     /* 21214 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 21217 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 21220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21224 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21228 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8261:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTINT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 21228 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_W),
     /* 21231 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21233 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21235 */     GIR_RootConstrainSelectedInstOperands,
     /* 21236 */     // GIR_Coverage, 847,
     /* 21236 */     GIR_EraseRootFromParent_Done,
     /* 21237 */   // Label 664: @21237
     /* 21237 */   GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(21273), // Rule ID 848 //
     /* 21242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftint_u_d),
     /* 21250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 21253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 21256 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21260 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21264 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8260:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTINT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 21264 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTINT_U_D),
     /* 21267 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21269 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21271 */     GIR_RootConstrainSelectedInstOperands,
     /* 21272 */     // GIR_Coverage, 848,
     /* 21272 */     GIR_EraseRootFromParent_Done,
     /* 21273 */   // Label 665: @21273
     /* 21273 */   GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(21309), // Rule ID 983 //
     /* 21278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21281 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_b),
     /* 21286 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 21289 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 21292 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 21296 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 21300 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8416:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLOC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
     /* 21300 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_B),
     /* 21303 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21305 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21307 */     GIR_RootConstrainSelectedInstOperands,
     /* 21308 */     // GIR_Coverage, 983,
     /* 21308 */     GIR_EraseRootFromParent_Done,
     /* 21309 */   // Label 666: @21309
     /* 21309 */   GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(21345), // Rule ID 984 //
     /* 21314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21317 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_h),
     /* 21322 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 21325 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 21328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 21332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 21336 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8418:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLOC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
     /* 21336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_H),
     /* 21339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21341 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21343 */     GIR_RootConstrainSelectedInstOperands,
     /* 21344 */     // GIR_Coverage, 984,
     /* 21344 */     GIR_EraseRootFromParent_Done,
     /* 21345 */   // Label 667: @21345
     /* 21345 */   GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(21381), // Rule ID 985 //
     /* 21350 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21353 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_w),
     /* 21358 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 21361 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 21364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21368 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 21372 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8419:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLOC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 21372 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_W),
     /* 21375 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21377 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21379 */     GIR_RootConstrainSelectedInstOperands,
     /* 21380 */     // GIR_Coverage, 985,
     /* 21380 */     GIR_EraseRootFromParent_Done,
     /* 21381 */   // Label 668: @21381
     /* 21381 */   GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(21417), // Rule ID 986 //
     /* 21386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21389 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_nloc_d),
     /* 21394 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 21397 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 21400 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21404 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 21408 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8417:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLOC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
     /* 21408 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NLOC_D),
     /* 21411 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21413 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21415 */     GIR_RootConstrainSelectedInstOperands,
     /* 21416 */     // GIR_Coverage, 986,
     /* 21416 */     GIR_EraseRootFromParent_Done,
     /* 21417 */   // Label 669: @21417
     /* 21417 */   GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(21453), // Rule ID 1326 //
     /* 21422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phl),
     /* 21430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 21433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 21436 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21444 */     // (intrinsic_wo_chain:{ *:[i32] } 8443:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
     /* 21444 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHL_MM),
     /* 21447 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21449 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21451 */     GIR_RootConstrainSelectedInstOperands,
     /* 21452 */     // GIR_Coverage, 1326,
     /* 21452 */     GIR_EraseRootFromParent_Done,
     /* 21453 */   // Label 670: @21453
     /* 21453 */   GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(21489), // Rule ID 1327 //
     /* 21458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceq_w_phr),
     /* 21466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 21469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 21472 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21476 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21480 */     // (intrinsic_wo_chain:{ *:[i32] } 8444:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (PRECEQ_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs)
     /* 21480 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQ_W_PHR_MM),
     /* 21483 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21485 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21487 */     GIR_RootConstrainSelectedInstOperands,
     /* 21488 */     // GIR_Coverage, 1327,
     /* 21488 */     GIR_EraseRootFromParent_Done,
     /* 21489 */   // Label 671: @21489
     /* 21489 */   GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(21525), // Rule ID 1328 //
     /* 21494 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21497 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbl),
     /* 21502 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21505 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21508 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21512 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21516 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8445:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBL_MM),
     /* 21519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21521 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21523 */     GIR_RootConstrainSelectedInstOperands,
     /* 21524 */     // GIR_Coverage, 1328,
     /* 21524 */     GIR_EraseRootFromParent_Done,
     /* 21525 */   // Label 672: @21525
     /* 21525 */   GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(21561), // Rule ID 1329 //
     /* 21530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21533 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbla),
     /* 21538 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21541 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21552 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8446:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBLA_MM),
     /* 21555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21557 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21559 */     GIR_RootConstrainSelectedInstOperands,
     /* 21560 */     // GIR_Coverage, 1329,
     /* 21560 */     GIR_EraseRootFromParent_Done,
     /* 21561 */   // Label 673: @21561
     /* 21561 */   GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(21597), // Rule ID 1330 //
     /* 21566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbr),
     /* 21574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21584 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21588 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8447:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBR_MM),
     /* 21591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21593 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21595 */     GIR_RootConstrainSelectedInstOperands,
     /* 21596 */     // GIR_Coverage, 1330,
     /* 21596 */     GIR_EraseRootFromParent_Done,
     /* 21597 */   // Label 674: @21597
     /* 21597 */   GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(21633), // Rule ID 1331 //
     /* 21602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precequ_ph_qbra),
     /* 21610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21620 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21624 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8448:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEQU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21624 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEQU_PH_QBRA_MM),
     /* 21627 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21629 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21631 */     GIR_RootConstrainSelectedInstOperands,
     /* 21632 */     // GIR_Coverage, 1331,
     /* 21632 */     GIR_EraseRootFromParent_Done,
     /* 21633 */   // Label 675: @21633
     /* 21633 */   GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(21669), // Rule ID 1332 //
     /* 21638 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21641 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbl),
     /* 21646 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21649 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21652 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21656 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21660 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8449:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBL_MM),
     /* 21663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21665 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21667 */     GIR_RootConstrainSelectedInstOperands,
     /* 21668 */     // GIR_Coverage, 1332,
     /* 21668 */     GIR_EraseRootFromParent_Done,
     /* 21669 */   // Label 676: @21669
     /* 21669 */   GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(21705), // Rule ID 1333 //
     /* 21674 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21677 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbla),
     /* 21682 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21685 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21696 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8450:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBLA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBLA_MM),
     /* 21699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21701 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21703 */     GIR_RootConstrainSelectedInstOperands,
     /* 21704 */     // GIR_Coverage, 1333,
     /* 21704 */     GIR_EraseRootFromParent_Done,
     /* 21705 */   // Label 677: @21705
     /* 21705 */   GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(21741), // Rule ID 1334 //
     /* 21710 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21713 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbr),
     /* 21718 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21721 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21732 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8451:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21732 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBR_MM),
     /* 21735 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21737 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21739 */     GIR_RootConstrainSelectedInstOperands,
     /* 21740 */     // GIR_Coverage, 1334,
     /* 21740 */     GIR_EraseRootFromParent_Done,
     /* 21741 */   // Label 678: @21741
     /* 21741 */   GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(21777), // Rule ID 1335 //
     /* 21746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21749 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_preceu_ph_qbra),
     /* 21754 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21757 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21768 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8452:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (PRECEU_PH_QBRA_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21768 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECEU_PH_QBRA_MM),
     /* 21771 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21773 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21775 */     GIR_RootConstrainSelectedInstOperands,
     /* 21776 */     // GIR_Coverage, 1335,
     /* 21776 */     GIR_EraseRootFromParent_Done,
     /* 21777 */   // Label 679: @21777
     /* 21777 */   GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(21813), // Rule ID 1361 //
     /* 21782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_raddu_w_qb),
     /* 21790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 21793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 21796 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21800 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21804 */     // (intrinsic_wo_chain:{ *:[i32] } 8461:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (RADDU_W_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 21804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RADDU_W_QB_MM),
     /* 21807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21809 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21811 */     GIR_RootConstrainSelectedInstOperands,
     /* 21812 */     // GIR_Coverage, 1361,
     /* 21812 */     GIR_EraseRootFromParent_Done,
     /* 21813 */   // Label 680: @21813
     /* 21813 */   GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(21849), // Rule ID 1365 //
     /* 21818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_ph),
     /* 21826 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 21829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 21832 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21836 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21840 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8463:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_PH_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 21840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_PH_MM),
     /* 21843 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21845 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21847 */     GIR_RootConstrainSelectedInstOperands,
     /* 21848 */     // GIR_Coverage, 1365,
     /* 21848 */     GIR_EraseRootFromParent_Done,
     /* 21849 */   // Label 681: @21849
     /* 21849 */   GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(21885), // Rule ID 1366 //
     /* 21854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21857 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_repl_qb),
     /* 21862 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 21865 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 21868 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 21872 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21876 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8464:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (REPLV_QB_MM:{ *:[v4i8] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 21876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::REPLV_QB_MM),
     /* 21879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21881 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21883 */     GIR_RootConstrainSelectedInstOperands,
     /* 21884 */     // GIR_Coverage, 1366,
     /* 21884 */     GIR_EraseRootFromParent_Done,
     /* 21885 */   // Label 682: @21885
     /* 21885 */   GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(21921), // Rule ID 1376 //
     /* 21890 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 21893 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bitrev),
     /* 21898 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 21901 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 21904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21908 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 21912 */     // (intrinsic_wo_chain:{ *:[i32] } 8017:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (BITREV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 21912 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BITREV_MM),
     /* 21915 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 21917 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 21919 */     GIR_RootConstrainSelectedInstOperands,
     /* 21920 */     // GIR_Coverage, 1376,
     /* 21920 */     GIR_EraseRootFromParent_Done,
     /* 21921 */   // Label 683: @21921
     /* 21921 */   GIM_Reject,
     /* 21922 */ // Label 629: @21922
     /* 21922 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31675),
     /* 21927 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 21930 */   GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(21976), // Rule ID 1013 //
     /* 21935 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21938 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_b),
     /* 21943 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 21946 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 21949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 21953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 21957 */     // MIs[0] m
     /* 21957 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 21960 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
     /* 21965 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8465:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
     /* 21965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_B),
     /* 21968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 21970 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 21972 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 21974 */     GIR_RootConstrainSelectedInstOperands,
     /* 21975 */     // GIR_Coverage, 1013,
     /* 21975 */     GIR_EraseRootFromParent_Done,
     /* 21976 */   // Label 685: @21976
     /* 21976 */   GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(22022), // Rule ID 1014 //
     /* 21981 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 21984 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_h),
     /* 21989 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 21992 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 21995 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 21999 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22003 */     // MIs[0] m
     /* 22003 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22006 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
     /* 22011 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8467:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_H),
     /* 22014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22016 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22018 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22020 */     GIR_RootConstrainSelectedInstOperands,
     /* 22021 */     // GIR_Coverage, 1014,
     /* 22021 */     GIR_EraseRootFromParent_Done,
     /* 22022 */   // Label 686: @22022
     /* 22022 */   GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(22068), // Rule ID 1015 //
     /* 22027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_w),
     /* 22035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 22038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 22041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22045 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22049 */     // MIs[0] m
     /* 22049 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22052 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 22057 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8468:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22057 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_W),
     /* 22060 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22062 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22064 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22066 */     GIR_RootConstrainSelectedInstOperands,
     /* 22067 */     // GIR_Coverage, 1015,
     /* 22067 */     GIR_EraseRootFromParent_Done,
     /* 22068 */   // Label 687: @22068
     /* 22068 */   GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(22114), // Rule ID 1016 //
     /* 22073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_s_d),
     /* 22081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 22084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 22087 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22091 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22095 */     // MIs[0] m
     /* 22095 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22098 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
     /* 22103 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8466:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22103 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_S_D),
     /* 22106 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22108 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22110 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22112 */     GIR_RootConstrainSelectedInstOperands,
     /* 22113 */     // GIR_Coverage, 1016,
     /* 22113 */     GIR_EraseRootFromParent_Done,
     /* 22114 */   // Label 688: @22114
     /* 22114 */   GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(22160), // Rule ID 1017 //
     /* 22119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_b),
     /* 22127 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 22130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 22133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22141 */     // MIs[0] m
     /* 22141 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22144 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
     /* 22149 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8469:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SAT_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_B),
     /* 22152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22154 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22156 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22158 */     GIR_RootConstrainSelectedInstOperands,
     /* 22159 */     // GIR_Coverage, 1017,
     /* 22159 */     GIR_EraseRootFromParent_Done,
     /* 22160 */   // Label 689: @22160
     /* 22160 */   GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(22206), // Rule ID 1018 //
     /* 22165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22168 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_h),
     /* 22173 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 22176 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 22179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22183 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22187 */     // MIs[0] m
     /* 22187 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22190 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
     /* 22195 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8471:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SAT_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22195 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_H),
     /* 22198 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22200 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22202 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22204 */     GIR_RootConstrainSelectedInstOperands,
     /* 22205 */     // GIR_Coverage, 1018,
     /* 22205 */     GIR_EraseRootFromParent_Done,
     /* 22206 */   // Label 690: @22206
     /* 22206 */   GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(22252), // Rule ID 1019 //
     /* 22211 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22214 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_w),
     /* 22219 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 22222 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 22225 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22233 */     // MIs[0] m
     /* 22233 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22236 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 22241 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8472:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SAT_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_W),
     /* 22244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22246 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22248 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22250 */     GIR_RootConstrainSelectedInstOperands,
     /* 22251 */     // GIR_Coverage, 1019,
     /* 22251 */     GIR_EraseRootFromParent_Done,
     /* 22252 */   // Label 691: @22252
     /* 22252 */   GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(22298), // Rule ID 1020 //
     /* 22257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sat_u_d),
     /* 22265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 22268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 22271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22279 */     // MIs[0] m
     /* 22279 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22282 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
     /* 22287 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8470:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SAT_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22287 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SAT_U_D),
     /* 22290 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22292 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22294 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22296 */     GIR_RootConstrainSelectedInstOperands,
     /* 22297 */     // GIR_Coverage, 1020,
     /* 22297 */     GIR_EraseRootFromParent_Done,
     /* 22298 */   // Label 692: @22298
     /* 22298 */   GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(22344), // Rule ID 1060 //
     /* 22303 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22306 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_b),
     /* 22311 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 22314 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 22317 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22325 */     // MIs[0] m
     /* 22325 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22328 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
     /* 22333 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8524:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRARI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22333 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_B),
     /* 22336 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22338 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22340 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22342 */     GIR_RootConstrainSelectedInstOperands,
     /* 22343 */     // GIR_Coverage, 1060,
     /* 22343 */     GIR_EraseRootFromParent_Done,
     /* 22344 */   // Label 693: @22344
     /* 22344 */   GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(22390), // Rule ID 1061 //
     /* 22349 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22352 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_h),
     /* 22357 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 22360 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 22363 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22367 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22371 */     // MIs[0] m
     /* 22371 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22374 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
     /* 22379 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8526:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRARI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22379 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_H),
     /* 22382 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22384 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22386 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22388 */     GIR_RootConstrainSelectedInstOperands,
     /* 22389 */     // GIR_Coverage, 1061,
     /* 22389 */     GIR_EraseRootFromParent_Done,
     /* 22390 */   // Label 694: @22390
     /* 22390 */   GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(22436), // Rule ID 1062 //
     /* 22395 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22398 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_w),
     /* 22403 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 22406 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 22409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22417 */     // MIs[0] m
     /* 22417 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22420 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 22425 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8527:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRARI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22425 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_W),
     /* 22428 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22430 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22432 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22434 */     GIR_RootConstrainSelectedInstOperands,
     /* 22435 */     // GIR_Coverage, 1062,
     /* 22435 */     GIR_EraseRootFromParent_Done,
     /* 22436 */   // Label 695: @22436
     /* 22436 */   GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(22482), // Rule ID 1063 //
     /* 22441 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22444 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srari_d),
     /* 22449 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 22452 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 22455 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22459 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22463 */     // MIs[0] m
     /* 22463 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22466 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
     /* 22471 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8525:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRARI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRARI_D),
     /* 22474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22476 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22478 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22480 */     GIR_RootConstrainSelectedInstOperands,
     /* 22481 */     // GIR_Coverage, 1063,
     /* 22481 */     GIR_EraseRootFromParent_Done,
     /* 22482 */   // Label 696: @22482
     /* 22482 */   GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(22528), // Rule ID 1076 //
     /* 22487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_b),
     /* 22495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 22498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 22501 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22505 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 22509 */     // MIs[0] m
     /* 22509 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22512 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
     /* 22517 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8540:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$m)  =>  (SRLRI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_B),
     /* 22520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22522 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22524 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22526 */     GIR_RootConstrainSelectedInstOperands,
     /* 22527 */     // GIR_Coverage, 1076,
     /* 22527 */     GIR_EraseRootFromParent_Done,
     /* 22528 */   // Label 697: @22528
     /* 22528 */   GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(22574), // Rule ID 1077 //
     /* 22533 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22536 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_h),
     /* 22541 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 22544 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 22547 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22551 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 22555 */     // MIs[0] m
     /* 22555 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22558 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
     /* 22563 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8542:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$m)  =>  (SRLRI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22563 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_H),
     /* 22566 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22568 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22570 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22572 */     GIR_RootConstrainSelectedInstOperands,
     /* 22573 */     // GIR_Coverage, 1077,
     /* 22573 */     GIR_EraseRootFromParent_Done,
     /* 22574 */   // Label 698: @22574
     /* 22574 */   GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(22620), // Rule ID 1078 //
     /* 22579 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22582 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_w),
     /* 22587 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 22590 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 22593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22597 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 22601 */     // MIs[0] m
     /* 22601 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22604 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 22609 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8543:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$m)  =>  (SRLRI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_W),
     /* 22612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22614 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22616 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22618 */     GIR_RootConstrainSelectedInstOperands,
     /* 22619 */     // GIR_Coverage, 1078,
     /* 22619 */     GIR_EraseRootFromParent_Done,
     /* 22620 */   // Label 699: @22620
     /* 22620 */   GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(22666), // Rule ID 1079 //
     /* 22625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 22628 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlri_d),
     /* 22633 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 22636 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 22639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22643 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 22647 */     // MIs[0] m
     /* 22647 */     GIM_CheckIsImm, /*MI*/0, /*Op*/3,
     /* 22650 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt6),
     /* 22655 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8541:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt6>>:$m)  =>  (SRLRI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$m)
     /* 22655 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLRI_D),
     /* 22658 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 22660 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 22662 */     GIR_RootToRootCopy, /*OpIdx*/3, // m
     /* 22664 */     GIR_RootConstrainSelectedInstOperands,
     /* 22665 */     // GIR_Coverage, 1079,
     /* 22665 */     GIR_EraseRootFromParent_Done,
     /* 22666 */   // Label 700: @22666
     /* 22666 */   GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(22722), // Rule ID 460 //
     /* 22671 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 22674 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
     /* 22679 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 22682 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 22685 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22688 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22692 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22696 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22700 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22704 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 22708 */     // MIs[1] Operand 1
     /* 22708 */     // No operand predicates
     /* 22708 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22710 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHRA_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
     /* 22710 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH),
     /* 22713 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 22715 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 22717 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
     /* 22720 */     GIR_RootConstrainSelectedInstOperands,
     /* 22721 */     // GIR_Coverage, 460,
     /* 22721 */     GIR_EraseRootFromParent_Done,
     /* 22722 */   // Label 701: @22722
     /* 22722 */   GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(22778), // Rule ID 464 //
     /* 22727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 22730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
     /* 22735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 22738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 22741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 22748 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 22752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22760 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 22764 */     // MIs[1] Operand 1
     /* 22764 */     // No operand predicates
     /* 22764 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22766 */     // (intrinsic_wo_chain:{ *:[i32] } 8485:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHRA_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
     /* 22766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W),
     /* 22769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 22771 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 22773 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
     /* 22776 */     GIR_RootConstrainSelectedInstOperands,
     /* 22777 */     // GIR_Coverage, 464,
     /* 22777 */     GIR_EraseRootFromParent_Done,
     /* 22778 */   // Label 702: @22778
     /* 22778 */   GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(22834), // Rule ID 555 //
     /* 22783 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 22786 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
     /* 22791 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 22794 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 22797 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22800 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22804 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22808 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22812 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22816 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
     /* 22820 */     // MIs[1] Operand 1
     /* 22820 */     // No operand predicates
     /* 22820 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22822 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$rs_sa)  =>  (SHRA_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, (imm:{ *:[i32] }):$rs_sa)
     /* 22822 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB),
     /* 22825 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 22827 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 22829 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
     /* 22832 */     GIR_RootConstrainSelectedInstOperands,
     /* 22833 */     // GIR_Coverage, 555,
     /* 22833 */     GIR_EraseRootFromParent_Done,
     /* 22834 */   // Label 703: @22834
     /* 22834 */   GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(22890), // Rule ID 1320 //
     /* 22839 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 22842 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
     /* 22847 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 22850 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 22853 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22856 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22860 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22872 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 22876 */     // MIs[1] Operand 1
     /* 22876 */     // No operand predicates
     /* 22876 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22878 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHRA_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
     /* 22878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_PH_MM),
     /* 22881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 22883 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 22885 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
     /* 22888 */     GIR_RootConstrainSelectedInstOperands,
     /* 22889 */     // GIR_Coverage, 1320,
     /* 22889 */     GIR_EraseRootFromParent_Done,
     /* 22890 */   // Label 704: @22890
     /* 22890 */   GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(22946), // Rule ID 1324 //
     /* 22895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 22898 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
     /* 22903 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 22906 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 22909 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22912 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 22916 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 22920 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22924 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22928 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 22932 */     // MIs[1] Operand 1
     /* 22932 */     // No operand predicates
     /* 22932 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22934 */     // (intrinsic_wo_chain:{ *:[i32] } 8485:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHRA_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
     /* 22934 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_W_MM),
     /* 22937 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 22939 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 22941 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
     /* 22944 */     GIR_RootConstrainSelectedInstOperands,
     /* 22945 */     // GIR_Coverage, 1324,
     /* 22945 */     GIR_EraseRootFromParent_Done,
     /* 22946 */   // Label 705: @22946
     /* 22946 */   GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(23002), // Rule ID 1399 //
     /* 22951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 22954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
     /* 22959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 22962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 22965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 22968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 22976 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 22980 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 22984 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
     /* 22988 */     // MIs[1] Operand 1
     /* 22988 */     // No operand predicates
     /* 22988 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 22990 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$sa)  =>  (SHRA_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, (imm:{ *:[i32] }):$sa)
     /* 22990 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_R_QB_MMR2),
     /* 22993 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 22995 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 22997 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
     /* 23000 */     GIR_RootConstrainSelectedInstOperands,
     /* 23001 */     // GIR_Coverage, 1399,
     /* 23001 */     GIR_EraseRootFromParent_Done,
     /* 23002 */   // Label 706: @23002
     /* 23002 */   GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(23054), // Rule ID 2070 //
     /* 23007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
     /* 23015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23028 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 23032 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 23036 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 23040 */     // MIs[1] Operand 1
     /* 23040 */     // No operand predicates
     /* 23040 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 23042 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8481:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRA_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
     /* 23042 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_PH),
     /* 23045 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23047 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 23049 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 23052 */     GIR_RootConstrainSelectedInstOperands,
     /* 23053 */     // GIR_Coverage, 2070,
     /* 23053 */     GIR_EraseRootFromParent_Done,
     /* 23054 */   // Label 707: @23054
     /* 23054 */   GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(23106), // Rule ID 2071 //
     /* 23059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
     /* 23067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23076 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23080 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 23084 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 23088 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 23092 */     // MIs[1] Operand 1
     /* 23092 */     // No operand predicates
     /* 23092 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 23094 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHRL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
     /* 23094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_PH),
     /* 23097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23099 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 23101 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 23104 */     GIR_RootConstrainSelectedInstOperands,
     /* 23105 */     // GIR_Coverage, 2071,
     /* 23105 */     GIR_EraseRootFromParent_Done,
     /* 23106 */   // Label 708: @23106
     /* 23106 */   GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(23158), // Rule ID 2076 //
     /* 23111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
     /* 23119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23122 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23125 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23132 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 23136 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 23140 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
     /* 23144 */     // MIs[1] Operand 1
     /* 23144 */     // No operand predicates
     /* 23144 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 23146 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8482:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRA_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
     /* 23146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRA_QB),
     /* 23149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23151 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 23153 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 23156 */     GIR_RootConstrainSelectedInstOperands,
     /* 23157 */     // GIR_Coverage, 2076,
     /* 23157 */     GIR_EraseRootFromParent_Done,
     /* 23158 */   // Label 709: @23158
     /* 23158 */   GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(23210), // Rule ID 2077 //
     /* 23163 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23166 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
     /* 23171 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23174 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23177 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 23188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 23192 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
     /* 23196 */     // MIs[1] Operand 1
     /* 23196 */     // No operand predicates
     /* 23196 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 23198 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8487:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHRL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
     /* 23198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRL_QB),
     /* 23201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23203 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 23205 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 23208 */     GIR_RootConstrainSelectedInstOperands,
     /* 23209 */     // GIR_Coverage, 2077,
     /* 23209 */     GIR_EraseRootFromParent_Done,
     /* 23210 */   // Label 710: @23210
     /* 23210 */   GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(23258), // Rule ID 430 //
     /* 23215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23218 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
     /* 23223 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23226 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23229 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23232 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23236 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23240 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23244 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7953:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23244 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB),
     /* 23247 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23249 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23251 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23253 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 23256 */     GIR_RootConstrainSelectedInstOperands,
     /* 23257 */     // GIR_Coverage, 430,
     /* 23257 */     GIR_EraseRootFromParent_Done,
     /* 23258 */   // Label 711: @23258
     /* 23258 */   GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(23306), // Rule ID 431 //
     /* 23263 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23266 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
     /* 23271 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23274 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23277 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23280 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23284 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23288 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23292 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8576:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23292 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB),
     /* 23295 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23297 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23299 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23301 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 23304 */     GIR_RootConstrainSelectedInstOperands,
     /* 23305 */     // GIR_Coverage, 431,
     /* 23305 */     GIR_EraseRootFromParent_Done,
     /* 23306 */   // Label 712: @23306
     /* 23306 */   GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(23354), // Rule ID 432 //
     /* 23311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
     /* 23319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 23328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23336 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23340 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7931:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 23340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH),
     /* 23343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23345 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23347 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23349 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 23352 */     GIR_RootConstrainSelectedInstOperands,
     /* 23353 */     // GIR_Coverage, 432,
     /* 23353 */     GIR_EraseRootFromParent_Done,
     /* 23354 */   // Label 713: @23354
     /* 23354 */   GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(23402), // Rule ID 433 //
     /* 23359 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23362 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
     /* 23367 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23370 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23373 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 23376 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23380 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23384 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23388 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8551:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 23388 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH),
     /* 23391 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23393 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23395 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23397 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 23400 */     GIR_RootConstrainSelectedInstOperands,
     /* 23401 */     // GIR_Coverage, 433,
     /* 23401 */     GIR_EraseRootFromParent_Done,
     /* 23402 */   // Label 714: @23402
     /* 23402 */   GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(23447), // Rule ID 436 //
     /* 23407 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23410 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
     /* 23415 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 23418 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 23421 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23428 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23432 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23436 */     // (intrinsic_wo_chain:{ *:[i32] } 8381:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 23436 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB),
     /* 23439 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23441 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23443 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23445 */     GIR_RootConstrainSelectedInstOperands,
     /* 23446 */     // GIR_Coverage, 436,
     /* 23446 */     GIR_EraseRootFromParent_Done,
     /* 23447 */   // Label 715: @23447
     /* 23447 */   GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(23492), // Rule ID 440 //
     /* 23452 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23455 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
     /* 23460 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23463 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23466 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 23469 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23477 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23481 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8457:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 23481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH),
     /* 23484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23486 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23488 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23490 */     GIR_RootConstrainSelectedInstOperands,
     /* 23491 */     // GIR_Coverage, 440,
     /* 23491 */     GIR_EraseRootFromParent_Done,
     /* 23492 */   // Label 716: @23492
     /* 23492 */   GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(23537), // Rule ID 441 //
     /* 23497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23500 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
     /* 23505 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23508 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 23511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23518 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23522 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23526 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8456:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 23526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W),
     /* 23529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23531 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23533 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23535 */     GIR_RootConstrainSelectedInstOperands,
     /* 23536 */     // GIR_Coverage, 441,
     /* 23536 */     GIR_EraseRootFromParent_Done,
     /* 23537 */   // Label 717: @23537
     /* 23537 */   GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(23582), // Rule ID 455 //
     /* 23542 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23545 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
     /* 23550 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23553 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23556 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23559 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23563 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23567 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23571 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 23571 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB),
     /* 23574 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23576 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 23578 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 23580 */     GIR_RootConstrainSelectedInstOperands,
     /* 23581 */     // GIR_Coverage, 455,
     /* 23581 */     GIR_EraseRootFromParent_Done,
     /* 23582 */   // Label 718: @23582
     /* 23582 */   GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(23627), // Rule ID 459 //
     /* 23587 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23590 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
     /* 23595 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23598 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23601 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23604 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23608 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23612 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23616 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 23616 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH),
     /* 23619 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23621 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 23623 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 23625 */     GIR_RootConstrainSelectedInstOperands,
     /* 23626 */     // GIR_Coverage, 459,
     /* 23626 */     GIR_EraseRootFromParent_Done,
     /* 23627 */   // Label 719: @23627
     /* 23627 */   GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(23672), // Rule ID 461 //
     /* 23632 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23635 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
     /* 23640 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23643 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23646 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23649 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23653 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23657 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23661 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 23661 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH),
     /* 23664 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23666 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 23668 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 23670 */     GIR_RootConstrainSelectedInstOperands,
     /* 23671 */     // GIR_Coverage, 461,
     /* 23671 */     GIR_EraseRootFromParent_Done,
     /* 23672 */   // Label 720: @23672
     /* 23672 */   GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(23717), // Rule ID 465 //
     /* 23677 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23680 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
     /* 23685 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 23688 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 23691 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 23694 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23698 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23702 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 23706 */     // (intrinsic_wo_chain:{ *:[i32] } 8485:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 23706 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W),
     /* 23709 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23711 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 23713 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 23715 */     GIR_RootConstrainSelectedInstOperands,
     /* 23716 */     // GIR_Coverage, 465,
     /* 23716 */     GIR_EraseRootFromParent_Done,
     /* 23717 */   // Label 721: @23717
     /* 23717 */   GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(23762), // Rule ID 502 //
     /* 23722 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 23725 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
     /* 23730 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23733 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23736 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 23739 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23743 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23747 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23751 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8428:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 23751 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH),
     /* 23754 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23756 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23758 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23760 */     GIR_RootConstrainSelectedInstOperands,
     /* 23761 */     // GIR_Coverage, 502,
     /* 23761 */     GIR_EraseRootFromParent_Done,
     /* 23762 */   // Label 722: @23762
     /* 23762 */   GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(23807), // Rule ID 526 //
     /* 23767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
     /* 23775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23792 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23796 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7954:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB),
     /* 23799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23801 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23803 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23805 */     GIR_RootConstrainSelectedInstOperands,
     /* 23806 */     // GIR_Coverage, 526,
     /* 23806 */     GIR_EraseRootFromParent_Done,
     /* 23807 */   // Label 723: @23807
     /* 23807 */   GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(23852), // Rule ID 527 //
     /* 23812 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23815 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
     /* 23820 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23823 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23826 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23833 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23837 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23841 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7955:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23841 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB),
     /* 23844 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23846 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23848 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23850 */     GIR_RootConstrainSelectedInstOperands,
     /* 23851 */     // GIR_Coverage, 527,
     /* 23851 */     GIR_EraseRootFromParent_Done,
     /* 23852 */   // Label 724: @23852
     /* 23852 */   GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(23897), // Rule ID 528 //
     /* 23857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23860 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
     /* 23865 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23868 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23871 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23874 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23878 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23882 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23886 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8577:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23886 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB),
     /* 23889 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23891 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23893 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23895 */     GIR_RootConstrainSelectedInstOperands,
     /* 23896 */     // GIR_Coverage, 528,
     /* 23896 */     GIR_EraseRootFromParent_Done,
     /* 23897 */   // Label 725: @23897
     /* 23897 */   GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(23942), // Rule ID 529 //
     /* 23902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
     /* 23910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 23913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 23916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 23919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23927 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23931 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8578:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 23931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB),
     /* 23934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23936 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23938 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23940 */     GIR_RootConstrainSelectedInstOperands,
     /* 23941 */     // GIR_Coverage, 529,
     /* 23941 */     GIR_EraseRootFromParent_Done,
     /* 23942 */   // Label 726: @23942
     /* 23942 */   GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(23987), // Rule ID 530 //
     /* 23947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
     /* 23955 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 23958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 23961 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 23964 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23968 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23972 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 23976 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7933:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 23976 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH),
     /* 23979 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 23981 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 23983 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 23985 */     GIR_RootConstrainSelectedInstOperands,
     /* 23986 */     // GIR_Coverage, 530,
     /* 23986 */     GIR_EraseRootFromParent_Done,
     /* 23987 */   // Label 727: @23987
     /* 23987 */   GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(24032), // Rule ID 531 //
     /* 23992 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 23995 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
     /* 24000 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 24003 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 24006 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 24009 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24013 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24017 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24021 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7934:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 24021 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH),
     /* 24024 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24026 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24028 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24030 */     GIR_RootConstrainSelectedInstOperands,
     /* 24031 */     // GIR_Coverage, 531,
     /* 24031 */     GIR_EraseRootFromParent_Done,
     /* 24032 */   // Label 728: @24032
     /* 24032 */   GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(24077), // Rule ID 532 //
     /* 24037 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24040 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
     /* 24045 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 24048 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 24051 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 24054 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24058 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24062 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24066 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8553:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 24066 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH),
     /* 24069 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24071 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24073 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24075 */     GIR_RootConstrainSelectedInstOperands,
     /* 24076 */     // GIR_Coverage, 532,
     /* 24076 */     GIR_EraseRootFromParent_Done,
     /* 24077 */   // Label 729: @24077
     /* 24077 */   GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(24122), // Rule ID 533 //
     /* 24082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24085 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
     /* 24090 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 24093 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 24096 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 24099 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24103 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24107 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24111 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8554:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 24111 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH),
     /* 24114 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24116 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24118 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24120 */     GIR_RootConstrainSelectedInstOperands,
     /* 24121 */     // GIR_Coverage, 533,
     /* 24121 */     GIR_EraseRootFromParent_Done,
     /* 24122 */   // Label 730: @24122
     /* 24122 */   GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(24167), // Rule ID 534 //
     /* 24127 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24130 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
     /* 24135 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 24138 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 24141 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24148 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24152 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24156 */     // (intrinsic_wo_chain:{ *:[i32] } 7936:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 24156 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W),
     /* 24159 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24161 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24163 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24165 */     GIR_RootConstrainSelectedInstOperands,
     /* 24166 */     // GIR_Coverage, 534,
     /* 24166 */     GIR_EraseRootFromParent_Done,
     /* 24167 */   // Label 731: @24167
     /* 24167 */   GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(24212), // Rule ID 535 //
     /* 24172 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24175 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
     /* 24180 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 24183 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 24186 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24189 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24197 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24201 */     // (intrinsic_wo_chain:{ *:[i32] } 7935:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 24201 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W),
     /* 24204 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24206 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24208 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24210 */     GIR_RootConstrainSelectedInstOperands,
     /* 24211 */     // GIR_Coverage, 535,
     /* 24211 */     GIR_EraseRootFromParent_Done,
     /* 24212 */   // Label 732: @24212
     /* 24212 */   GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(24257), // Rule ID 536 //
     /* 24217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24220 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
     /* 24225 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 24228 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 24231 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24234 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24238 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24242 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24246 */     // (intrinsic_wo_chain:{ *:[i32] } 8556:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 24246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W),
     /* 24249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24251 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24253 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24255 */     GIR_RootConstrainSelectedInstOperands,
     /* 24256 */     // GIR_Coverage, 536,
     /* 24256 */     GIR_EraseRootFromParent_Done,
     /* 24257 */   // Label 733: @24257
     /* 24257 */   GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(24302), // Rule ID 537 //
     /* 24262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
     /* 24270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 24273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 24276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24283 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24287 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24291 */     // (intrinsic_wo_chain:{ *:[i32] } 8555:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 24291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W),
     /* 24294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24296 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 24298 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 24300 */     GIR_RootConstrainSelectedInstOperands,
     /* 24301 */     // GIR_Coverage, 537,
     /* 24301 */     GIR_EraseRootFromParent_Done,
     /* 24302 */   // Label 734: @24302
     /* 24302 */   GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(24347), // Rule ID 554 //
     /* 24307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24310 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
     /* 24315 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 24318 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 24321 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24328 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24332 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24336 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 24336 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB),
     /* 24339 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24341 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 24343 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 24345 */     GIR_RootConstrainSelectedInstOperands,
     /* 24346 */     // GIR_Coverage, 554,
     /* 24346 */     GIR_EraseRootFromParent_Done,
     /* 24347 */   // Label 735: @24347
     /* 24347 */   GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(24392), // Rule ID 556 //
     /* 24352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
     /* 24360 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 24363 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 24366 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24369 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24373 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24377 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24381 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRAV_R_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 24381 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB),
     /* 24384 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24386 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 24388 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 24390 */     GIR_RootConstrainSelectedInstOperands,
     /* 24391 */     // GIR_Coverage, 556,
     /* 24391 */     GIR_EraseRootFromParent_Done,
     /* 24392 */   // Label 736: @24392
     /* 24392 */   GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(24437), // Rule ID 557 //
     /* 24397 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 24400 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
     /* 24405 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 24408 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 24411 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 24414 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24418 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 24422 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 24426 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHRLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 24426 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH),
     /* 24429 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 24431 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 24433 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 24435 */     GIR_RootConstrainSelectedInstOperands,
     /* 24436 */     // GIR_Coverage, 557,
     /* 24436 */     GIR_EraseRootFromParent_Done,
     /* 24437 */   // Label 737: @24437
     /* 24437 */   GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(24482), // Rule ID 566 //
     /* 24442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24445 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_b),
     /* 24450 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 24453 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 24456 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 24459 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24463 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24467 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24471 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7926:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADD_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 24471 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_B),
     /* 24474 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24476 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24478 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24480 */     GIR_RootConstrainSelectedInstOperands,
     /* 24481 */     // GIR_Coverage, 566,
     /* 24481 */     GIR_EraseRootFromParent_Done,
     /* 24482 */   // Label 738: @24482
     /* 24482 */   GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(24527), // Rule ID 567 //
     /* 24487 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24490 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_h),
     /* 24495 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 24498 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 24501 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 24504 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24508 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24512 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24516 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7928:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADD_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 24516 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_H),
     /* 24519 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24521 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24523 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24525 */     GIR_RootConstrainSelectedInstOperands,
     /* 24526 */     // GIR_Coverage, 567,
     /* 24526 */     GIR_EraseRootFromParent_Done,
     /* 24527 */   // Label 739: @24527
     /* 24527 */   GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(24572), // Rule ID 568 //
     /* 24532 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24535 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_w),
     /* 24540 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 24543 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 24546 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 24549 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24553 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24557 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24561 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7929:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADD_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 24561 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_W),
     /* 24564 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24566 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24568 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24570 */     GIR_RootConstrainSelectedInstOperands,
     /* 24571 */     // GIR_Coverage, 568,
     /* 24571 */     GIR_EraseRootFromParent_Done,
     /* 24572 */   // Label 740: @24572
     /* 24572 */   GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(24617), // Rule ID 569 //
     /* 24577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24580 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_add_a_d),
     /* 24585 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 24588 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 24591 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 24594 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24598 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24602 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24606 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7927:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADD_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 24606 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADD_A_D),
     /* 24609 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24611 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24613 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24615 */     GIR_RootConstrainSelectedInstOperands,
     /* 24616 */     // GIR_Coverage, 569,
     /* 24616 */     GIR_EraseRootFromParent_Done,
     /* 24617 */   // Label 741: @24617
     /* 24617 */   GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(24662), // Rule ID 570 //
     /* 24622 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24625 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_b),
     /* 24630 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 24633 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 24636 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 24639 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24643 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24647 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24651 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7937:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 24651 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_B),
     /* 24654 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24656 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24658 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24660 */     GIR_RootConstrainSelectedInstOperands,
     /* 24661 */     // GIR_Coverage, 570,
     /* 24661 */     GIR_EraseRootFromParent_Done,
     /* 24662 */   // Label 742: @24662
     /* 24662 */   GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(24707), // Rule ID 571 //
     /* 24667 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24670 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_h),
     /* 24675 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 24678 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 24681 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 24684 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24688 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24692 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24696 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7939:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 24696 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_H),
     /* 24699 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24701 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24703 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24705 */     GIR_RootConstrainSelectedInstOperands,
     /* 24706 */     // GIR_Coverage, 571,
     /* 24706 */     GIR_EraseRootFromParent_Done,
     /* 24707 */   // Label 743: @24707
     /* 24707 */   GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(24752), // Rule ID 572 //
     /* 24712 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24715 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_w),
     /* 24720 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 24723 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 24726 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 24729 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24733 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24737 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24741 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7940:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 24741 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_W),
     /* 24744 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24746 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24748 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24750 */     GIR_RootConstrainSelectedInstOperands,
     /* 24751 */     // GIR_Coverage, 572,
     /* 24751 */     GIR_EraseRootFromParent_Done,
     /* 24752 */   // Label 744: @24752
     /* 24752 */   GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(24797), // Rule ID 573 //
     /* 24757 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24760 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_a_d),
     /* 24765 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 24768 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 24771 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 24774 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24778 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24782 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24786 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7938:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 24786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_A_D),
     /* 24789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24791 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24793 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24795 */     GIR_RootConstrainSelectedInstOperands,
     /* 24796 */     // GIR_Coverage, 573,
     /* 24796 */     GIR_EraseRootFromParent_Done,
     /* 24797 */   // Label 745: @24797
     /* 24797 */   GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(24842), // Rule ID 574 //
     /* 24802 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24805 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_b),
     /* 24810 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 24813 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 24816 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 24819 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24823 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24827 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 24831 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7941:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 24831 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_B),
     /* 24834 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24836 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24838 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24840 */     GIR_RootConstrainSelectedInstOperands,
     /* 24841 */     // GIR_Coverage, 574,
     /* 24841 */     GIR_EraseRootFromParent_Done,
     /* 24842 */   // Label 746: @24842
     /* 24842 */   GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(24887), // Rule ID 575 //
     /* 24847 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24850 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_h),
     /* 24855 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 24858 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 24861 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 24864 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24868 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24872 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 24876 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7943:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 24876 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_H),
     /* 24879 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24881 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24883 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24885 */     GIR_RootConstrainSelectedInstOperands,
     /* 24886 */     // GIR_Coverage, 575,
     /* 24886 */     GIR_EraseRootFromParent_Done,
     /* 24887 */   // Label 747: @24887
     /* 24887 */   GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(24932), // Rule ID 576 //
     /* 24892 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24895 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_w),
     /* 24900 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 24903 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 24906 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 24909 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24913 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24917 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 24921 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7944:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 24921 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_W),
     /* 24924 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24926 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24928 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24930 */     GIR_RootConstrainSelectedInstOperands,
     /* 24931 */     // GIR_Coverage, 576,
     /* 24931 */     GIR_EraseRootFromParent_Done,
     /* 24932 */   // Label 748: @24932
     /* 24932 */   GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(24977), // Rule ID 577 //
     /* 24937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24940 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_s_d),
     /* 24945 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 24948 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 24951 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 24954 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24958 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24962 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 24966 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7942:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 24966 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_S_D),
     /* 24969 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 24971 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 24973 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 24975 */     GIR_RootConstrainSelectedInstOperands,
     /* 24976 */     // GIR_Coverage, 577,
     /* 24976 */     GIR_EraseRootFromParent_Done,
     /* 24977 */   // Label 749: @24977
     /* 24977 */   GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(25022), // Rule ID 578 //
     /* 24982 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 24985 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_b),
     /* 24990 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 24993 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 24996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 24999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25003 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25007 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25011 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7945:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ADDS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25011 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_B),
     /* 25014 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25016 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25018 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25020 */     GIR_RootConstrainSelectedInstOperands,
     /* 25021 */     // GIR_Coverage, 578,
     /* 25021 */     GIR_EraseRootFromParent_Done,
     /* 25022 */   // Label 750: @25022
     /* 25022 */   GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(25067), // Rule ID 579 //
     /* 25027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_h),
     /* 25035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25041 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25048 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25052 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25056 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7947:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ADDS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_H),
     /* 25059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25061 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25063 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25065 */     GIR_RootConstrainSelectedInstOperands,
     /* 25066 */     // GIR_Coverage, 579,
     /* 25066 */     GIR_EraseRootFromParent_Done,
     /* 25067 */   // Label 751: @25067
     /* 25067 */   GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(25112), // Rule ID 580 //
     /* 25072 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25075 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_w),
     /* 25080 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25083 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25086 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25089 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25093 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25097 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25101 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7948:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ADDS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 25101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_W),
     /* 25104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25106 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25108 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25110 */     GIR_RootConstrainSelectedInstOperands,
     /* 25111 */     // GIR_Coverage, 580,
     /* 25111 */     GIR_EraseRootFromParent_Done,
     /* 25112 */   // Label 752: @25112
     /* 25112 */   GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(25157), // Rule ID 581 //
     /* 25117 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25120 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adds_u_d),
     /* 25125 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 25128 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 25131 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 25134 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25138 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25142 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25146 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7946:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ADDS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 25146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDS_U_D),
     /* 25149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25151 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25153 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25155 */     GIR_RootConstrainSelectedInstOperands,
     /* 25156 */     // GIR_Coverage, 581,
     /* 25156 */     GIR_EraseRootFromParent_Done,
     /* 25157 */   // Label 753: @25157
     /* 25157 */   GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(25202), // Rule ID 595 //
     /* 25162 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25165 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_b),
     /* 25170 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 25173 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 25176 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 25179 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25183 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25187 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25191 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7968:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25191 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_B),
     /* 25194 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25196 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25198 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25200 */     GIR_RootConstrainSelectedInstOperands,
     /* 25201 */     // GIR_Coverage, 595,
     /* 25201 */     GIR_EraseRootFromParent_Done,
     /* 25202 */   // Label 754: @25202
     /* 25202 */   GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(25247), // Rule ID 596 //
     /* 25207 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25210 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_h),
     /* 25215 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25218 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25221 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25224 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25228 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25232 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25236 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7970:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25236 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_H),
     /* 25239 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25241 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25243 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25245 */     GIR_RootConstrainSelectedInstOperands,
     /* 25246 */     // GIR_Coverage, 596,
     /* 25246 */     GIR_EraseRootFromParent_Done,
     /* 25247 */   // Label 755: @25247
     /* 25247 */   GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(25292), // Rule ID 597 //
     /* 25252 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25255 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_w),
     /* 25260 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25263 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25266 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25269 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25273 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25277 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25281 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7971:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 25281 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_W),
     /* 25284 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25286 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25288 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25290 */     GIR_RootConstrainSelectedInstOperands,
     /* 25291 */     // GIR_Coverage, 597,
     /* 25291 */     GIR_EraseRootFromParent_Done,
     /* 25292 */   // Label 756: @25292
     /* 25292 */   GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(25337), // Rule ID 598 //
     /* 25297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25300 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_s_d),
     /* 25305 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 25308 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 25311 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 25314 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25318 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25322 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25326 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7969:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 25326 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_S_D),
     /* 25329 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25331 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25333 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25335 */     GIR_RootConstrainSelectedInstOperands,
     /* 25336 */     // GIR_Coverage, 598,
     /* 25336 */     GIR_EraseRootFromParent_Done,
     /* 25337 */   // Label 757: @25337
     /* 25337 */   GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(25382), // Rule ID 599 //
     /* 25342 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25345 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_b),
     /* 25350 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 25353 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 25356 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 25359 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25363 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25367 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25371 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7972:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (ASUB_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25371 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_B),
     /* 25374 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25376 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25378 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25380 */     GIR_RootConstrainSelectedInstOperands,
     /* 25381 */     // GIR_Coverage, 599,
     /* 25381 */     GIR_EraseRootFromParent_Done,
     /* 25382 */   // Label 758: @25382
     /* 25382 */   GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(25427), // Rule ID 600 //
     /* 25387 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25390 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_h),
     /* 25395 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25398 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25401 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25404 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25412 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25416 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7974:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (ASUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_H),
     /* 25419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25421 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25423 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25425 */     GIR_RootConstrainSelectedInstOperands,
     /* 25426 */     // GIR_Coverage, 600,
     /* 25426 */     GIR_EraseRootFromParent_Done,
     /* 25427 */   // Label 759: @25427
     /* 25427 */   GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(25472), // Rule ID 601 //
     /* 25432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25435 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_w),
     /* 25440 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25443 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25446 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25449 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25453 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25457 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25461 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7975:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (ASUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 25461 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_W),
     /* 25464 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25466 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25468 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25470 */     GIR_RootConstrainSelectedInstOperands,
     /* 25471 */     // GIR_Coverage, 601,
     /* 25471 */     GIR_EraseRootFromParent_Done,
     /* 25472 */   // Label 760: @25472
     /* 25472 */   GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(25517), // Rule ID 602 //
     /* 25477 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25480 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_asub_u_d),
     /* 25485 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 25488 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 25491 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 25494 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25498 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25502 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25506 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7973:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (ASUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 25506 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ASUB_U_D),
     /* 25509 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25511 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25513 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25515 */     GIR_RootConstrainSelectedInstOperands,
     /* 25516 */     // GIR_Coverage, 602,
     /* 25516 */     GIR_EraseRootFromParent_Done,
     /* 25517 */   // Label 761: @25517
     /* 25517 */   GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(25562), // Rule ID 603 //
     /* 25522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25525 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_b),
     /* 25530 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 25533 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 25536 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 25539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25547 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25551 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7976:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25551 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_B),
     /* 25554 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25556 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25558 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25560 */     GIR_RootConstrainSelectedInstOperands,
     /* 25561 */     // GIR_Coverage, 603,
     /* 25561 */     GIR_EraseRootFromParent_Done,
     /* 25562 */   // Label 762: @25562
     /* 25562 */   GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(25607), // Rule ID 604 //
     /* 25567 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25570 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_h),
     /* 25575 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25578 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25581 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25584 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25588 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25592 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25596 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7978:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25596 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_H),
     /* 25599 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25601 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25603 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25605 */     GIR_RootConstrainSelectedInstOperands,
     /* 25606 */     // GIR_Coverage, 604,
     /* 25606 */     GIR_EraseRootFromParent_Done,
     /* 25607 */   // Label 763: @25607
     /* 25607 */   GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(25652), // Rule ID 605 //
     /* 25612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25615 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_w),
     /* 25620 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25629 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25633 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25637 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25641 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7979:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 25641 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_W),
     /* 25644 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25646 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25648 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25650 */     GIR_RootConstrainSelectedInstOperands,
     /* 25651 */     // GIR_Coverage, 605,
     /* 25651 */     GIR_EraseRootFromParent_Done,
     /* 25652 */   // Label 764: @25652
     /* 25652 */   GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(25697), // Rule ID 606 //
     /* 25657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25660 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_s_d),
     /* 25665 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 25668 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 25671 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 25674 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25678 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25682 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25686 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7977:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 25686 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_S_D),
     /* 25689 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25691 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25693 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25695 */     GIR_RootConstrainSelectedInstOperands,
     /* 25696 */     // GIR_Coverage, 606,
     /* 25696 */     GIR_EraseRootFromParent_Done,
     /* 25697 */   // Label 765: @25697
     /* 25697 */   GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(25742), // Rule ID 607 //
     /* 25702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25705 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_b),
     /* 25710 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 25713 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 25716 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 25719 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25723 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25727 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25731 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7980:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVE_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25731 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_B),
     /* 25734 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25736 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25738 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25740 */     GIR_RootConstrainSelectedInstOperands,
     /* 25741 */     // GIR_Coverage, 607,
     /* 25741 */     GIR_EraseRootFromParent_Done,
     /* 25742 */   // Label 766: @25742
     /* 25742 */   GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(25787), // Rule ID 608 //
     /* 25747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25750 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_h),
     /* 25755 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25758 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25761 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25764 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25768 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25772 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25776 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7982:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVE_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25776 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_H),
     /* 25779 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25781 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25783 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25785 */     GIR_RootConstrainSelectedInstOperands,
     /* 25786 */     // GIR_Coverage, 608,
     /* 25786 */     GIR_EraseRootFromParent_Done,
     /* 25787 */   // Label 767: @25787
     /* 25787 */   GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(25832), // Rule ID 609 //
     /* 25792 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25795 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_w),
     /* 25800 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25803 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25806 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25813 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25817 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25821 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7983:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVE_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 25821 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_W),
     /* 25824 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25826 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25828 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25830 */     GIR_RootConstrainSelectedInstOperands,
     /* 25831 */     // GIR_Coverage, 609,
     /* 25831 */     GIR_EraseRootFromParent_Done,
     /* 25832 */   // Label 768: @25832
     /* 25832 */   GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(25877), // Rule ID 610 //
     /* 25837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25840 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ave_u_d),
     /* 25845 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 25848 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 25851 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 25854 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25858 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25862 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 25866 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7981:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVE_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 25866 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVE_U_D),
     /* 25869 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25871 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25873 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25875 */     GIR_RootConstrainSelectedInstOperands,
     /* 25876 */     // GIR_Coverage, 610,
     /* 25876 */     GIR_EraseRootFromParent_Done,
     /* 25877 */   // Label 769: @25877
     /* 25877 */   GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(25922), // Rule ID 611 //
     /* 25882 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25885 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_b),
     /* 25890 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 25893 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 25896 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 25899 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25903 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25907 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 25911 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7984:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 25911 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_B),
     /* 25914 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25916 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25918 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25920 */     GIR_RootConstrainSelectedInstOperands,
     /* 25921 */     // GIR_Coverage, 611,
     /* 25921 */     GIR_EraseRootFromParent_Done,
     /* 25922 */   // Label 770: @25922
     /* 25922 */   GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(25967), // Rule ID 612 //
     /* 25927 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25930 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_h),
     /* 25935 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 25938 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 25941 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 25944 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25948 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25952 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 25956 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7986:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 25956 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_H),
     /* 25959 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 25961 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 25963 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 25965 */     GIR_RootConstrainSelectedInstOperands,
     /* 25966 */     // GIR_Coverage, 612,
     /* 25966 */     GIR_EraseRootFromParent_Done,
     /* 25967 */   // Label 771: @25967
     /* 25967 */   GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(26012), // Rule ID 613 //
     /* 25972 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 25975 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_w),
     /* 25980 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 25983 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 25986 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 25989 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25993 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 25997 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26001 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7987:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 26001 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_W),
     /* 26004 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26006 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26008 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26010 */     GIR_RootConstrainSelectedInstOperands,
     /* 26011 */     // GIR_Coverage, 613,
     /* 26011 */     GIR_EraseRootFromParent_Done,
     /* 26012 */   // Label 772: @26012
     /* 26012 */   GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(26057), // Rule ID 614 //
     /* 26017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26020 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_s_d),
     /* 26025 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26028 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26031 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26034 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26038 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26042 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26046 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7985:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 26046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_S_D),
     /* 26049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26051 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26053 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26055 */     GIR_RootConstrainSelectedInstOperands,
     /* 26056 */     // GIR_Coverage, 614,
     /* 26056 */     GIR_EraseRootFromParent_Done,
     /* 26057 */   // Label 773: @26057
     /* 26057 */   GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(26102), // Rule ID 615 //
     /* 26062 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26065 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_b),
     /* 26070 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 26073 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 26076 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 26079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26087 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26091 */     // (intrinsic_wo_chain:{ *:[v16i8] } 7988:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (AVER_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 26091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_B),
     /* 26094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26096 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26098 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26100 */     GIR_RootConstrainSelectedInstOperands,
     /* 26101 */     // GIR_Coverage, 615,
     /* 26101 */     GIR_EraseRootFromParent_Done,
     /* 26102 */   // Label 774: @26102
     /* 26102 */   GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(26147), // Rule ID 616 //
     /* 26107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26110 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_h),
     /* 26115 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 26118 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 26121 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 26124 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26128 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26132 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26136 */     // (intrinsic_wo_chain:{ *:[v8i16] } 7990:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (AVER_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 26136 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_H),
     /* 26139 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26141 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26143 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26145 */     GIR_RootConstrainSelectedInstOperands,
     /* 26146 */     // GIR_Coverage, 616,
     /* 26146 */     GIR_EraseRootFromParent_Done,
     /* 26147 */   // Label 775: @26147
     /* 26147 */   GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(26192), // Rule ID 617 //
     /* 26152 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26155 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_w),
     /* 26160 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26163 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26166 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26169 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26173 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26177 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26181 */     // (intrinsic_wo_chain:{ *:[v4i32] } 7991:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (AVER_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 26181 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_W),
     /* 26184 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26186 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26188 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26190 */     GIR_RootConstrainSelectedInstOperands,
     /* 26191 */     // GIR_Coverage, 617,
     /* 26191 */     GIR_EraseRootFromParent_Done,
     /* 26192 */   // Label 776: @26192
     /* 26192 */   GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(26237), // Rule ID 618 //
     /* 26197 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26200 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_aver_u_d),
     /* 26205 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26208 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26211 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26214 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26218 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26222 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26226 */     // (intrinsic_wo_chain:{ *:[v2i64] } 7989:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (AVER_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 26226 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::AVER_U_D),
     /* 26229 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26231 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26233 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26235 */     GIR_RootConstrainSelectedInstOperands,
     /* 26236 */     // GIR_Coverage, 618,
     /* 26236 */     GIR_EraseRootFromParent_Done,
     /* 26237 */   // Label 777: @26237
     /* 26237 */   GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(26282), // Rule ID 727 //
     /* 26242 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26245 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_h),
     /* 26250 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 26253 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 26256 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 26259 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26263 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26267 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26271 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8123:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 26271 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_H),
     /* 26274 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26276 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26278 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26280 */     GIR_RootConstrainSelectedInstOperands,
     /* 26281 */     // GIR_Coverage, 727,
     /* 26281 */     GIR_EraseRootFromParent_Done,
     /* 26282 */   // Label 778: @26282
     /* 26282 */   GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(26327), // Rule ID 728 //
     /* 26287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26290 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_w),
     /* 26295 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26298 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 26301 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 26304 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26308 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26312 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26316 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8124:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 26316 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_W),
     /* 26319 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26321 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26323 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26325 */     GIR_RootConstrainSelectedInstOperands,
     /* 26326 */     // GIR_Coverage, 728,
     /* 26326 */     GIR_EraseRootFromParent_Done,
     /* 26327 */   // Label 779: @26327
     /* 26327 */   GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(26372), // Rule ID 729 //
     /* 26332 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26335 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_s_d),
     /* 26340 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26343 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26346 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26353 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26357 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26361 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8122:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 26361 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_S_D),
     /* 26364 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26366 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26368 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26370 */     GIR_RootConstrainSelectedInstOperands,
     /* 26371 */     // GIR_Coverage, 729,
     /* 26371 */     GIR_EraseRootFromParent_Done,
     /* 26372 */   // Label 780: @26372
     /* 26372 */   GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(26417), // Rule ID 730 //
     /* 26377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26380 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_h),
     /* 26385 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 26388 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 26391 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 26394 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26398 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26402 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 26406 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8126:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DOTP_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 26406 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_H),
     /* 26409 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26411 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26413 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26415 */     GIR_RootConstrainSelectedInstOperands,
     /* 26416 */     // GIR_Coverage, 730,
     /* 26416 */     GIR_EraseRootFromParent_Done,
     /* 26417 */   // Label 781: @26417
     /* 26417 */   GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(26462), // Rule ID 731 //
     /* 26422 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26425 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_w),
     /* 26430 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26433 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 26436 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 26439 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26443 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26447 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26451 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8127:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DOTP_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 26451 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_W),
     /* 26454 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26456 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26458 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26460 */     GIR_RootConstrainSelectedInstOperands,
     /* 26461 */     // GIR_Coverage, 731,
     /* 26461 */     GIR_EraseRootFromParent_Done,
     /* 26462 */   // Label 782: @26462
     /* 26462 */   GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(26507), // Rule ID 732 //
     /* 26467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26470 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dotp_u_d),
     /* 26475 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26478 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26481 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26484 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26492 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26496 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8125:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DOTP_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 26496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DOTP_U_D),
     /* 26499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26501 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26503 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26505 */     GIR_RootConstrainSelectedInstOperands,
     /* 26506 */     // GIR_Coverage, 732,
     /* 26506 */     GIR_EraseRootFromParent_Done,
     /* 26507 */   // Label 783: @26507
     /* 26507 */   GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(26552), // Rule ID 747 //
     /* 26512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26515 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_w),
     /* 26520 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26523 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26526 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26529 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26533 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26537 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26541 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8165:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FCAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26541 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_W),
     /* 26544 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26546 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26548 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26550 */     GIR_RootConstrainSelectedInstOperands,
     /* 26551 */     // GIR_Coverage, 747,
     /* 26551 */     GIR_EraseRootFromParent_Done,
     /* 26552 */   // Label 784: @26552
     /* 26552 */   GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(26597), // Rule ID 748 //
     /* 26557 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26560 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fcaf_d),
     /* 26565 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26568 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26571 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26578 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26582 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26586 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8164:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FCAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 26586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FCAF_D),
     /* 26589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26591 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26593 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26595 */     GIR_RootConstrainSelectedInstOperands,
     /* 26596 */     // GIR_Coverage, 748,
     /* 26596 */     GIR_EraseRootFromParent_Done,
     /* 26597 */   // Label 785: @26597
     /* 26597 */   GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(26642), // Rule ID 773 //
     /* 26602 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26605 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_h),
     /* 26610 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 26613 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26616 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 26623 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26627 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26631 */     // (intrinsic_wo_chain:{ *:[v8f16] } 8190:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FEXDO_H:{ *:[v8f16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_H),
     /* 26634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26636 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26638 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26640 */     GIR_RootConstrainSelectedInstOperands,
     /* 26641 */     // GIR_Coverage, 773,
     /* 26641 */     GIR_EraseRootFromParent_Done,
     /* 26642 */   // Label 786: @26642
     /* 26642 */   GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(26687), // Rule ID 774 //
     /* 26647 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26650 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fexdo_w),
     /* 26655 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26658 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26661 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26664 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26668 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26672 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26676 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8191:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FEXDO_W:{ *:[v4f32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 26676 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXDO_W),
     /* 26679 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26681 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26683 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26685 */     GIR_RootConstrainSelectedInstOperands,
     /* 26686 */     // GIR_Coverage, 774,
     /* 26686 */     GIR_EraseRootFromParent_Done,
     /* 26687 */   // Label 787: @26687
     /* 26687 */   GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(26732), // Rule ID 801 //
     /* 26692 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26695 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_w),
     /* 26700 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26703 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26706 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26709 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26713 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26717 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26721 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8217:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26721 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_W),
     /* 26724 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26726 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26728 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26730 */     GIR_RootConstrainSelectedInstOperands,
     /* 26731 */     // GIR_Coverage, 801,
     /* 26731 */     GIR_EraseRootFromParent_Done,
     /* 26732 */   // Label 788: @26732
     /* 26732 */   GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(26777), // Rule ID 802 //
     /* 26737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26740 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_d),
     /* 26745 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26748 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26751 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26754 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26758 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26762 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26766 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8216:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 26766 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_D),
     /* 26769 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26771 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26773 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26775 */     GIR_RootConstrainSelectedInstOperands,
     /* 26776 */     // GIR_Coverage, 802,
     /* 26776 */     GIR_EraseRootFromParent_Done,
     /* 26777 */   // Label 789: @26777
     /* 26777 */   GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(26822), // Rule ID 803 //
     /* 26782 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26785 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_w),
     /* 26790 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26793 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26796 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26799 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26803 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26807 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26811 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8215:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMAX_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26811 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_W),
     /* 26814 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26816 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26818 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26820 */     GIR_RootConstrainSelectedInstOperands,
     /* 26821 */     // GIR_Coverage, 803,
     /* 26821 */     GIR_EraseRootFromParent_Done,
     /* 26822 */   // Label 790: @26822
     /* 26822 */   GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(26867), // Rule ID 804 //
     /* 26827 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26830 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmax_a_d),
     /* 26835 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26838 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26841 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26844 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26848 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26852 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26856 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8214:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMAX_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 26856 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMAX_A_D),
     /* 26859 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26861 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26863 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26865 */     GIR_RootConstrainSelectedInstOperands,
     /* 26866 */     // GIR_Coverage, 804,
     /* 26866 */     GIR_EraseRootFromParent_Done,
     /* 26867 */   // Label 791: @26867
     /* 26867 */   GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(26912), // Rule ID 805 //
     /* 26872 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26875 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_w),
     /* 26880 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26883 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26886 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26901 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8221:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_W),
     /* 26904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26906 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26908 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26910 */     GIR_RootConstrainSelectedInstOperands,
     /* 26911 */     // GIR_Coverage, 805,
     /* 26911 */     GIR_EraseRootFromParent_Done,
     /* 26912 */   // Label 792: @26912
     /* 26912 */   GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(26957), // Rule ID 806 //
     /* 26917 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26920 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_d),
     /* 26925 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 26928 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 26931 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 26934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26938 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26942 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 26946 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8220:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 26946 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_D),
     /* 26949 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26951 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26953 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 26955 */     GIR_RootConstrainSelectedInstOperands,
     /* 26956 */     // GIR_Coverage, 806,
     /* 26956 */     GIR_EraseRootFromParent_Done,
     /* 26957 */   // Label 793: @26957
     /* 26957 */   GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(27002), // Rule ID 807 //
     /* 26962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 26965 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_w),
     /* 26970 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 26973 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 26976 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 26979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26983 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26987 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 26991 */     // (intrinsic_wo_chain:{ *:[v4f32] } 8219:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMIN_A_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 26991 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_W),
     /* 26994 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 26996 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 26998 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27000 */     GIR_RootConstrainSelectedInstOperands,
     /* 27001 */     // GIR_Coverage, 807,
     /* 27001 */     GIR_EraseRootFromParent_Done,
     /* 27002 */   // Label 794: @27002
     /* 27002 */   GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(27047), // Rule ID 808 //
     /* 27007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27010 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fmin_a_d),
     /* 27015 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27018 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27021 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27024 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27028 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27032 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27036 */     // (intrinsic_wo_chain:{ *:[v2f64] } 8218:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMIN_A_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27036 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMIN_A_D),
     /* 27039 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27041 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27043 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27045 */     GIR_RootConstrainSelectedInstOperands,
     /* 27046 */     // GIR_Coverage, 808,
     /* 27046 */     GIR_EraseRootFromParent_Done,
     /* 27047 */   // Label 795: @27047
     /* 27047 */   GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(27092), // Rule ID 819 //
     /* 27052 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27055 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_w),
     /* 27060 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27063 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27066 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27069 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27073 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27077 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27081 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8233:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSAF_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27081 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_W),
     /* 27084 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27086 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27088 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27090 */     GIR_RootConstrainSelectedInstOperands,
     /* 27091 */     // GIR_Coverage, 819,
     /* 27091 */     GIR_EraseRootFromParent_Done,
     /* 27092 */   // Label 796: @27092
     /* 27092 */   GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(27137), // Rule ID 820 //
     /* 27097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27100 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsaf_d),
     /* 27105 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27108 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27111 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27114 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27118 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27122 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27126 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8232:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSAF_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27126 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSAF_D),
     /* 27129 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27131 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27133 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27135 */     GIR_RootConstrainSelectedInstOperands,
     /* 27136 */     // GIR_Coverage, 820,
     /* 27136 */     GIR_EraseRootFromParent_Done,
     /* 27137 */   // Label 797: @27137
     /* 27137 */   GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(27182), // Rule ID 821 //
     /* 27142 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27145 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_w),
     /* 27150 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27153 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27156 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27163 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27167 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27171 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8235:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27171 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_W),
     /* 27174 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27176 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27178 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27180 */     GIR_RootConstrainSelectedInstOperands,
     /* 27181 */     // GIR_Coverage, 821,
     /* 27181 */     GIR_EraseRootFromParent_Done,
     /* 27182 */   // Label 798: @27182
     /* 27182 */   GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(27227), // Rule ID 822 //
     /* 27187 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27190 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fseq_d),
     /* 27195 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27198 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27201 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27204 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27208 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27212 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27216 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8234:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27216 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSEQ_D),
     /* 27219 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27221 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27223 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27225 */     GIR_RootConstrainSelectedInstOperands,
     /* 27226 */     // GIR_Coverage, 822,
     /* 27226 */     GIR_EraseRootFromParent_Done,
     /* 27227 */   // Label 799: @27227
     /* 27227 */   GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(27272), // Rule ID 823 //
     /* 27232 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27235 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_w),
     /* 27240 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27243 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27246 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27249 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27253 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27257 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27261 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8237:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27261 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_W),
     /* 27264 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27266 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27268 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27270 */     GIR_RootConstrainSelectedInstOperands,
     /* 27271 */     // GIR_Coverage, 823,
     /* 27271 */     GIR_EraseRootFromParent_Done,
     /* 27272 */   // Label 800: @27272
     /* 27272 */   GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(27317), // Rule ID 824 //
     /* 27277 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27280 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsle_d),
     /* 27285 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27288 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27291 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27294 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27298 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27302 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27306 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8236:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27306 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLE_D),
     /* 27309 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27311 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27313 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27315 */     GIR_RootConstrainSelectedInstOperands,
     /* 27316 */     // GIR_Coverage, 824,
     /* 27316 */     GIR_EraseRootFromParent_Done,
     /* 27317 */   // Label 801: @27317
     /* 27317 */   GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(27362), // Rule ID 825 //
     /* 27322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27325 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_w),
     /* 27330 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27333 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27336 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27339 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27343 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27347 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27351 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8239:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSLT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27351 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_W),
     /* 27354 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27356 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27358 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27360 */     GIR_RootConstrainSelectedInstOperands,
     /* 27361 */     // GIR_Coverage, 825,
     /* 27361 */     GIR_EraseRootFromParent_Done,
     /* 27362 */   // Label 802: @27362
     /* 27362 */   GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(27407), // Rule ID 826 //
     /* 27367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27370 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fslt_d),
     /* 27375 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27378 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27381 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27388 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27392 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27396 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8238:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSLT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27396 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSLT_D),
     /* 27399 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27401 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27403 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27405 */     GIR_RootConstrainSelectedInstOperands,
     /* 27406 */     // GIR_Coverage, 826,
     /* 27406 */     GIR_EraseRootFromParent_Done,
     /* 27407 */   // Label 803: @27407
     /* 27407 */   GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(27452), // Rule ID 827 //
     /* 27412 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27415 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_w),
     /* 27420 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27423 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27426 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27429 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27433 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27437 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27441 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8241:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27441 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_W),
     /* 27444 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27446 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27448 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27450 */     GIR_RootConstrainSelectedInstOperands,
     /* 27451 */     // GIR_Coverage, 827,
     /* 27451 */     GIR_EraseRootFromParent_Done,
     /* 27452 */   // Label 804: @27452
     /* 27452 */   GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(27497), // Rule ID 828 //
     /* 27457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27460 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsne_d),
     /* 27465 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27468 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27471 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27478 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27482 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27486 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8240:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27486 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSNE_D),
     /* 27489 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27491 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27493 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27495 */     GIR_RootConstrainSelectedInstOperands,
     /* 27496 */     // GIR_Coverage, 828,
     /* 27496 */     GIR_EraseRootFromParent_Done,
     /* 27497 */   // Label 805: @27497
     /* 27497 */   GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(27542), // Rule ID 829 //
     /* 27502 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27505 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_w),
     /* 27510 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27513 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27516 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27519 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27527 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27531 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8243:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSOR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27531 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_W),
     /* 27534 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27536 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27538 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27540 */     GIR_RootConstrainSelectedInstOperands,
     /* 27541 */     // GIR_Coverage, 829,
     /* 27541 */     GIR_EraseRootFromParent_Done,
     /* 27542 */   // Label 806: @27542
     /* 27542 */   GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(27587), // Rule ID 830 //
     /* 27547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27550 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsor_d),
     /* 27555 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27558 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27561 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27564 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27568 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27572 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27576 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8242:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSOR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27576 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSOR_D),
     /* 27579 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27581 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27583 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27585 */     GIR_RootConstrainSelectedInstOperands,
     /* 27586 */     // GIR_Coverage, 830,
     /* 27586 */     GIR_EraseRootFromParent_Done,
     /* 27587 */   // Label 807: @27587
     /* 27587 */   GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(27632), // Rule ID 835 //
     /* 27592 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27595 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_w),
     /* 27600 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27603 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27606 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27609 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27613 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27617 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27621 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8249:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUEQ_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_W),
     /* 27624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27626 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27628 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27630 */     GIR_RootConstrainSelectedInstOperands,
     /* 27631 */     // GIR_Coverage, 835,
     /* 27631 */     GIR_EraseRootFromParent_Done,
     /* 27632 */   // Label 808: @27632
     /* 27632 */   GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(27677), // Rule ID 836 //
     /* 27637 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27640 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsueq_d),
     /* 27645 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27648 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27651 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27654 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27658 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27662 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27666 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8248:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUEQ_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUEQ_D),
     /* 27669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27671 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27673 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27675 */     GIR_RootConstrainSelectedInstOperands,
     /* 27676 */     // GIR_Coverage, 836,
     /* 27676 */     GIR_EraseRootFromParent_Done,
     /* 27677 */   // Label 809: @27677
     /* 27677 */   GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(27722), // Rule ID 837 //
     /* 27682 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27685 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_w),
     /* 27690 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27693 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27696 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27699 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27703 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27707 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27711 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8251:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_W),
     /* 27714 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27716 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27718 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27720 */     GIR_RootConstrainSelectedInstOperands,
     /* 27721 */     // GIR_Coverage, 837,
     /* 27721 */     GIR_EraseRootFromParent_Done,
     /* 27722 */   // Label 810: @27722
     /* 27722 */   GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(27767), // Rule ID 838 //
     /* 27727 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27730 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsule_d),
     /* 27735 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27738 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27741 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27744 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27748 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27752 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27756 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8250:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27756 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULE_D),
     /* 27759 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27761 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27763 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27765 */     GIR_RootConstrainSelectedInstOperands,
     /* 27766 */     // GIR_Coverage, 838,
     /* 27766 */     GIR_EraseRootFromParent_Done,
     /* 27767 */   // Label 811: @27767
     /* 27767 */   GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(27812), // Rule ID 839 //
     /* 27772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27775 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_w),
     /* 27780 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27783 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27786 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27789 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27797 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27801 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8253:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSULT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27801 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_W),
     /* 27804 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27806 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27808 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27810 */     GIR_RootConstrainSelectedInstOperands,
     /* 27811 */     // GIR_Coverage, 839,
     /* 27811 */     GIR_EraseRootFromParent_Done,
     /* 27812 */   // Label 812: @27812
     /* 27812 */   GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(27857), // Rule ID 840 //
     /* 27817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27820 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsult_d),
     /* 27825 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27828 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27831 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27834 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27838 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27842 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27846 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8252:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSULT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27846 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSULT_D),
     /* 27849 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27851 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27853 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27855 */     GIR_RootConstrainSelectedInstOperands,
     /* 27856 */     // GIR_Coverage, 840,
     /* 27856 */     GIR_EraseRootFromParent_Done,
     /* 27857 */   // Label 813: @27857
     /* 27857 */   GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(27902), // Rule ID 841 //
     /* 27862 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27865 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_w),
     /* 27870 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27873 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27876 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27879 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27883 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27887 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27891 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8255:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUN_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27891 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_W),
     /* 27894 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27896 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27898 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27900 */     GIR_RootConstrainSelectedInstOperands,
     /* 27901 */     // GIR_Coverage, 841,
     /* 27901 */     GIR_EraseRootFromParent_Done,
     /* 27902 */   // Label 814: @27902
     /* 27902 */   GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(27947), // Rule ID 842 //
     /* 27907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27910 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsun_d),
     /* 27915 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 27918 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 27921 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 27924 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27928 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27932 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 27936 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8254:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUN_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 27936 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUN_D),
     /* 27939 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27941 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27943 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27945 */     GIR_RootConstrainSelectedInstOperands,
     /* 27946 */     // GIR_Coverage, 842,
     /* 27946 */     GIR_EraseRootFromParent_Done,
     /* 27947 */   // Label 815: @27947
     /* 27947 */   GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(27992), // Rule ID 843 //
     /* 27952 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 27955 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_w),
     /* 27960 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 27963 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 27966 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 27969 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27977 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 27981 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8257:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUNE_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 27981 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_W),
     /* 27984 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 27986 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 27988 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 27990 */     GIR_RootConstrainSelectedInstOperands,
     /* 27991 */     // GIR_Coverage, 843,
     /* 27991 */     GIR_EraseRootFromParent_Done,
     /* 27992 */   // Label 816: @27992
     /* 27992 */   GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(28037), // Rule ID 844 //
     /* 27997 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28000 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_fsune_d),
     /* 28005 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28008 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 28011 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 28014 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28018 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28022 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28026 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8256:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUNE_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 28026 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUNE_D),
     /* 28029 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28031 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28033 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28035 */     GIR_RootConstrainSelectedInstOperands,
     /* 28036 */     // GIR_Coverage, 844,
     /* 28036 */     GIR_EraseRootFromParent_Done,
     /* 28037 */   // Label 817: @28037
     /* 28037 */   GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(28082), // Rule ID 849 //
     /* 28042 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28045 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_h),
     /* 28050 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28053 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28056 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28059 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28063 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28067 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28071 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8262:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FTQ_H:{ *:[v8i16] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 28071 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_H),
     /* 28074 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28076 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28078 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28080 */     GIR_RootConstrainSelectedInstOperands,
     /* 28081 */     // GIR_Coverage, 849,
     /* 28081 */     GIR_EraseRootFromParent_Done,
     /* 28082 */   // Label 818: @28082
     /* 28082 */   GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(28127), // Rule ID 850 //
     /* 28087 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28090 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ftq_w),
     /* 28095 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28098 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 28101 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 28104 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28108 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28112 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28116 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8263:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FTQ_W:{ *:[v4i32] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 28116 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FTQ_W),
     /* 28119 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28121 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28123 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28125 */     GIR_RootConstrainSelectedInstOperands,
     /* 28126 */     // GIR_Coverage, 850,
     /* 28126 */     GIR_EraseRootFromParent_Done,
     /* 28127 */   // Label 819: @28127
     /* 28127 */   GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(28172), // Rule ID 855 //
     /* 28132 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28135 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_h),
     /* 28140 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28143 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28146 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28149 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28153 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28157 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28161 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8269:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28161 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_H),
     /* 28164 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28166 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28168 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28170 */     GIR_RootConstrainSelectedInstOperands,
     /* 28171 */     // GIR_Coverage, 855,
     /* 28171 */     GIR_EraseRootFromParent_Done,
     /* 28172 */   // Label 820: @28172
     /* 28172 */   GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(28217), // Rule ID 856 //
     /* 28177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28180 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_w),
     /* 28185 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28188 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28191 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28194 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28198 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28202 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28206 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8270:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28206 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_W),
     /* 28209 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28211 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28213 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28215 */     GIR_RootConstrainSelectedInstOperands,
     /* 28216 */     // GIR_Coverage, 856,
     /* 28216 */     GIR_EraseRootFromParent_Done,
     /* 28217 */   // Label 821: @28217
     /* 28217 */   GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(28262), // Rule ID 857 //
     /* 28222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28225 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_s_d),
     /* 28230 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28233 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28236 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28239 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28243 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28247 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28251 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8268:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28251 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_S_D),
     /* 28254 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28256 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28258 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28260 */     GIR_RootConstrainSelectedInstOperands,
     /* 28261 */     // GIR_Coverage, 857,
     /* 28261 */     GIR_EraseRootFromParent_Done,
     /* 28262 */   // Label 822: @28262
     /* 28262 */   GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(28307), // Rule ID 858 //
     /* 28267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28270 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_h),
     /* 28275 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28278 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28281 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28284 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28288 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28292 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28296 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8272:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HADD_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_H),
     /* 28299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28301 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28303 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28305 */     GIR_RootConstrainSelectedInstOperands,
     /* 28306 */     // GIR_Coverage, 858,
     /* 28306 */     GIR_EraseRootFromParent_Done,
     /* 28307 */   // Label 823: @28307
     /* 28307 */   GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(28352), // Rule ID 859 //
     /* 28312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28315 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_w),
     /* 28320 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28323 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28326 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28329 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28333 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28337 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28341 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8273:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HADD_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28341 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_W),
     /* 28344 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28346 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28348 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28350 */     GIR_RootConstrainSelectedInstOperands,
     /* 28351 */     // GIR_Coverage, 859,
     /* 28351 */     GIR_EraseRootFromParent_Done,
     /* 28352 */   // Label 824: @28352
     /* 28352 */   GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(28397), // Rule ID 860 //
     /* 28357 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28360 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hadd_u_d),
     /* 28365 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28368 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28371 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28374 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28378 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28382 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28386 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8271:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HADD_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HADD_U_D),
     /* 28389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28391 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28393 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28395 */     GIR_RootConstrainSelectedInstOperands,
     /* 28396 */     // GIR_Coverage, 860,
     /* 28396 */     GIR_EraseRootFromParent_Done,
     /* 28397 */   // Label 825: @28397
     /* 28397 */   GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(28442), // Rule ID 861 //
     /* 28402 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28405 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_h),
     /* 28410 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28413 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28416 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28419 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28423 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28427 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28431 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8275:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_S_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28431 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_H),
     /* 28434 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28436 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28438 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28440 */     GIR_RootConstrainSelectedInstOperands,
     /* 28441 */     // GIR_Coverage, 861,
     /* 28441 */     GIR_EraseRootFromParent_Done,
     /* 28442 */   // Label 826: @28442
     /* 28442 */   GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(28487), // Rule ID 862 //
     /* 28447 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28450 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_w),
     /* 28455 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28458 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28461 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28464 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28468 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28472 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28476 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8276:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_S_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28476 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_W),
     /* 28479 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28481 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28483 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28485 */     GIR_RootConstrainSelectedInstOperands,
     /* 28486 */     // GIR_Coverage, 862,
     /* 28486 */     GIR_EraseRootFromParent_Done,
     /* 28487 */   // Label 827: @28487
     /* 28487 */   GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(28532), // Rule ID 863 //
     /* 28492 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28495 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_s_d),
     /* 28500 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28503 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28506 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28513 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28517 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28521 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8274:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_S_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28521 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_S_D),
     /* 28524 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28526 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28528 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28530 */     GIR_RootConstrainSelectedInstOperands,
     /* 28531 */     // GIR_Coverage, 863,
     /* 28531 */     GIR_EraseRootFromParent_Done,
     /* 28532 */   // Label 828: @28532
     /* 28532 */   GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(28577), // Rule ID 864 //
     /* 28537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_h),
     /* 28545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28558 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28562 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28566 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8278:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (HSUB_U_H:{ *:[v8i16] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_H),
     /* 28569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28571 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28573 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28575 */     GIR_RootConstrainSelectedInstOperands,
     /* 28576 */     // GIR_Coverage, 864,
     /* 28576 */     GIR_EraseRootFromParent_Done,
     /* 28577 */   // Label 829: @28577
     /* 28577 */   GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(28622), // Rule ID 865 //
     /* 28582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28585 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_w),
     /* 28590 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28593 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28596 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28599 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28603 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28607 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28611 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8279:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (HSUB_U_W:{ *:[v4i32] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28611 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_W),
     /* 28614 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28616 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28618 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28620 */     GIR_RootConstrainSelectedInstOperands,
     /* 28621 */     // GIR_Coverage, 865,
     /* 28621 */     GIR_EraseRootFromParent_Done,
     /* 28622 */   // Label 830: @28622
     /* 28622 */   GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(28667), // Rule ID 866 //
     /* 28627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28630 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_hsub_u_d),
     /* 28635 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28638 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28641 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28644 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28648 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28652 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28656 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8277:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (HSUB_U_D:{ *:[v2i64] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::HSUB_U_D),
     /* 28659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28661 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28663 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28665 */     GIR_RootConstrainSelectedInstOperands,
     /* 28666 */     // GIR_Coverage, 866,
     /* 28666 */     GIR_EraseRootFromParent_Done,
     /* 28667 */   // Label 831: @28667
     /* 28667 */   GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(28712), // Rule ID 919 //
     /* 28672 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28675 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_b),
     /* 28680 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 28683 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28686 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28693 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28697 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28701 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8333:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28701 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_B),
     /* 28704 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28706 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28708 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28710 */     GIR_RootConstrainSelectedInstOperands,
     /* 28711 */     // GIR_Coverage, 919,
     /* 28711 */     GIR_EraseRootFromParent_Done,
     /* 28712 */   // Label 832: @28712
     /* 28712 */   GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(28757), // Rule ID 920 //
     /* 28717 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28720 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_h),
     /* 28725 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28728 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28731 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28734 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28738 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28742 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28746 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8335:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28746 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_H),
     /* 28749 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28751 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28753 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28755 */     GIR_RootConstrainSelectedInstOperands,
     /* 28756 */     // GIR_Coverage, 920,
     /* 28756 */     GIR_EraseRootFromParent_Done,
     /* 28757 */   // Label 833: @28757
     /* 28757 */   GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(28802), // Rule ID 921 //
     /* 28762 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28765 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_w),
     /* 28770 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28773 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28776 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28779 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28783 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28787 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28791 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8336:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28791 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_W),
     /* 28794 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28796 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28798 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28800 */     GIR_RootConstrainSelectedInstOperands,
     /* 28801 */     // GIR_Coverage, 921,
     /* 28801 */     GIR_EraseRootFromParent_Done,
     /* 28802 */   // Label 834: @28802
     /* 28802 */   GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(28847), // Rule ID 922 //
     /* 28807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_max_a_d),
     /* 28815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 28821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 28824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28832 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 28836 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8334:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 28836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MAX_A_D),
     /* 28839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28841 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28843 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28845 */     GIR_RootConstrainSelectedInstOperands,
     /* 28846 */     // GIR_Coverage, 922,
     /* 28846 */     GIR_EraseRootFromParent_Done,
     /* 28847 */   // Label 835: @28847
     /* 28847 */   GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(28892), // Rule ID 939 //
     /* 28852 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28855 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_b),
     /* 28860 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 28863 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 28866 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 28869 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28873 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28877 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 28881 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8353:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_A_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 28881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_B),
     /* 28884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28886 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28888 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28890 */     GIR_RootConstrainSelectedInstOperands,
     /* 28891 */     // GIR_Coverage, 939,
     /* 28891 */     GIR_EraseRootFromParent_Done,
     /* 28892 */   // Label 836: @28892
     /* 28892 */   GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(28937), // Rule ID 940 //
     /* 28897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_h),
     /* 28905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 28908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 28911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 28914 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28918 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28922 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 28926 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8355:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_A_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 28926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_H),
     /* 28929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28931 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28933 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28935 */     GIR_RootConstrainSelectedInstOperands,
     /* 28936 */     // GIR_Coverage, 940,
     /* 28936 */     GIR_EraseRootFromParent_Done,
     /* 28937 */   // Label 837: @28937
     /* 28937 */   GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(28982), // Rule ID 941 //
     /* 28942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28945 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_w),
     /* 28950 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 28953 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 28956 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 28959 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28963 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28967 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 28971 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8356:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_A_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 28971 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_W),
     /* 28974 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 28976 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 28978 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 28980 */     GIR_RootConstrainSelectedInstOperands,
     /* 28981 */     // GIR_Coverage, 941,
     /* 28981 */     GIR_EraseRootFromParent_Done,
     /* 28982 */   // Label 838: @28982
     /* 28982 */   GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(29027), // Rule ID 942 //
     /* 28987 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 28990 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_min_a_d),
     /* 28995 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 28998 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 29001 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 29004 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29012 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29016 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8354:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_A_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 29016 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_A_D),
     /* 29019 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29021 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29023 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29025 */     GIR_RootConstrainSelectedInstOperands,
     /* 29026 */     // GIR_Coverage, 942,
     /* 29026 */     GIR_EraseRootFromParent_Done,
     /* 29027 */   // Label 839: @29027
     /* 29027 */   GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(29072), // Rule ID 975 //
     /* 29032 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29035 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_h),
     /* 29040 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29043 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29046 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29049 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29053 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29057 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29061 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8395:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MUL_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29061 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_H),
     /* 29064 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29066 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29068 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29070 */     GIR_RootConstrainSelectedInstOperands,
     /* 29071 */     // GIR_Coverage, 975,
     /* 29071 */     GIR_EraseRootFromParent_Done,
     /* 29072 */   // Label 840: @29072
     /* 29072 */   GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(29117), // Rule ID 976 //
     /* 29077 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29080 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_q_w),
     /* 29085 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29088 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29091 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29094 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29098 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29102 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29106 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8396:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MUL_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29106 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_Q_W),
     /* 29109 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29111 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29113 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29115 */     GIR_RootConstrainSelectedInstOperands,
     /* 29116 */     // GIR_Coverage, 976,
     /* 29116 */     GIR_EraseRootFromParent_Done,
     /* 29117 */   // Label 841: @29117
     /* 29117 */   GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(29162), // Rule ID 977 //
     /* 29122 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29125 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_h),
     /* 29130 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29133 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29136 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29139 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29143 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29147 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29151 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8406:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MULR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_H),
     /* 29154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29156 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29158 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29160 */     GIR_RootConstrainSelectedInstOperands,
     /* 29161 */     // GIR_Coverage, 977,
     /* 29161 */     GIR_EraseRootFromParent_Done,
     /* 29162 */   // Label 842: @29162
     /* 29162 */   GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(29207), // Rule ID 978 //
     /* 29167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulr_q_w),
     /* 29175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29184 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29188 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29192 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29196 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8407:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MULR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29196 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULR_Q_W),
     /* 29199 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29201 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29203 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29205 */     GIR_RootConstrainSelectedInstOperands,
     /* 29206 */     // GIR_Coverage, 978,
     /* 29206 */     GIR_EraseRootFromParent_Done,
     /* 29207 */   // Label 843: @29207
     /* 29207 */   GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(29252), // Rule ID 1056 //
     /* 29212 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29215 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_b),
     /* 29220 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 29223 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 29226 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 29229 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29233 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29237 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29241 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8520:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRAR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 29241 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_B),
     /* 29244 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29246 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29248 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29250 */     GIR_RootConstrainSelectedInstOperands,
     /* 29251 */     // GIR_Coverage, 1056,
     /* 29251 */     GIR_EraseRootFromParent_Done,
     /* 29252 */   // Label 844: @29252
     /* 29252 */   GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(29297), // Rule ID 1057 //
     /* 29257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29260 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_h),
     /* 29265 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29268 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29271 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29274 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29278 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29282 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29286 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8522:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRAR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_H),
     /* 29289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29291 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29293 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29295 */     GIR_RootConstrainSelectedInstOperands,
     /* 29296 */     // GIR_Coverage, 1057,
     /* 29296 */     GIR_EraseRootFromParent_Done,
     /* 29297 */   // Label 845: @29297
     /* 29297 */   GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(29342), // Rule ID 1058 //
     /* 29302 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29305 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_w),
     /* 29310 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29313 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29316 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29319 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29323 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29327 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29331 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8523:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRAR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29331 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_W),
     /* 29334 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29336 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29338 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29340 */     GIR_RootConstrainSelectedInstOperands,
     /* 29341 */     // GIR_Coverage, 1058,
     /* 29341 */     GIR_EraseRootFromParent_Done,
     /* 29342 */   // Label 846: @29342
     /* 29342 */   GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(29387), // Rule ID 1059 //
     /* 29347 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29350 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srar_d),
     /* 29355 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 29358 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 29361 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 29364 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29368 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29372 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29376 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8521:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRAR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 29376 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRAR_D),
     /* 29379 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29381 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29383 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29385 */     GIR_RootConstrainSelectedInstOperands,
     /* 29386 */     // GIR_Coverage, 1059,
     /* 29386 */     GIR_EraseRootFromParent_Done,
     /* 29387 */   // Label 847: @29387
     /* 29387 */   GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(29432), // Rule ID 1072 //
     /* 29392 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29395 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_b),
     /* 29400 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 29403 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 29406 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 29409 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29413 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29417 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29421 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8536:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRLR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 29421 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_B),
     /* 29424 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29426 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29428 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29430 */     GIR_RootConstrainSelectedInstOperands,
     /* 29431 */     // GIR_Coverage, 1072,
     /* 29431 */     GIR_EraseRootFromParent_Done,
     /* 29432 */   // Label 848: @29432
     /* 29432 */   GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(29477), // Rule ID 1073 //
     /* 29437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_h),
     /* 29445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29462 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29466 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8538:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRLR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_H),
     /* 29469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29471 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29473 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29475 */     GIR_RootConstrainSelectedInstOperands,
     /* 29476 */     // GIR_Coverage, 1073,
     /* 29476 */     GIR_EraseRootFromParent_Done,
     /* 29477 */   // Label 849: @29477
     /* 29477 */   GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(29522), // Rule ID 1074 //
     /* 29482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_w),
     /* 29490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29503 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29507 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29511 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8539:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRLR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29511 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_W),
     /* 29514 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29516 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29518 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29520 */     GIR_RootConstrainSelectedInstOperands,
     /* 29521 */     // GIR_Coverage, 1074,
     /* 29521 */     GIR_EraseRootFromParent_Done,
     /* 29522 */   // Label 850: @29522
     /* 29522 */   GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(29567), // Rule ID 1075 //
     /* 29527 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29530 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_srlr_d),
     /* 29535 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 29538 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 29541 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 29544 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29552 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29556 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8537:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRLR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 29556 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRLR_D),
     /* 29559 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29561 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29563 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29565 */     GIR_RootConstrainSelectedInstOperands,
     /* 29566 */     // GIR_Coverage, 1075,
     /* 29566 */     GIR_EraseRootFromParent_Done,
     /* 29567 */   // Label 851: @29567
     /* 29567 */   GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(29612), // Rule ID 1084 //
     /* 29572 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29575 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_b),
     /* 29580 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 29583 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 29586 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 29589 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29593 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29597 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29601 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8557:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 29601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_B),
     /* 29604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29606 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29608 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29610 */     GIR_RootConstrainSelectedInstOperands,
     /* 29611 */     // GIR_Coverage, 1084,
     /* 29611 */     GIR_EraseRootFromParent_Done,
     /* 29612 */   // Label 852: @29612
     /* 29612 */   GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(29657), // Rule ID 1085 //
     /* 29617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29620 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_h),
     /* 29625 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29628 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29631 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29638 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29642 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29646 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8559:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29646 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_H),
     /* 29649 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29651 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29653 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29655 */     GIR_RootConstrainSelectedInstOperands,
     /* 29656 */     // GIR_Coverage, 1085,
     /* 29656 */     GIR_EraseRootFromParent_Done,
     /* 29657 */   // Label 853: @29657
     /* 29657 */   GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(29702), // Rule ID 1086 //
     /* 29662 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29665 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_w),
     /* 29670 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29673 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29676 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29679 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29683 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29687 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29691 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8560:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29691 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_W),
     /* 29694 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29696 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29698 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29700 */     GIR_RootConstrainSelectedInstOperands,
     /* 29701 */     // GIR_Coverage, 1086,
     /* 29701 */     GIR_EraseRootFromParent_Done,
     /* 29702 */   // Label 854: @29702
     /* 29702 */   GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(29747), // Rule ID 1087 //
     /* 29707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_s_d),
     /* 29715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 29718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 29721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 29724 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29728 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29732 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29736 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8558:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 29736 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_S_D),
     /* 29739 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29741 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29743 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29745 */     GIR_RootConstrainSelectedInstOperands,
     /* 29746 */     // GIR_Coverage, 1087,
     /* 29746 */     GIR_EraseRootFromParent_Done,
     /* 29747 */   // Label 855: @29747
     /* 29747 */   GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(29792), // Rule ID 1088 //
     /* 29752 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29755 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_b),
     /* 29760 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 29763 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 29766 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 29769 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29773 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29777 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29781 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8561:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 29781 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_B),
     /* 29784 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29786 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29788 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29790 */     GIR_RootConstrainSelectedInstOperands,
     /* 29791 */     // GIR_Coverage, 1088,
     /* 29791 */     GIR_EraseRootFromParent_Done,
     /* 29792 */   // Label 856: @29792
     /* 29792 */   GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(29837), // Rule ID 1089 //
     /* 29797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_h),
     /* 29805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29822 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29826 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8563:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 29826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_H),
     /* 29829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29831 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29833 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29835 */     GIR_RootConstrainSelectedInstOperands,
     /* 29836 */     // GIR_Coverage, 1089,
     /* 29836 */     GIR_EraseRootFromParent_Done,
     /* 29837 */   // Label 857: @29837
     /* 29837 */   GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(29882), // Rule ID 1090 //
     /* 29842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29845 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_w),
     /* 29850 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 29853 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 29856 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 29859 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29863 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29867 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 29871 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8564:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 29871 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_W),
     /* 29874 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29876 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29878 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29880 */     GIR_RootConstrainSelectedInstOperands,
     /* 29881 */     // GIR_Coverage, 1090,
     /* 29881 */     GIR_EraseRootFromParent_Done,
     /* 29882 */   // Label 858: @29882
     /* 29882 */   GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(29927), // Rule ID 1091 //
     /* 29887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29890 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subs_u_d),
     /* 29895 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 29898 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 29901 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 29904 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29908 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29912 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 29916 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8562:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 29916 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBS_U_D),
     /* 29919 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29921 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29923 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29925 */     GIR_RootConstrainSelectedInstOperands,
     /* 29926 */     // GIR_Coverage, 1091,
     /* 29926 */     GIR_EraseRootFromParent_Done,
     /* 29927 */   // Label 859: @29927
     /* 29927 */   GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(29972), // Rule ID 1092 //
     /* 29932 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29935 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_b),
     /* 29940 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 29943 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 29946 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 29949 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29953 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29957 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 29961 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8565:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUS_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 29961 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_B),
     /* 29964 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 29966 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 29968 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 29970 */     GIR_RootConstrainSelectedInstOperands,
     /* 29971 */     // GIR_Coverage, 1092,
     /* 29971 */     GIR_EraseRootFromParent_Done,
     /* 29972 */   // Label 860: @29972
     /* 29972 */   GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(30017), // Rule ID 1093 //
     /* 29977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 29980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_h),
     /* 29985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 29988 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 29991 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 29994 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 29998 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 30002 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 30006 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8567:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUS_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 30006 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_H),
     /* 30009 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30011 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30013 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30015 */     GIR_RootConstrainSelectedInstOperands,
     /* 30016 */     // GIR_Coverage, 1093,
     /* 30016 */     GIR_EraseRootFromParent_Done,
     /* 30017 */   // Label 861: @30017
     /* 30017 */   GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(30062), // Rule ID 1094 //
     /* 30022 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30025 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_w),
     /* 30030 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 30033 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 30036 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 30039 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30043 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30047 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30051 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8568:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUS_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 30051 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_W),
     /* 30054 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30056 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30058 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30060 */     GIR_RootConstrainSelectedInstOperands,
     /* 30061 */     // GIR_Coverage, 1094,
     /* 30061 */     GIR_EraseRootFromParent_Done,
     /* 30062 */   // Label 862: @30062
     /* 30062 */   GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(30107), // Rule ID 1095 //
     /* 30067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30070 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsus_u_d),
     /* 30075 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 30078 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 30081 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 30084 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30088 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30092 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30096 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8566:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUS_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 30096 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUS_U_D),
     /* 30099 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30101 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30103 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30105 */     GIR_RootConstrainSelectedInstOperands,
     /* 30106 */     // GIR_Coverage, 1095,
     /* 30106 */     GIR_EraseRootFromParent_Done,
     /* 30107 */   // Label 863: @30107
     /* 30107 */   GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(30152), // Rule ID 1096 //
     /* 30112 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30115 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_b),
     /* 30120 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 30123 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 30126 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 30129 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 30133 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 30137 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 30141 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8569:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SUBSUU_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 30141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_B),
     /* 30144 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30146 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30148 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30150 */     GIR_RootConstrainSelectedInstOperands,
     /* 30151 */     // GIR_Coverage, 1096,
     /* 30151 */     GIR_EraseRootFromParent_Done,
     /* 30152 */   // Label 864: @30152
     /* 30152 */   GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(30197), // Rule ID 1097 //
     /* 30157 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30160 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_h),
     /* 30165 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 30168 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 30171 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 30174 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 30178 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 30182 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 30186 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8571:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SUBSUU_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 30186 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_H),
     /* 30189 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30191 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30193 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30195 */     GIR_RootConstrainSelectedInstOperands,
     /* 30196 */     // GIR_Coverage, 1097,
     /* 30196 */     GIR_EraseRootFromParent_Done,
     /* 30197 */   // Label 865: @30197
     /* 30197 */   GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(30242), // Rule ID 1098 //
     /* 30202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_w),
     /* 30210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 30213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 30216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 30219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30223 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30227 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 30231 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8572:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SUBSUU_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 30231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_W),
     /* 30234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30236 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30238 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30240 */     GIR_RootConstrainSelectedInstOperands,
     /* 30241 */     // GIR_Coverage, 1098,
     /* 30241 */     GIR_EraseRootFromParent_Done,
     /* 30242 */   // Label 866: @30242
     /* 30242 */   GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(30287), // Rule ID 1099 //
     /* 30247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 30250 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subsuu_s_d),
     /* 30255 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 30258 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 30261 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 30264 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30268 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30272 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 30276 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8570:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SUBSUU_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 30276 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBSUU_S_D),
     /* 30279 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 30281 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 30283 */     GIR_RootToRootCopy, /*OpIdx*/3, // wt
     /* 30285 */     GIR_RootConstrainSelectedInstOperands,
     /* 30286 */     // GIR_Coverage, 1099,
     /* 30286 */     GIR_EraseRootFromParent_Done,
     /* 30287 */   // Label 867: @30287
     /* 30287 */   GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(30335), // Rule ID 1298 //
     /* 30292 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30295 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_ph),
     /* 30300 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30303 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30306 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30309 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30313 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30317 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30321 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7931:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30321 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_PH_MM),
     /* 30324 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30326 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30328 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30330 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 30333 */     GIR_RootConstrainSelectedInstOperands,
     /* 30334 */     // GIR_Coverage, 1298,
     /* 30334 */     GIR_EraseRootFromParent_Done,
     /* 30335 */   // Label 868: @30335
     /* 30335 */   GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(30383), // Rule ID 1300 //
     /* 30340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30343 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_qb),
     /* 30348 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 30351 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 30354 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 30357 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30361 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30365 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30369 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7953:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 30369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_QB_MM),
     /* 30372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30374 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30376 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30378 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 30381 */     GIR_RootConstrainSelectedInstOperands,
     /* 30382 */     // GIR_Coverage, 1300,
     /* 30382 */     GIR_EraseRootFromParent_Done,
     /* 30383 */   // Label 869: @30383
     /* 30383 */   GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(30428), // Rule ID 1321 //
     /* 30388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_ph),
     /* 30396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30402 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30405 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30409 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30413 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30417 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8481:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 30417 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_PH_MM),
     /* 30420 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30422 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 30424 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 30426 */     GIR_RootConstrainSelectedInstOperands,
     /* 30427 */     // GIR_Coverage, 1321,
     /* 30427 */     GIR_EraseRootFromParent_Done,
     /* 30428 */   // Label 870: @30428
     /* 30428 */   GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(30473), // Rule ID 1322 //
     /* 30433 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30436 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_ph),
     /* 30441 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30444 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30447 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30450 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30454 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30458 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30462 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8483:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 30462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_PH_MM),
     /* 30465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30467 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 30469 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 30471 */     GIR_RootConstrainSelectedInstOperands,
     /* 30472 */     // GIR_Coverage, 1322,
     /* 30472 */     GIR_EraseRootFromParent_Done,
     /* 30473 */   // Label 871: @30473
     /* 30473 */   GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(30518), // Rule ID 1323 //
     /* 30478 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30481 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_w),
     /* 30486 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 30489 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 30492 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30495 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30499 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30503 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30507 */     // (intrinsic_wo_chain:{ *:[i32] } 8485:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 30507 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_W_MM),
     /* 30510 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30512 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 30514 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 30516 */     GIR_RootConstrainSelectedInstOperands,
     /* 30517 */     // GIR_Coverage, 1323,
     /* 30517 */     GIR_EraseRootFromParent_Done,
     /* 30518 */   // Label 872: @30518
     /* 30518 */   GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(30563), // Rule ID 1325 //
     /* 30523 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30526 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_qb),
     /* 30531 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 30534 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 30537 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30544 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30548 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30552 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8487:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 30552 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_QB_MM),
     /* 30555 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30557 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 30559 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 30561 */     GIR_RootConstrainSelectedInstOperands,
     /* 30562 */     // GIR_Coverage, 1325,
     /* 30562 */     GIR_EraseRootFromParent_Done,
     /* 30563 */   // Label 873: @30563
     /* 30563 */   GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(30611), // Rule ID 1336 //
     /* 30568 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30571 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_ph),
     /* 30576 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30579 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30582 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30589 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30593 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30597 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8551:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30597 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_PH_MM),
     /* 30600 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30602 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30604 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30606 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 30609 */     GIR_RootConstrainSelectedInstOperands,
     /* 30610 */     // GIR_Coverage, 1336,
     /* 30610 */     GIR_EraseRootFromParent_Done,
     /* 30611 */   // Label 874: @30611
     /* 30611 */   GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(30659), // Rule ID 1338 //
     /* 30616 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30619 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_qb),
     /* 30624 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 30627 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 30630 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 30633 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30637 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30641 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30645 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8576:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBU_S_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 30645 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_QB_MM),
     /* 30648 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30650 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30652 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30654 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 30657 */     GIR_RootConstrainSelectedInstOperands,
     /* 30658 */     // GIR_Coverage, 1338,
     /* 30658 */     GIR_EraseRootFromParent_Done,
     /* 30659 */   // Label 875: @30659
     /* 30659 */   GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(30704), // Rule ID 1348 //
     /* 30664 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30667 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_ph_w),
     /* 30672 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30675 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 30678 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30681 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30685 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30689 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30693 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8456:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 30693 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_PH_W_MM),
     /* 30696 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30698 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30700 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30702 */     GIR_RootConstrainSelectedInstOperands,
     /* 30703 */     // GIR_Coverage, 1348,
     /* 30703 */     GIR_EraseRootFromParent_Done,
     /* 30704 */   // Label 876: @30704
     /* 30704 */   GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(30749), // Rule ID 1349 //
     /* 30709 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30712 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_qb_ph),
     /* 30717 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 30720 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30723 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30726 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30730 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30734 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30738 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8457:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQ_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30738 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_QB_PH_MM),
     /* 30741 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30743 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30745 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30747 */     GIR_RootConstrainSelectedInstOperands,
     /* 30748 */     // GIR_Coverage, 1349,
     /* 30748 */     GIR_EraseRootFromParent_Done,
     /* 30749 */   // Label 877: @30749
     /* 30749 */   GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(30794), // Rule ID 1368 //
     /* 30754 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30757 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_packrl_ph),
     /* 30762 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30765 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30768 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30771 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30775 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30779 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30783 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8428:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PACKRL_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30783 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PACKRL_PH_MM),
     /* 30786 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30788 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30790 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30792 */     GIR_RootConstrainSelectedInstOperands,
     /* 30793 */     // GIR_Coverage, 1368,
     /* 30793 */     GIR_EraseRootFromParent_Done,
     /* 30794 */   // Label 878: @30794
     /* 30794 */   GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(30839), // Rule ID 1374 //
     /* 30799 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 30802 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_modsub),
     /* 30807 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 30810 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 30813 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30816 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30820 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30824 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30828 */     // (intrinsic_wo_chain:{ *:[i32] } 8381:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MODSUB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 30828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MODSUB_MM),
     /* 30831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30833 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30835 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30837 */     GIR_RootConstrainSelectedInstOperands,
     /* 30838 */     // GIR_Coverage, 1374,
     /* 30838 */     GIR_EraseRootFromParent_Done,
     /* 30839 */   // Label 879: @30839
     /* 30839 */   GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(30884), // Rule ID 1387 //
     /* 30844 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 30847 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_ph),
     /* 30852 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30855 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30858 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30861 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30865 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30869 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30873 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7933:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_PH_MMR2),
     /* 30876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30878 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30880 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30882 */     GIR_RootConstrainSelectedInstOperands,
     /* 30883 */     // GIR_Coverage, 1387,
     /* 30883 */     GIR_EraseRootFromParent_Done,
     /* 30884 */   // Label 880: @30884
     /* 30884 */   GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(30929), // Rule ID 1388 //
     /* 30889 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 30892 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_ph),
     /* 30897 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 30900 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 30903 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 30906 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30910 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30914 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 30918 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7934:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 30918 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_PH_MMR2),
     /* 30921 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30923 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30925 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30927 */     GIR_RootConstrainSelectedInstOperands,
     /* 30928 */     // GIR_Coverage, 1388,
     /* 30928 */     GIR_EraseRootFromParent_Done,
     /* 30929 */   // Label 881: @30929
     /* 30929 */   GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(30974), // Rule ID 1389 //
     /* 30934 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 30937 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_w),
     /* 30942 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 30945 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 30948 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30955 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30959 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 30963 */     // (intrinsic_wo_chain:{ *:[i32] } 7936:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 30963 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_W_MMR2),
     /* 30966 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 30968 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 30970 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 30972 */     GIR_RootConstrainSelectedInstOperands,
     /* 30973 */     // GIR_Coverage, 1389,
     /* 30973 */     GIR_EraseRootFromParent_Done,
     /* 30974 */   // Label 882: @30974
     /* 30974 */   GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(31019), // Rule ID 1390 //
     /* 30979 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 30982 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addqh_r_w),
     /* 30987 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 30990 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 30993 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 30996 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31000 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31004 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31008 */     // (intrinsic_wo_chain:{ *:[i32] } 7935:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 31008 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQH_R_W_MMR2),
     /* 31011 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31013 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31015 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31017 */     GIR_RootConstrainSelectedInstOperands,
     /* 31018 */     // GIR_Coverage, 1390,
     /* 31018 */     GIR_EraseRootFromParent_Done,
     /* 31019 */   // Label 883: @31019
     /* 31019 */   GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(31064), // Rule ID 1393 //
     /* 31024 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31027 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_qb),
     /* 31032 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31035 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31045 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31049 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31053 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7954:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 31053 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_QB_MMR2),
     /* 31056 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31058 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31060 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31062 */     GIR_RootConstrainSelectedInstOperands,
     /* 31063 */     // GIR_Coverage, 1393,
     /* 31063 */     GIR_EraseRootFromParent_Done,
     /* 31064 */   // Label 884: @31064
     /* 31064 */   GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(31109), // Rule ID 1394 //
     /* 31069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_adduh_r_qb),
     /* 31077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31080 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31083 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31086 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31090 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31094 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31098 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7955:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ADDUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 31098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDUH_R_QB_MMR2),
     /* 31101 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31103 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31105 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31107 */     GIR_RootConstrainSelectedInstOperands,
     /* 31108 */     // GIR_Coverage, 1394,
     /* 31108 */     GIR_EraseRootFromParent_Done,
     /* 31109 */   // Label 885: @31109
     /* 31109 */   GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(31154), // Rule ID 1400 //
     /* 31114 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31117 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_qb),
     /* 31122 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31125 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31128 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31131 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31135 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31139 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31143 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8482:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 31143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_QB_MMR2),
     /* 31146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31148 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 31150 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31152 */     GIR_RootConstrainSelectedInstOperands,
     /* 31153 */     // GIR_Coverage, 1400,
     /* 31153 */     GIR_EraseRootFromParent_Done,
     /* 31154 */   // Label 886: @31154
     /* 31154 */   GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(31199), // Rule ID 1401 //
     /* 31159 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31162 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shra_r_qb),
     /* 31167 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31170 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31173 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31176 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31180 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31184 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31188 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8484:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRAV_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 31188 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRAV_R_QB_MMR2),
     /* 31191 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31193 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 31195 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31197 */     GIR_RootConstrainSelectedInstOperands,
     /* 31198 */     // GIR_Coverage, 1401,
     /* 31198 */     GIR_EraseRootFromParent_Done,
     /* 31199 */   // Label 887: @31199
     /* 31199 */   GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(31244), // Rule ID 1406 //
     /* 31204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31207 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shrl_ph),
     /* 31212 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31215 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 31218 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31221 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31225 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31229 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31233 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8486:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHRLV_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 31233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHRLV_PH_MMR2),
     /* 31236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31238 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 31240 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31242 */     GIR_RootConstrainSelectedInstOperands,
     /* 31243 */     // GIR_Coverage, 1406,
     /* 31243 */     GIR_EraseRootFromParent_Done,
     /* 31244 */   // Label 888: @31244
     /* 31244 */   GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(31289), // Rule ID 1407 //
     /* 31249 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31252 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_ph),
     /* 31257 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31260 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 31263 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 31266 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31270 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31274 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31278 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8553:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 31278 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_PH_MMR2),
     /* 31281 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31283 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31285 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31287 */     GIR_RootConstrainSelectedInstOperands,
     /* 31288 */     // GIR_Coverage, 1407,
     /* 31288 */     GIR_EraseRootFromParent_Done,
     /* 31289 */   // Label 889: @31289
     /* 31289 */   GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(31334), // Rule ID 1408 //
     /* 31294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31297 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_ph),
     /* 31302 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31305 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 31308 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 31311 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31315 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31319 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31323 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8554:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBQH_R_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 31323 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_PH_MMR2),
     /* 31326 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31328 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31330 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31332 */     GIR_RootConstrainSelectedInstOperands,
     /* 31333 */     // GIR_Coverage, 1408,
     /* 31333 */     GIR_EraseRootFromParent_Done,
     /* 31334 */   // Label 890: @31334
     /* 31334 */   GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(31379), // Rule ID 1409 //
     /* 31339 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31342 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_w),
     /* 31347 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 31350 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31353 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31356 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31360 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31364 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31368 */     // (intrinsic_wo_chain:{ *:[i32] } 8556:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 31368 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_W_MMR2),
     /* 31371 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31373 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31375 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31377 */     GIR_RootConstrainSelectedInstOperands,
     /* 31378 */     // GIR_Coverage, 1409,
     /* 31378 */     GIR_EraseRootFromParent_Done,
     /* 31379 */   // Label 891: @31379
     /* 31379 */   GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(31424), // Rule ID 1410 //
     /* 31384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31387 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subqh_r_w),
     /* 31392 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 31395 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31398 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31401 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31405 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31409 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31413 */     // (intrinsic_wo_chain:{ *:[i32] } 8555:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQH_R_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 31413 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQH_R_W_MMR2),
     /* 31416 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31418 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31420 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31422 */     GIR_RootConstrainSelectedInstOperands,
     /* 31423 */     // GIR_Coverage, 1410,
     /* 31423 */     GIR_EraseRootFromParent_Done,
     /* 31424 */   // Label 892: @31424
     /* 31424 */   GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(31469), // Rule ID 1413 //
     /* 31429 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31432 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_qb),
     /* 31437 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31440 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31443 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31446 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31450 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31454 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31458 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8577:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 31458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_QB_MMR2),
     /* 31461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31463 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31465 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31467 */     GIR_RootConstrainSelectedInstOperands,
     /* 31468 */     // GIR_Coverage, 1413,
     /* 31468 */     GIR_EraseRootFromParent_Done,
     /* 31469 */   // Label 893: @31469
     /* 31469 */   GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(31514), // Rule ID 1414 //
     /* 31474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 31477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subuh_r_qb),
     /* 31482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31488 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31491 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31495 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31499 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31503 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8578:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (SUBUH_R_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 31503 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBUH_R_QB_MMR2),
     /* 31506 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31508 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 31510 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 31512 */     GIR_RootConstrainSelectedInstOperands,
     /* 31513 */     // GIR_Coverage, 1414,
     /* 31513 */     GIR_EraseRootFromParent_Done,
     /* 31514 */   // Label 894: @31514
     /* 31514 */   GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(31554), // Rule ID 2052 //
     /* 31519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 31522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_ph),
     /* 31527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 31533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 31536 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31540 */     // (intrinsic_wo_chain:{ *:[v2i16] } 7930:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /* 31540 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_PH),
     /* 31543 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31545 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 31547 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 31549 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 31552 */     GIR_RootConstrainSelectedInstOperands,
     /* 31553 */     // GIR_Coverage, 2052,
     /* 31553 */     GIR_EraseRootFromParent_Done,
     /* 31554 */   // Label 895: @31554
     /* 31554 */   GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(31594), // Rule ID 2054 //
     /* 31559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 31562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_ph),
     /* 31567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 31573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 31576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31580 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8550:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /* 31580 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_PH),
     /* 31583 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31585 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 31587 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 31589 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 31592 */     GIR_RootConstrainSelectedInstOperands,
     /* 31593 */     // GIR_Coverage, 2054,
     /* 31593 */     GIR_EraseRootFromParent_Done,
     /* 31594 */   // Label 896: @31594
     /* 31594 */   GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(31634), // Rule ID 2058 //
     /* 31599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 31602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_qb),
     /* 31607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31616 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31620 */     // (intrinsic_wo_chain:{ *:[v4i8] } 7951:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
     /* 31620 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_QB),
     /* 31623 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31625 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 31627 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 31629 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 31632 */     GIR_RootConstrainSelectedInstOperands,
     /* 31633 */     // GIR_Coverage, 2058,
     /* 31633 */     GIR_EraseRootFromParent_Done,
     /* 31634 */   // Label 897: @31634
     /* 31634 */   GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(31674), // Rule ID 2060 //
     /* 31639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 31642 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_qb),
     /* 31647 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 31650 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 31653 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 31656 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31660 */     // (intrinsic_wo_chain:{ *:[v4i8] } 8574:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)  =>  (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
     /* 31660 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_QB),
     /* 31663 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 31665 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 31667 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 31669 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 31672 */     GIR_RootConstrainSelectedInstOperands,
     /* 31673 */     // GIR_Coverage, 2060,
     /* 31673 */     GIR_EraseRootFromParent_Done,
     /* 31674 */   // Label 898: @31674
     /* 31674 */   GIM_Reject,
     /* 31675 */ // Label 684: @31675
     /* 31675 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(34189),
     /* 31680 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
     /* 31683 */   GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(31738), // Rule ID 552 //
     /* 31688 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 31691 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
     /* 31696 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31699 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31702 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31705 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31709 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31713 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31717 */     // MIs[0] sa
     /* 31717 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31720 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 31725 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8454:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 31725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W),
     /* 31728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 31730 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31732 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 31734 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 31736 */     GIR_RootConstrainSelectedInstOperands,
     /* 31737 */     // GIR_Coverage, 552,
     /* 31737 */     GIR_EraseRootFromParent_Done,
     /* 31738 */   // Label 900: @31738
     /* 31738 */   GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(31793), // Rule ID 553 //
     /* 31743 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 31746 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
     /* 31751 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 31754 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31757 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31760 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 31764 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31768 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31772 */     // MIs[0] sa
     /* 31772 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31775 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 31780 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8455:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 31780 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W),
     /* 31783 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 31785 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31787 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 31789 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 31791 */     GIR_RootConstrainSelectedInstOperands,
     /* 31792 */     // GIR_Coverage, 553,
     /* 31792 */     GIR_EraseRootFromParent_Done,
     /* 31793 */   // Label 901: @31793
     /* 31793 */   GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(31848), // Rule ID 558 //
     /* 31798 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 31801 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
     /* 31806 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 31809 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31812 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31815 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31819 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31823 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31827 */     // MIs[0] sa
     /* 31827 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31830 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 31835 */     // (intrinsic_wo_chain:{ *:[i32] } 7967:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 31835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND),
     /* 31838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 31840 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31842 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 31844 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 31846 */     GIR_RootConstrainSelectedInstOperands,
     /* 31847 */     // GIR_Coverage, 558,
     /* 31847 */     GIR_EraseRootFromParent_Done,
     /* 31848 */   // Label 902: @31848
     /* 31848 */   GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(31903), // Rule ID 559 //
     /* 31853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 31856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
     /* 31861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 31864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31874 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31878 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31882 */     // MIs[0] sa
     /* 31882 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31885 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
     /* 31890 */     // (intrinsic_wo_chain:{ *:[i32] } 7992:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$sa)  =>  (BALIGN:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 31890 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN),
     /* 31893 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 31895 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31897 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 31899 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 31901 */     GIR_RootConstrainSelectedInstOperands,
     /* 31902 */     // GIR_Coverage, 559,
     /* 31902 */     GIR_EraseRootFromParent_Done,
     /* 31903 */   // Label 903: @31903
     /* 31903 */   GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(31958), // Rule ID 560 //
     /* 31908 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 31911 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
     /* 31916 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 31919 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 31922 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 31925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31929 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31933 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 31937 */     // MIs[0] sa
     /* 31937 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31940 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 31945 */     // (intrinsic_wo_chain:{ *:[i32] } 8460:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 31945 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND),
     /* 31948 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 31950 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 31952 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 31954 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 31956 */     GIR_RootConstrainSelectedInstOperands,
     /* 31957 */     // GIR_Coverage, 560,
     /* 31957 */     GIR_EraseRootFromParent_Done,
     /* 31958 */   // Label 904: @31958
     /* 31958 */   GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(32013), // Rule ID 1028 //
     /* 31963 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 31966 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_b),
     /* 31971 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 31974 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 31977 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 31980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 31984 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 31988 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 31992 */     // MIs[0] n
     /* 31992 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 31995 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt4),
     /* 32000 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8492:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt4>>:$n)  =>  (SLDI_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, (timm:{ *:[i32] }):$n)
     /* 32000 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_B),
     /* 32003 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32005 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32007 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32009 */     GIR_RootToRootCopy, /*OpIdx*/4, // n
     /* 32011 */     GIR_RootConstrainSelectedInstOperands,
     /* 32012 */     // GIR_Coverage, 1028,
     /* 32012 */     GIR_EraseRootFromParent_Done,
     /* 32013 */   // Label 905: @32013
     /* 32013 */   GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(32068), // Rule ID 1029 //
     /* 32018 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32021 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_h),
     /* 32026 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 32029 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 32032 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 32035 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32043 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32047 */     // MIs[0] n
     /* 32047 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32050 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt3),
     /* 32055 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8494:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt3>>:$n)  =>  (SLDI_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, (timm:{ *:[i32] }):$n)
     /* 32055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_H),
     /* 32058 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32060 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32062 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32064 */     GIR_RootToRootCopy, /*OpIdx*/4, // n
     /* 32066 */     GIR_RootConstrainSelectedInstOperands,
     /* 32067 */     // GIR_Coverage, 1029,
     /* 32067 */     GIR_EraseRootFromParent_Done,
     /* 32068 */   // Label 906: @32068
     /* 32068 */   GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(32123), // Rule ID 1030 //
     /* 32073 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32076 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_w),
     /* 32081 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 32084 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 32087 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 32090 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32098 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32102 */     // MIs[0] n
     /* 32102 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32105 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt2),
     /* 32110 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8495:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt2>>:$n)  =>  (SLDI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, (timm:{ *:[i32] }):$n)
     /* 32110 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_W),
     /* 32113 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32115 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32117 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32119 */     GIR_RootToRootCopy, /*OpIdx*/4, // n
     /* 32121 */     GIR_RootConstrainSelectedInstOperands,
     /* 32122 */     // GIR_Coverage, 1030,
     /* 32122 */     GIR_EraseRootFromParent_Done,
     /* 32123 */   // Label 907: @32123
     /* 32123 */   GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(32178), // Rule ID 1031 //
     /* 32128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sldi_d),
     /* 32136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 32139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 32142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 32145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32149 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32157 */     // MIs[0] n
     /* 32157 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32160 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt1),
     /* 32165 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8493:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] })<<P:Predicate_timmZExt1>>:$n)  =>  (SLDI_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, (timm:{ *:[i32] }):$n)
     /* 32165 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLDI_D),
     /* 32168 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32170 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32172 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32174 */     GIR_RootToRootCopy, /*OpIdx*/4, // n
     /* 32176 */     GIR_RootConstrainSelectedInstOperands,
     /* 32177 */     // GIR_Coverage, 1031,
     /* 32177 */     GIR_EraseRootFromParent_Done,
     /* 32178 */   // Label 908: @32178
     /* 32178 */   GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(32233), // Rule ID 1424 //
     /* 32183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 32186 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_ph_w),
     /* 32191 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 32194 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 32197 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 32200 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 32204 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32208 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32212 */     // MIs[0] sa
     /* 32212 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32215 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 32220 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8454:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 32220 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_PH_W_MMR2),
     /* 32223 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 32225 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 32227 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 32229 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 32231 */     GIR_RootConstrainSelectedInstOperands,
     /* 32232 */     // GIR_Coverage, 1424,
     /* 32232 */     GIR_EraseRootFromParent_Done,
     /* 32233 */   // Label 909: @32233
     /* 32233 */   GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(32288), // Rule ID 1425 //
     /* 32238 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 32241 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_sra_r_ph_w),
     /* 32246 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 32249 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 32252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 32255 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 32259 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32263 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32267 */     // MIs[0] sa
     /* 32267 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32270 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 32275 */     // (intrinsic_wo_chain:{ *:[v2i16] } 8455:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PRECR_SRA_R_PH_W_MMR2:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 32275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_SRA_R_PH_W_MMR2),
     /* 32278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 32280 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 32282 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 32284 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 32286 */     GIR_RootConstrainSelectedInstOperands,
     /* 32287 */     // GIR_Coverage, 1425,
     /* 32287 */     GIR_EraseRootFromParent_Done,
     /* 32288 */   // Label 910: @32288
     /* 32288 */   GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(32343), // Rule ID 1426 //
     /* 32293 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 32296 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_prepend),
     /* 32301 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 32304 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 32307 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 32310 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32314 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32318 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32322 */     // MIs[0] sa
     /* 32322 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32325 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 32330 */     // (intrinsic_wo_chain:{ *:[i32] } 8460:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (PREPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 32330 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PREPEND_MMR2),
     /* 32333 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 32335 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 32337 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 32339 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 32341 */     GIR_RootConstrainSelectedInstOperands,
     /* 32342 */     // GIR_Coverage, 1426,
     /* 32342 */     GIR_EraseRootFromParent_Done,
     /* 32343 */   // Label 911: @32343
     /* 32343 */   GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(32398), // Rule ID 1427 //
     /* 32348 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 32351 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_append),
     /* 32356 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 32359 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 32362 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 32365 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32369 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32373 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32377 */     // MIs[0] sa
     /* 32377 */     GIM_CheckIsImm, /*MI*/0, /*Op*/4,
     /* 32380 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt5),
     /* 32385 */     // (intrinsic_wo_chain:{ *:[i32] } 7967:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt5>>:$sa)  =>  (APPEND_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$sa, GPR32Opnd:{ *:[i32] }:$src)
     /* 32385 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::APPEND_MMR2),
     /* 32388 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 32390 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 32392 */     GIR_RootToRootCopy, /*OpIdx*/4, // sa
     /* 32394 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 32396 */     GIR_RootConstrainSelectedInstOperands,
     /* 32397 */     // GIR_Coverage, 1427,
     /* 32397 */     GIR_EraseRootFromParent_Done,
     /* 32398 */   // Label 912: @32398
     /* 32398 */   GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(32460), // Rule ID 1402 //
     /* 32403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 32406 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_balign),
     /* 32411 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 32414 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 32417 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 32420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32424 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32428 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 32432 */     // MIs[0] bp
     /* 32432 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
     /* 32436 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 32440 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2),
     /* 32444 */     // MIs[1] Operand 1
     /* 32444 */     // No operand predicates
     /* 32444 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 32446 */     // (intrinsic_wo_chain:{ *:[i32] } 7992:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2>>:$bp)  =>  (BALIGN_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$bp, GPR32Opnd:{ *:[i32] }:$src)
     /* 32446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BALIGN_MMR2),
     /* 32449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 32451 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 32453 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // bp
     /* 32456 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 32458 */     GIR_RootConstrainSelectedInstOperands,
     /* 32459 */     // GIR_Coverage, 1402,
     /* 32459 */     GIR_EraseRootFromParent_Done,
     /* 32460 */   // Label 913: @32460
     /* 32460 */   GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(32514), // Rule ID 627 //
     /* 32465 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32468 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_b),
     /* 32473 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 32476 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 32479 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 32482 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 32485 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32489 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32493 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32497 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32501 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8001:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 32501 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_B),
     /* 32504 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32506 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32508 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32510 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32512 */     GIR_RootConstrainSelectedInstOperands,
     /* 32513 */     // GIR_Coverage, 627,
     /* 32513 */     GIR_EraseRootFromParent_Done,
     /* 32514 */   // Label 914: @32514
     /* 32514 */   GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(32568), // Rule ID 628 //
     /* 32519 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32522 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_h),
     /* 32527 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 32530 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 32533 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 32536 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 32539 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32543 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32547 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32551 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32555 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8003:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 32555 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_H),
     /* 32558 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32560 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32562 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32564 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32566 */     GIR_RootConstrainSelectedInstOperands,
     /* 32567 */     // GIR_Coverage, 628,
     /* 32567 */     GIR_EraseRootFromParent_Done,
     /* 32568 */   // Label 915: @32568
     /* 32568 */   GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(32622), // Rule ID 629 //
     /* 32573 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32576 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_w),
     /* 32581 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 32584 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 32587 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 32590 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 32593 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32597 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32601 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32605 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32609 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8004:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 32609 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_W),
     /* 32612 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32614 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32616 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32618 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32620 */     GIR_RootConstrainSelectedInstOperands,
     /* 32621 */     // GIR_Coverage, 629,
     /* 32621 */     GIR_EraseRootFromParent_Done,
     /* 32622 */   // Label 916: @32622
     /* 32622 */   GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(32676), // Rule ID 630 //
     /* 32627 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32630 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsl_d),
     /* 32635 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 32638 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 32641 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 32644 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 32647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32651 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32655 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32659 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32663 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8002:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 32663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSL_D),
     /* 32666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32668 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32670 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32672 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32674 */     GIR_RootConstrainSelectedInstOperands,
     /* 32675 */     // GIR_Coverage, 630,
     /* 32675 */     GIR_EraseRootFromParent_Done,
     /* 32676 */   // Label 917: @32676
     /* 32676 */   GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(32730), // Rule ID 635 //
     /* 32681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32684 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_b),
     /* 32689 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 32692 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 32695 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 32698 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 32701 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32705 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32709 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32713 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32717 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8009:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (BINSR_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 32717 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_B),
     /* 32720 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32722 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32724 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32726 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32728 */     GIR_RootConstrainSelectedInstOperands,
     /* 32729 */     // GIR_Coverage, 635,
     /* 32729 */     GIR_EraseRootFromParent_Done,
     /* 32730 */   // Label 918: @32730
     /* 32730 */   GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(32784), // Rule ID 636 //
     /* 32735 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32738 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_h),
     /* 32743 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 32746 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 32749 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 32752 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 32755 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32759 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32763 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32767 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32771 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8011:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (BINSR_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 32771 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_H),
     /* 32774 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32776 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32778 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32780 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32782 */     GIR_RootConstrainSelectedInstOperands,
     /* 32783 */     // GIR_Coverage, 636,
     /* 32783 */     GIR_EraseRootFromParent_Done,
     /* 32784 */   // Label 919: @32784
     /* 32784 */   GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(32838), // Rule ID 637 //
     /* 32789 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32792 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_w),
     /* 32797 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 32800 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 32803 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 32806 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 32809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32813 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32817 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32821 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32825 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8012:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (BINSR_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 32825 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_W),
     /* 32828 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32830 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32832 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32834 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32836 */     GIR_RootConstrainSelectedInstOperands,
     /* 32837 */     // GIR_Coverage, 637,
     /* 32837 */     GIR_EraseRootFromParent_Done,
     /* 32838 */   // Label 920: @32838
     /* 32838 */   GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(32892), // Rule ID 638 //
     /* 32843 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32846 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_binsr_d),
     /* 32851 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 32854 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 32857 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 32860 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
     /* 32863 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32867 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32871 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32875 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 32879 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8010:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (BINSR_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 32879 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BINSR_D),
     /* 32882 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32884 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32886 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32888 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32890 */     GIR_RootConstrainSelectedInstOperands,
     /* 32891 */     // GIR_Coverage, 638,
     /* 32891 */     GIR_EraseRootFromParent_Done,
     /* 32892 */   // Label 921: @32892
     /* 32892 */   GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(32946), // Rule ID 733 //
     /* 32897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_h),
     /* 32905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 32908 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 32911 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 32914 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 32917 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32929 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 32933 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8130:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 32933 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_H),
     /* 32936 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32938 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32940 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32942 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32944 */     GIR_RootConstrainSelectedInstOperands,
     /* 32945 */     // GIR_Coverage, 733,
     /* 32945 */     GIR_EraseRootFromParent_Done,
     /* 32946 */   // Label 922: @32946
     /* 32946 */   GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(33000), // Rule ID 734 //
     /* 32951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 32954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_w),
     /* 32959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 32962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 32965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 32968 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 32971 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32975 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 32979 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32983 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 32987 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8131:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 32987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_W),
     /* 32990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 32992 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 32994 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 32996 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 32998 */     GIR_RootConstrainSelectedInstOperands,
     /* 32999 */     // GIR_Coverage, 734,
     /* 32999 */     GIR_EraseRootFromParent_Done,
     /* 33000 */   // Label 923: @33000
     /* 33000 */   GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(33054), // Rule ID 735 //
     /* 33005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_s_d),
     /* 33013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 33016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 33019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33022 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33025 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33029 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33033 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33037 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33041 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8129:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33041 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_S_D),
     /* 33044 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33046 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33048 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33050 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33052 */     GIR_RootConstrainSelectedInstOperands,
     /* 33053 */     // GIR_Coverage, 735,
     /* 33053 */     GIR_EraseRootFromParent_Done,
     /* 33054 */   // Label 924: @33054
     /* 33054 */   GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(33108), // Rule ID 736 //
     /* 33059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33062 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_h),
     /* 33067 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33070 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33073 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 33076 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 33079 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33083 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33087 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33091 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33095 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8133:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPADD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 33095 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_H),
     /* 33098 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33100 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33102 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33104 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33106 */     GIR_RootConstrainSelectedInstOperands,
     /* 33107 */     // GIR_Coverage, 736,
     /* 33107 */     GIR_EraseRootFromParent_Done,
     /* 33108 */   // Label 925: @33108
     /* 33108 */   GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(33162), // Rule ID 737 //
     /* 33113 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33116 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_w),
     /* 33121 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33124 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33127 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33130 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33133 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33141 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33145 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33149 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8134:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPADD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33149 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_W),
     /* 33152 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33154 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33156 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33158 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33160 */     GIR_RootConstrainSelectedInstOperands,
     /* 33161 */     // GIR_Coverage, 737,
     /* 33161 */     GIR_EraseRootFromParent_Done,
     /* 33162 */   // Label 926: @33162
     /* 33162 */   GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(33216), // Rule ID 738 //
     /* 33167 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33170 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpadd_u_d),
     /* 33175 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 33178 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 33181 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33184 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33187 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33191 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33195 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33199 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33203 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8132:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPADD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33203 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPADD_U_D),
     /* 33206 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33208 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33210 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33212 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33214 */     GIR_RootConstrainSelectedInstOperands,
     /* 33215 */     // GIR_Coverage, 738,
     /* 33215 */     GIR_EraseRootFromParent_Done,
     /* 33216 */   // Label 927: @33216
     /* 33216 */   GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(33270), // Rule ID 739 //
     /* 33221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33224 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_h),
     /* 33229 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33232 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33235 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 33238 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 33241 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33245 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33249 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33253 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33257 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8150:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 33257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_H),
     /* 33260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33262 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33264 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33266 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33268 */     GIR_RootConstrainSelectedInstOperands,
     /* 33269 */     // GIR_Coverage, 739,
     /* 33269 */     GIR_EraseRootFromParent_Done,
     /* 33270 */   // Label 928: @33270
     /* 33270 */   GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(33324), // Rule ID 740 //
     /* 33275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_w),
     /* 33283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33286 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33289 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33292 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33295 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33299 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33303 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33307 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33311 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8151:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33311 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_W),
     /* 33314 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33316 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33318 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33320 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33322 */     GIR_RootConstrainSelectedInstOperands,
     /* 33323 */     // GIR_Coverage, 740,
     /* 33323 */     GIR_EraseRootFromParent_Done,
     /* 33324 */   // Label 929: @33324
     /* 33324 */   GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(33378), // Rule ID 741 //
     /* 33329 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33332 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_s_d),
     /* 33337 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 33340 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 33343 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33346 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33349 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33353 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33357 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33361 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33365 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8149:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33365 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_S_D),
     /* 33368 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33370 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33372 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33374 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33376 */     GIR_RootConstrainSelectedInstOperands,
     /* 33377 */     // GIR_Coverage, 741,
     /* 33377 */     GIR_EraseRootFromParent_Done,
     /* 33378 */   // Label 930: @33378
     /* 33378 */   GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(33432), // Rule ID 742 //
     /* 33383 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33386 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_h),
     /* 33391 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33394 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33397 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 33400 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
     /* 33403 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33407 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33411 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33415 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 33419 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8153:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (DPSUB_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 33419 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_H),
     /* 33422 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33424 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33426 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33428 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33430 */     GIR_RootConstrainSelectedInstOperands,
     /* 33431 */     // GIR_Coverage, 742,
     /* 33431 */     GIR_EraseRootFromParent_Done,
     /* 33432 */   // Label 931: @33432
     /* 33432 */   GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(33486), // Rule ID 743 //
     /* 33437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_w),
     /* 33445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33454 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33457 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33461 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33465 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33469 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33473 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8154:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (DPSUB_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_W),
     /* 33476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33478 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33480 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33482 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33484 */     GIR_RootConstrainSelectedInstOperands,
     /* 33485 */     // GIR_Coverage, 743,
     /* 33485 */     GIR_EraseRootFromParent_Done,
     /* 33486 */   // Label 932: @33486
     /* 33486 */   GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(33540), // Rule ID 744 //
     /* 33491 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33494 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_dpsub_u_d),
     /* 33499 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 33502 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 33505 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33508 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33511 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33515 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 33519 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33523 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33527 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8152:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (DPSUB_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33527 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DPSUB_U_D),
     /* 33530 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33532 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33534 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33536 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33538 */     GIR_RootConstrainSelectedInstOperands,
     /* 33539 */     // GIR_Coverage, 744,
     /* 33539 */     GIR_EraseRootFromParent_Done,
     /* 33540 */   // Label 933: @33540
     /* 33540 */   GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(33594), // Rule ID 911 //
     /* 33545 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33548 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_h),
     /* 33553 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33556 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33559 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33562 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33569 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33573 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33577 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33581 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8320:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADD_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33581 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_H),
     /* 33584 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33586 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33588 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33590 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33592 */     GIR_RootConstrainSelectedInstOperands,
     /* 33593 */     // GIR_Coverage, 911,
     /* 33593 */     GIR_EraseRootFromParent_Done,
     /* 33594 */   // Label 934: @33594
     /* 33594 */   GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(33648), // Rule ID 912 //
     /* 33599 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33602 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_madd_q_w),
     /* 33607 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33610 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33613 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33616 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33619 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33623 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33627 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33631 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33635 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8321:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADD_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33635 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_Q_W),
     /* 33638 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33640 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33642 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33644 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33646 */     GIR_RootConstrainSelectedInstOperands,
     /* 33647 */     // GIR_Coverage, 912,
     /* 33647 */     GIR_EraseRootFromParent_Done,
     /* 33648 */   // Label 935: @33648
     /* 33648 */   GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(33702), // Rule ID 913 //
     /* 33653 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33656 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_h),
     /* 33661 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33664 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33667 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33670 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33677 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33681 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33685 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33689 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8322:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MADDR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33689 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_H),
     /* 33692 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33694 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33696 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33698 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33700 */     GIR_RootConstrainSelectedInstOperands,
     /* 33701 */     // GIR_Coverage, 913,
     /* 33701 */     GIR_EraseRootFromParent_Done,
     /* 33702 */   // Label 936: @33702
     /* 33702 */   GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(33756), // Rule ID 914 //
     /* 33707 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33710 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_maddr_q_w),
     /* 33715 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33718 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33721 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33724 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33731 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33735 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33739 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33743 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8323:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MADDR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADDR_Q_W),
     /* 33746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33748 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33750 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33752 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33754 */     GIR_RootConstrainSelectedInstOperands,
     /* 33755 */     // GIR_Coverage, 914,
     /* 33755 */     GIR_EraseRootFromParent_Done,
     /* 33756 */   // Label 937: @33756
     /* 33756 */   GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(33810), // Rule ID 967 //
     /* 33761 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33764 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_h),
     /* 33769 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33772 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33775 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33778 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33781 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33785 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33789 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33793 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33797 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8384:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUB_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_H),
     /* 33800 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33802 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33804 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33806 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33808 */     GIR_RootConstrainSelectedInstOperands,
     /* 33809 */     // GIR_Coverage, 967,
     /* 33809 */     GIR_EraseRootFromParent_Done,
     /* 33810 */   // Label 938: @33810
     /* 33810 */   GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(33864), // Rule ID 968 //
     /* 33815 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33818 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msub_q_w),
     /* 33823 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33826 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33829 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33832 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33835 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33839 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33843 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33847 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33851 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8385:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUB_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33851 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_Q_W),
     /* 33854 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33856 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33858 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33860 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33862 */     GIR_RootConstrainSelectedInstOperands,
     /* 33863 */     // GIR_Coverage, 968,
     /* 33863 */     GIR_EraseRootFromParent_Done,
     /* 33864 */   // Label 939: @33864
     /* 33864 */   GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(33918), // Rule ID 969 //
     /* 33869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33872 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_h),
     /* 33877 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 33880 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 33883 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 33886 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
     /* 33889 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33893 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33897 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33901 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 33905 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8386:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MSUBR_Q_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 33905 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_H),
     /* 33908 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33910 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33912 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33914 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33916 */     GIR_RootConstrainSelectedInstOperands,
     /* 33917 */     // GIR_Coverage, 969,
     /* 33917 */     GIR_EraseRootFromParent_Done,
     /* 33918 */   // Label 940: @33918
     /* 33918 */   GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(33972), // Rule ID 970 //
     /* 33923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_msubr_q_w),
     /* 33931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 33934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 33937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 33940 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
     /* 33943 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33947 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33951 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33955 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 33959 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8387:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MSUBR_Q_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 33959 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUBR_Q_W),
     /* 33962 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 33964 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 33966 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 33968 */     GIR_RootToRootCopy, /*OpIdx*/4, // wt
     /* 33970 */     GIR_RootConstrainSelectedInstOperands,
     /* 33971 */     // GIR_Coverage, 970,
     /* 33971 */     GIR_EraseRootFromParent_Done,
     /* 33972 */   // Label 941: @33972
     /* 33972 */   GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(34026), // Rule ID 1024 //
     /* 33977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 33980 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_b),
     /* 33985 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
     /* 33988 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 33991 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 33994 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 33997 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 34001 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 34005 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 34009 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34013 */     // (intrinsic_wo_chain:{ *:[v16i8] } 8488:{ *:[iPTR] }, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
     /* 34013 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_B),
     /* 34016 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 34018 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 34020 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 34022 */     GIR_RootToRootCopy, /*OpIdx*/4, // rt
     /* 34024 */     GIR_RootConstrainSelectedInstOperands,
     /* 34025 */     // GIR_Coverage, 1024,
     /* 34025 */     GIR_EraseRootFromParent_Done,
     /* 34026 */   // Label 942: @34026
     /* 34026 */   GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(34080), // Rule ID 1025 //
     /* 34031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 34034 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_h),
     /* 34039 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
     /* 34042 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 34045 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 34048 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 34051 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 34055 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 34059 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 34063 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34067 */     // (intrinsic_wo_chain:{ *:[v8i16] } 8490:{ *:[iPTR] }, MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
     /* 34067 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_H),
     /* 34070 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 34072 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 34074 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 34076 */     GIR_RootToRootCopy, /*OpIdx*/4, // rt
     /* 34078 */     GIR_RootConstrainSelectedInstOperands,
     /* 34079 */     // GIR_Coverage, 1025,
     /* 34079 */     GIR_EraseRootFromParent_Done,
     /* 34080 */   // Label 943: @34080
     /* 34080 */   GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(34134), // Rule ID 1026 //
     /* 34085 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 34088 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_w),
     /* 34093 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 34096 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 34099 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 34102 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 34105 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 34109 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 34113 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 34117 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34121 */     // (intrinsic_wo_chain:{ *:[v4i32] } 8491:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
     /* 34121 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_W),
     /* 34124 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 34126 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 34128 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 34130 */     GIR_RootToRootCopy, /*OpIdx*/4, // rt
     /* 34132 */     GIR_RootConstrainSelectedInstOperands,
     /* 34133 */     // GIR_Coverage, 1026,
     /* 34133 */     GIR_EraseRootFromParent_Done,
     /* 34134 */   // Label 944: @34134
     /* 34134 */   GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(34188), // Rule ID 1027 //
     /* 34139 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 34142 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_sld_d),
     /* 34147 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 34150 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 34153 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 34156 */     GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
     /* 34159 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 34163 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 34167 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 34171 */     GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34175 */     // (intrinsic_wo_chain:{ *:[v2i64] } 8489:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SLD_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, GPR32Opnd:{ *:[i32] }:$rt)
     /* 34175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLD_D),
     /* 34178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 34180 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 34182 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 34184 */     GIR_RootToRootCopy, /*OpIdx*/4, // rt
     /* 34186 */     GIR_RootConstrainSelectedInstOperands,
     /* 34187 */     // GIR_Coverage, 1027,
     /* 34187 */     GIR_EraseRootFromParent_Done,
     /* 34188 */   // Label 945: @34188
     /* 34188 */   GIM_Reject,
     /* 34189 */ // Label 899: @34189
     /* 34189 */ GIM_Reject,
     /* 34190 */ // Label 30: @34190
     /* 34190 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(34221), // Rule ID 429 //
     /* 34195 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
     /* 34198 */   GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_bposge32),
     /* 34203 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 34206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34210 */   // (intrinsic_w_chain:{ *:[i32] } 8035:{ *:[iPTR] })  =>  (BPOSGE32_PSEUDO:{ *:[i32] })
     /* 34210 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BPOSGE32_PSEUDO),
     /* 34213 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 34215 */   GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34219 */   GIR_RootConstrainSelectedInstOperands,
     /* 34220 */   // GIR_Coverage, 429,
     /* 34220 */   GIR_EraseRootFromParent_Done,
     /* 34221 */ // Label 946: @34221
     /* 34221 */ GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(35158),
     /* 34226 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
     /* 34229 */   GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(34270), // Rule ID 516 //
     /* 34234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34237 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
     /* 34242 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 34245 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34249 */     // MIs[0] mask
     /* 34249 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 34252 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
     /* 34257 */     // (intrinsic_w_chain:{ *:[i32] } 8462:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (RDDSP:{ *:[i32] } (timm:{ *:[i32] }):$mask)
     /* 34257 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP),
     /* 34260 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 34262 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /* 34264 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34268 */     GIR_RootConstrainSelectedInstOperands,
     /* 34269 */     // GIR_Coverage, 516,
     /* 34269 */     GIR_EraseRootFromParent_Done,
     /* 34270 */   // Label 948: @34270
     /* 34270 */   GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(34306), // Rule ID 1362 //
     /* 34275 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34278 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_rddsp),
     /* 34283 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 34286 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34290 */     // MIs[0] mask
     /* 34290 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 34293 */     // (intrinsic_w_chain:{ *:[i32] } 8462:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (RDDSP_MM:{ *:[i32] } (timm:{ *:[i32] }):$mask)
     /* 34293 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::RDDSP_MM),
     /* 34296 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 34298 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /* 34300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34304 */     GIR_RootConstrainSelectedInstOperands,
     /* 34305 */     // GIR_Coverage, 1362,
     /* 34305 */     GIR_EraseRootFromParent_Done,
     /* 34306 */   // Label 949: @34306
     /* 34306 */   GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(34347), // Rule ID 517 //
     /* 34311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_NotInMicroMips),
     /* 34314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
     /* 34319 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 34322 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34326 */     // MIs[0] mask
     /* 34326 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 34329 */     GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_timmZExt10),
     /* 34334 */     // (intrinsic_void 8591:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] })<<P:Predicate_timmZExt10>>:$mask)  =>  (WRDSP GPR32Opnd:{ *:[i32] }:$rs, (timm:{ *:[i32] }):$mask)
     /* 34334 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP),
     /* 34337 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34339 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /* 34341 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34345 */     GIR_RootConstrainSelectedInstOperands,
     /* 34346 */     // GIR_Coverage, 517,
     /* 34346 */     GIR_EraseRootFromParent_Done,
     /* 34347 */   // Label 950: @34347
     /* 34347 */   GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(34383), // Rule ID 1373 //
     /* 34352 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34355 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_wrdsp),
     /* 34360 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 34363 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34367 */     // MIs[0] mask
     /* 34367 */     GIM_CheckIsImm, /*MI*/0, /*Op*/2,
     /* 34370 */     // (intrinsic_void 8591:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] })<<P:Predicate_timmZExt7>>:$mask)  =>  (WRDSP_MM GPR32Opnd:{ *:[i32] }:$rt, (timm:{ *:[i32] }):$mask)
     /* 34370 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::WRDSP_MM),
     /* 34373 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 34375 */     GIR_RootToRootCopy, /*OpIdx*/2, // mask
     /* 34377 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34381 */     GIR_RootConstrainSelectedInstOperands,
     /* 34382 */     // GIR_Coverage, 1373,
     /* 34382 */     GIR_EraseRootFromParent_Done,
     /* 34383 */   // Label 951: @34383
     /* 34383 */   GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(34426), // Rule ID 438 //
     /* 34388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34391 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
     /* 34396 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 34399 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34410 */     // (intrinsic_w_chain:{ *:[v2i16] } 7923:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ABSQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34410 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH),
     /* 34413 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 34415 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34417 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34420 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34424 */     GIR_RootConstrainSelectedInstOperands,
     /* 34425 */     // GIR_Coverage, 438,
     /* 34425 */     GIR_EraseRootFromParent_Done,
     /* 34426 */   // Label 952: @34426
     /* 34426 */   GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(34469), // Rule ID 439 //
     /* 34431 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34434 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
     /* 34439 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 34442 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 34445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34449 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34453 */     // (intrinsic_w_chain:{ *:[i32] } 7925:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ABSQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 34453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W),
     /* 34456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 34458 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34460 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34463 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34467 */     GIR_RootConstrainSelectedInstOperands,
     /* 34468 */     // GIR_Coverage, 439,
     /* 34468 */     GIR_EraseRootFromParent_Done,
     /* 34469 */   // Label 953: @34469
     /* 34469 */   GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(34512), // Rule ID 525 //
     /* 34474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 34477 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
     /* 34482 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 34485 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 34488 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34492 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34496 */     // (intrinsic_w_chain:{ *:[v4i8] } 7924:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (ABSQ_S_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt)
     /* 34496 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB),
     /* 34499 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 34501 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34503 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34506 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34510 */     GIR_RootConstrainSelectedInstOperands,
     /* 34511 */     // GIR_Coverage, 525,
     /* 34511 */     GIR_EraseRootFromParent_Done,
     /* 34512 */   // Label 954: @34512
     /* 34512 */   GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(34555), // Rule ID 1305 //
     /* 34517 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34520 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_ph),
     /* 34525 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 34528 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34539 */     // (intrinsic_w_chain:{ *:[v2i16] } 7923:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs)  =>  (ABSQ_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs)
     /* 34539 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_PH_MM),
     /* 34542 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 34544 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 34546 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34549 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34553 */     GIR_RootConstrainSelectedInstOperands,
     /* 34554 */     // GIR_Coverage, 1305,
     /* 34554 */     GIR_EraseRootFromParent_Done,
     /* 34555 */   // Label 955: @34555
     /* 34555 */   GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(34598), // Rule ID 1306 //
     /* 34560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34563 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_w),
     /* 34568 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 34571 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 34574 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34578 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 34582 */     // (intrinsic_w_chain:{ *:[i32] } 7925:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ABSQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 34582 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_W_MM),
     /* 34585 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 34587 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 34589 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34592 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34596 */     GIR_RootConstrainSelectedInstOperands,
     /* 34597 */     // GIR_Coverage, 1306,
     /* 34597 */     GIR_EraseRootFromParent_Done,
     /* 34598 */   // Label 956: @34598
     /* 34598 */   GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(34641), // Rule ID 1386 //
     /* 34603 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 34606 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_absq_s_qb),
     /* 34611 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 34614 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 34617 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34621 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34625 */     // (intrinsic_w_chain:{ *:[v4i8] } 7924:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs)  =>  (ABSQ_S_QB_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs)
     /* 34625 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ABSQ_S_QB_MMR2),
     /* 34628 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 34630 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 34632 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 34635 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34639 */     GIR_RootConstrainSelectedInstOperands,
     /* 34640 */     // GIR_Coverage, 1386,
     /* 34640 */     GIR_EraseRootFromParent_Done,
     /* 34641 */   // Label 957: @34641
     /* 34641 */   GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(34684), // Rule ID 492 //
     /* 34646 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34649 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
     /* 34654 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 34657 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 34660 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34664 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34668 */     // (intrinsic_void 8101:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 34668 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB),
     /* 34671 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34673 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34675 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34678 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34682 */     GIR_RootConstrainSelectedInstOperands,
     /* 34683 */     // GIR_Coverage, 492,
     /* 34683 */     GIR_EraseRootFromParent_Done,
     /* 34684 */   // Label 958: @34684
     /* 34684 */   GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(34727), // Rule ID 493 //
     /* 34689 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34692 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
     /* 34697 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 34700 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 34703 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34707 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34711 */     // (intrinsic_void 8103:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 34711 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB),
     /* 34714 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34716 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34718 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34721 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34725 */     GIR_RootConstrainSelectedInstOperands,
     /* 34726 */     // GIR_Coverage, 493,
     /* 34726 */     GIR_EraseRootFromParent_Done,
     /* 34727 */   // Label 959: @34727
     /* 34727 */   GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(34770), // Rule ID 494 //
     /* 34732 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34735 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
     /* 34740 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 34743 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 34746 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34750 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34754 */     // (intrinsic_void 8102:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 34754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB),
     /* 34757 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34759 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34761 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34764 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34768 */     GIR_RootConstrainSelectedInstOperands,
     /* 34769 */     // GIR_Coverage, 494,
     /* 34769 */     GIR_EraseRootFromParent_Done,
     /* 34770 */   // Label 960: @34770
     /* 34770 */   GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(34813), // Rule ID 498 //
     /* 34775 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34778 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
     /* 34783 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 34786 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34789 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34793 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34797 */     // (intrinsic_void 8092:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34797 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH),
     /* 34800 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34802 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34804 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34807 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34811 */     GIR_RootConstrainSelectedInstOperands,
     /* 34812 */     // GIR_Coverage, 498,
     /* 34812 */     GIR_EraseRootFromParent_Done,
     /* 34813 */   // Label 961: @34813
     /* 34813 */   GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(34856), // Rule ID 499 //
     /* 34818 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34821 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
     /* 34826 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 34829 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34832 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34836 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34840 */     // (intrinsic_void 8094:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34840 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH),
     /* 34843 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34845 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34847 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34850 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34854 */     GIR_RootConstrainSelectedInstOperands,
     /* 34855 */     // GIR_Coverage, 499,
     /* 34855 */     GIR_EraseRootFromParent_Done,
     /* 34856 */   // Label 962: @34856
     /* 34856 */   GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(34899), // Rule ID 500 //
     /* 34861 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 34864 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
     /* 34869 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 34872 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34883 */     // (intrinsic_void 8093:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34883 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH),
     /* 34886 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34888 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34890 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34893 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34897 */     GIR_RootConstrainSelectedInstOperands,
     /* 34898 */     // GIR_Coverage, 500,
     /* 34898 */     GIR_EraseRootFromParent_Done,
     /* 34899 */   // Label 963: @34899
     /* 34899 */   GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(34942), // Rule ID 1377 //
     /* 34904 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34907 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_eq_ph),
     /* 34912 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 34915 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34918 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34922 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34926 */     // (intrinsic_void 8092:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_EQ_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_PH_MM),
     /* 34929 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34931 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34933 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34936 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34940 */     GIR_RootConstrainSelectedInstOperands,
     /* 34941 */     // GIR_Coverage, 1377,
     /* 34941 */     GIR_EraseRootFromParent_Done,
     /* 34942 */   // Label 964: @34942
     /* 34942 */   GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(34985), // Rule ID 1378 //
     /* 34947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34950 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_lt_ph),
     /* 34955 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 34958 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 34961 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34965 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 34969 */     // (intrinsic_void 8094:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LT_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 34969 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_PH_MM),
     /* 34972 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 34974 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 34976 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 34979 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 34983 */     GIR_RootConstrainSelectedInstOperands,
     /* 34984 */     // GIR_Coverage, 1378,
     /* 34984 */     GIR_EraseRootFromParent_Done,
     /* 34985 */   // Label 965: @34985
     /* 34985 */   GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(35028), // Rule ID 1379 //
     /* 34990 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 34993 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmp_le_ph),
     /* 34998 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16,
     /* 35001 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35004 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35008 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35012 */     // (intrinsic_void 8093:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (CMP_LE_PH_MM DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 35012 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_PH_MM),
     /* 35015 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 35017 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35019 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 35022 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35026 */     GIR_RootConstrainSelectedInstOperands,
     /* 35027 */     // GIR_Coverage, 1379,
     /* 35027 */     GIR_EraseRootFromParent_Done,
     /* 35028 */   // Label 966: @35028
     /* 35028 */   GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(35071), // Rule ID 1383 //
     /* 35033 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 35036 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_eq_qb),
     /* 35041 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 35044 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35047 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35055 */     // (intrinsic_void 8101:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_EQ_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 35055 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_EQ_QB_MM),
     /* 35058 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 35060 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35062 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 35065 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35069 */     GIR_RootConstrainSelectedInstOperands,
     /* 35070 */     // GIR_Coverage, 1383,
     /* 35070 */     GIR_EraseRootFromParent_Done,
     /* 35071 */   // Label 967: @35071
     /* 35071 */   GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(35114), // Rule ID 1384 //
     /* 35076 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 35079 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_lt_qb),
     /* 35084 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 35087 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35090 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35094 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35098 */     // (intrinsic_void 8103:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LT_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 35098 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LT_QB_MM),
     /* 35101 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 35103 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35105 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 35108 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35112 */     GIR_RootConstrainSelectedInstOperands,
     /* 35113 */     // GIR_Coverage, 1384,
     /* 35113 */     GIR_EraseRootFromParent_Done,
     /* 35114 */   // Label 968: @35114
     /* 35114 */   GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35157), // Rule ID 1385 //
     /* 35119 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 35122 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_cmpu_le_qb),
     /* 35127 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s8,
     /* 35130 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35133 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35141 */     // (intrinsic_void 8102:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPU_LE_QB_MM DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 35141 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPU_LE_QB_MM),
     /* 35144 */     GIR_RootToRootCopy, /*OpIdx*/1, // rs
     /* 35146 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35148 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 35151 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35155 */     GIR_RootConstrainSelectedInstOperands,
     /* 35156 */     // GIR_Coverage, 1385,
     /* 35156 */     GIR_EraseRootFromParent_Done,
     /* 35157 */   // Label 969: @35157
     /* 35157 */   GIM_Reject,
     /* 35158 */ // Label 947: @35158
     /* 35158 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(39283),
     /* 35163 */   GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
     /* 35166 */   GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(35230), // Rule ID 457 //
     /* 35171 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35174 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
     /* 35179 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35182 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35185 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35188 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35192 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35196 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35200 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35204 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 35208 */     // MIs[1] Operand 1
     /* 35208 */     // No operand predicates
     /* 35208 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35210 */     // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$rs_sa)  =>  (SHLL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, (imm:{ *:[i32] }):$rs_sa)
     /* 35210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH),
     /* 35213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35215 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35217 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
     /* 35220 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35223 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 35228 */     GIR_RootConstrainSelectedInstOperands,
     /* 35229 */     // GIR_Coverage, 457,
     /* 35229 */     GIR_EraseRootFromParent_Done,
     /* 35230 */   // Label 971: @35230
     /* 35230 */   GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35294), // Rule ID 462 //
     /* 35235 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35238 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
     /* 35243 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 35246 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35249 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35252 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35256 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35260 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35264 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35268 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 35272 */     // MIs[1] Operand 1
     /* 35272 */     // No operand predicates
     /* 35272 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35274 */     // (intrinsic_w_chain:{ *:[i32] } 8480:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$rs_sa)  =>  (SHLL_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$rs_sa)
     /* 35274 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W),
     /* 35277 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35279 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35281 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rs_sa
     /* 35284 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35287 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 35292 */     GIR_RootConstrainSelectedInstOperands,
     /* 35293 */     // GIR_Coverage, 462,
     /* 35293 */     GIR_EraseRootFromParent_Done,
     /* 35294 */   // Label 972: @35294
     /* 35294 */   GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(35358), // Rule ID 1314 //
     /* 35299 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 35302 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
     /* 35307 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35310 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35313 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35316 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35324 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35328 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35332 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 35336 */     // MIs[1] Operand 1
     /* 35336 */     // No operand predicates
     /* 35336 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35338 */     // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$sa)  =>  (SHLL_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, (imm:{ *:[i32] }):$sa)
     /* 35338 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_PH_MM),
     /* 35341 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 35343 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35345 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
     /* 35348 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35351 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 35356 */     GIR_RootConstrainSelectedInstOperands,
     /* 35357 */     // GIR_Coverage, 1314,
     /* 35357 */     GIR_EraseRootFromParent_Done,
     /* 35358 */   // Label 973: @35358
     /* 35358 */   GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(35422), // Rule ID 1319 //
     /* 35363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 35366 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
     /* 35371 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 35374 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35377 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35384 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35396 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 35400 */     // MIs[1] Operand 1
     /* 35400 */     // No operand predicates
     /* 35400 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35402 */     // (intrinsic_w_chain:{ *:[i32] } 8480:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$sa)  =>  (SHLL_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$sa)
     /* 35402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_S_W_MM),
     /* 35405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 35407 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35409 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // sa
     /* 35412 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35415 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
     /* 35420 */     GIR_RootConstrainSelectedInstOperands,
     /* 35421 */     // GIR_Coverage, 1319,
     /* 35421 */     GIR_EraseRootFromParent_Done,
     /* 35422 */   // Label 974: @35422
     /* 35422 */   GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(35477), // Rule ID 2069 //
     /* 35427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35430 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
     /* 35435 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35438 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35441 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35444 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35448 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35452 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35456 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 35460 */     // MIs[1] Operand 1
     /* 35460 */     // No operand predicates
     /* 35460 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35462 */     // (intrinsic_w_chain:{ *:[v2i16] } 8477:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)  =>  (SHLL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$shamt)
     /* 35462 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_PH),
     /* 35465 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35467 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 35469 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 35472 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35475 */     GIR_RootConstrainSelectedInstOperands,
     /* 35476 */     // GIR_Coverage, 2069,
     /* 35476 */     GIR_EraseRootFromParent_Done,
     /* 35477 */   // Label 975: @35477
     /* 35477 */   GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(35532), // Rule ID 2075 //
     /* 35482 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35485 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
     /* 35490 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 35493 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35496 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35499 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35503 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
     /* 35507 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 35511 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt3),
     /* 35515 */     // MIs[1] Operand 1
     /* 35515 */     // No operand predicates
     /* 35515 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 35517 */     // (intrinsic_w_chain:{ *:[v4i8] } 8478:{ *:[iPTR] }, v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)  =>  (SHLL_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, (imm:{ *:[i32] })<<P:Predicate_immZExt3>>:$shamt)
     /* 35517 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLL_QB),
     /* 35520 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35522 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 35524 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 35527 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35530 */     GIR_RootConstrainSelectedInstOperands,
     /* 35531 */     // GIR_Coverage, 2075,
     /* 35531 */     GIR_EraseRootFromParent_Done,
     /* 35532 */   // Label 976: @35532
     /* 35532 */   GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(35584), // Rule ID 434 //
     /* 35537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35540 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
     /* 35545 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 35548 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35558 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35562 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35566 */     // (intrinsic_w_chain:{ *:[i32] } 7932:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 35566 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W),
     /* 35569 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35571 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35573 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 35575 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 35578 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35582 */     GIR_RootConstrainSelectedInstOperands,
     /* 35583 */     // GIR_Coverage, 434,
     /* 35583 */     GIR_EraseRootFromParent_Done,
     /* 35584 */   // Label 977: @35584
     /* 35584 */   GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(35636), // Rule ID 435 //
     /* 35589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35592 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
     /* 35597 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 35600 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35603 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35606 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35610 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35614 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35618 */     // (intrinsic_w_chain:{ *:[i32] } 8552:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 35618 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W),
     /* 35621 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35623 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35625 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 35627 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 35630 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35634 */     GIR_RootConstrainSelectedInstOperands,
     /* 35635 */     // GIR_Coverage, 435,
     /* 35635 */     GIR_EraseRootFromParent_Done,
     /* 35636 */   // Label 978: @35636
     /* 35636 */   GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(35688), // Rule ID 442 //
     /* 35641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35644 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
     /* 35649 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35652 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35655 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35658 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35662 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35666 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35670 */     // (intrinsic_w_chain:{ *:[v2i16] } 8458:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 35670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W),
     /* 35673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35675 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35677 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 35679 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35682 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35686 */     GIR_RootConstrainSelectedInstOperands,
     /* 35687 */     // GIR_Coverage, 442,
     /* 35687 */     GIR_EraseRootFromParent_Done,
     /* 35688 */   // Label 979: @35688
     /* 35688 */   GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(35740), // Rule ID 443 //
     /* 35693 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35696 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
     /* 35701 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 35704 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35707 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 35710 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35714 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35718 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35722 */     // (intrinsic_w_chain:{ *:[v4i8] } 8459:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 35722 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH),
     /* 35725 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35727 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35729 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 35731 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35734 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35738 */     GIR_RootConstrainSelectedInstOperands,
     /* 35739 */     // GIR_Coverage, 443,
     /* 35739 */     GIR_EraseRootFromParent_Done,
     /* 35740 */   // Label 980: @35740
     /* 35740 */   GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(35792), // Rule ID 454 //
     /* 35745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35748 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
     /* 35753 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 35756 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35759 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35762 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35766 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35770 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35774 */     // (intrinsic_w_chain:{ *:[v4i8] } 8478:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 35774 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB),
     /* 35777 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35779 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35781 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 35783 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35786 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35790 */     GIR_RootConstrainSelectedInstOperands,
     /* 35791 */     // GIR_Coverage, 454,
     /* 35791 */     GIR_EraseRootFromParent_Done,
     /* 35792 */   // Label 981: @35792
     /* 35792 */   GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(35844), // Rule ID 456 //
     /* 35797 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35800 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
     /* 35805 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35808 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35811 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35814 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35818 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35822 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35826 */     // (intrinsic_w_chain:{ *:[v2i16] } 8477:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 35826 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH),
     /* 35829 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35831 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35833 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 35835 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35838 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35842 */     GIR_RootConstrainSelectedInstOperands,
     /* 35843 */     // GIR_Coverage, 456,
     /* 35843 */     GIR_EraseRootFromParent_Done,
     /* 35844 */   // Label 982: @35844
     /* 35844 */   GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(35896), // Rule ID 458 //
     /* 35849 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35852 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
     /* 35857 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35860 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 35863 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35866 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35870 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35874 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35878 */     // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 35878 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH),
     /* 35881 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35883 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35885 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 35887 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35890 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35894 */     GIR_RootConstrainSelectedInstOperands,
     /* 35895 */     // GIR_Coverage, 458,
     /* 35895 */     GIR_EraseRootFromParent_Done,
     /* 35896 */   // Label 983: @35896
     /* 35896 */   GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(35948), // Rule ID 463 //
     /* 35901 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35904 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
     /* 35909 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 35912 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 35915 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 35918 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35922 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35926 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 35930 */     // (intrinsic_w_chain:{ *:[i32] } 8480:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)  =>  (SHLLV_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs_sa)
     /* 35930 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W),
     /* 35933 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35935 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 35937 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs_sa
     /* 35939 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 35942 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35946 */     GIR_RootConstrainSelectedInstOperands,
     /* 35947 */     // GIR_Coverage, 463,
     /* 35947 */     GIR_EraseRootFromParent_Done,
     /* 35948 */   // Label 984: @35948
     /* 35948 */   GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(36000), // Rule ID 466 //
     /* 35953 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 35956 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
     /* 35961 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 35964 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 35967 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 35970 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35974 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35978 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 35982 */     // (intrinsic_w_chain:{ *:[v2i16] } 8400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 35982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL),
     /* 35985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 35987 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 35989 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 35991 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 35994 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 35998 */     GIR_RootConstrainSelectedInstOperands,
     /* 35999 */     // GIR_Coverage, 466,
     /* 35999 */     GIR_EraseRootFromParent_Done,
     /* 36000 */   // Label 985: @36000
     /* 36000 */   GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(36052), // Rule ID 467 //
     /* 36005 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36008 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
     /* 36013 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36016 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36019 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36022 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36026 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36030 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36034 */     // (intrinsic_w_chain:{ *:[v2i16] } 8401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36034 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR),
     /* 36037 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36039 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36041 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36043 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36046 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36050 */     GIR_RootConstrainSelectedInstOperands,
     /* 36051 */     // GIR_Coverage, 467,
     /* 36051 */     GIR_EraseRootFromParent_Done,
     /* 36052 */   // Label 986: @36052
     /* 36052 */   GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(36104), // Rule ID 468 //
     /* 36057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36060 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
     /* 36065 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36068 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36071 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36078 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36082 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36086 */     // (intrinsic_w_chain:{ *:[i32] } 8398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36086 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL),
     /* 36089 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36091 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36093 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36095 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36098 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36102 */     GIR_RootConstrainSelectedInstOperands,
     /* 36103 */     // GIR_Coverage, 468,
     /* 36103 */     GIR_EraseRootFromParent_Done,
     /* 36104 */   // Label 987: @36104
     /* 36104 */   GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(36156), // Rule ID 469 //
     /* 36109 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36112 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
     /* 36117 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36120 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36123 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36126 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36130 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36134 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36138 */     // (intrinsic_w_chain:{ *:[i32] } 8399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36138 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR),
     /* 36141 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36143 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36145 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36147 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36150 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36154 */     GIR_RootConstrainSelectedInstOperands,
     /* 36155 */     // GIR_Coverage, 469,
     /* 36155 */     GIR_EraseRootFromParent_Done,
     /* 36156 */   // Label 988: @36156
     /* 36156 */   GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(36208), // Rule ID 470 //
     /* 36161 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36164 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
     /* 36169 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36172 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36175 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36178 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36182 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36186 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36190 */     // (intrinsic_w_chain:{ *:[v2i16] } 8402:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36190 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH),
     /* 36193 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36195 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36197 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36199 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36202 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36206 */     GIR_RootConstrainSelectedInstOperands,
     /* 36207 */     // GIR_Coverage, 470,
     /* 36207 */     GIR_EraseRootFromParent_Done,
     /* 36208 */   // Label 989: @36208
     /* 36208 */   GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(36257), // Rule ID 495 //
     /* 36213 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36216 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
     /* 36221 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36224 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36227 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36230 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36234 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36238 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36242 */     // (intrinsic_w_chain:{ *:[i32] } 8098:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36242 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB),
     /* 36245 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36247 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36249 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36251 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36255 */     GIR_RootConstrainSelectedInstOperands,
     /* 36256 */     // GIR_Coverage, 495,
     /* 36256 */     GIR_EraseRootFromParent_Done,
     /* 36257 */   // Label 990: @36257
     /* 36257 */   GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(36306), // Rule ID 496 //
     /* 36262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36265 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
     /* 36270 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36273 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36276 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36279 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36283 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36287 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36291 */     // (intrinsic_w_chain:{ *:[i32] } 8100:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36291 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB),
     /* 36294 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36296 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36298 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36300 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36304 */     GIR_RootConstrainSelectedInstOperands,
     /* 36305 */     // GIR_Coverage, 496,
     /* 36305 */     GIR_EraseRootFromParent_Done,
     /* 36306 */   // Label 991: @36306
     /* 36306 */   GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(36355), // Rule ID 497 //
     /* 36311 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36314 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
     /* 36319 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36322 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36325 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36328 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36336 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36340 */     // (intrinsic_w_chain:{ *:[i32] } 8099:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36340 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB),
     /* 36343 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36345 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36347 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36349 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36353 */     GIR_RootConstrainSelectedInstOperands,
     /* 36354 */     // GIR_Coverage, 497,
     /* 36354 */     GIR_EraseRootFromParent_Done,
     /* 36355 */   // Label 992: @36355
     /* 36355 */   GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(36404), // Rule ID 507 //
     /* 36360 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36363 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
     /* 36368 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 36371 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36374 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36377 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36381 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36385 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36389 */     // (intrinsic_w_chain:{ *:[v4i8] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB),
     /* 36392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36394 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36396 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36398 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36402 */     GIR_RootConstrainSelectedInstOperands,
     /* 36403 */     // GIR_Coverage, 507,
     /* 36403 */     GIR_EraseRootFromParent_Done,
     /* 36404 */   // Label 993: @36404
     /* 36404 */   GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(36453), // Rule ID 508 //
     /* 36409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36412 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
     /* 36417 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36420 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36423 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36426 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36430 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36434 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36438 */     // (intrinsic_w_chain:{ *:[v2i16] } 8441:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH),
     /* 36441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36443 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36445 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36447 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36451 */     GIR_RootConstrainSelectedInstOperands,
     /* 36452 */     // GIR_Coverage, 508,
     /* 36452 */     GIR_EraseRootFromParent_Done,
     /* 36453 */   // Label 994: @36453
     /* 36453 */   GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(36502), // Rule ID 512 //
     /* 36458 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 36461 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
     /* 36466 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36469 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 36472 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 36475 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36479 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36483 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36487 */     // (intrinsic_w_chain:{ *:[i32] } 8300:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
     /* 36487 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV),
     /* 36490 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 36492 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 36494 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 36496 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36500 */     GIR_RootConstrainSelectedInstOperands,
     /* 36501 */     // GIR_Coverage, 512,
     /* 36501 */     GIR_EraseRootFromParent_Done,
     /* 36502 */   // Label 995: @36502
     /* 36502 */   GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(36554), // Rule ID 518 //
     /* 36507 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36510 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
     /* 36515 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36518 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36521 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36528 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36532 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36536 */     // (intrinsic_w_chain:{ *:[v2i16] } 7950:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36536 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH),
     /* 36539 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36541 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36543 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36545 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 36548 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36552 */     GIR_RootConstrainSelectedInstOperands,
     /* 36553 */     // GIR_Coverage, 518,
     /* 36553 */     GIR_EraseRootFromParent_Done,
     /* 36554 */   // Label 996: @36554
     /* 36554 */   GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(36606), // Rule ID 519 //
     /* 36559 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36562 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
     /* 36567 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36570 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36573 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36576 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36580 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36584 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36588 */     // (intrinsic_w_chain:{ *:[v2i16] } 7952:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36588 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH),
     /* 36591 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36593 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36595 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36597 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 36600 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36604 */     GIR_RootConstrainSelectedInstOperands,
     /* 36605 */     // GIR_Coverage, 519,
     /* 36605 */     GIR_EraseRootFromParent_Done,
     /* 36606 */   // Label 997: @36606
     /* 36606 */   GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36658), // Rule ID 520 //
     /* 36611 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36614 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
     /* 36619 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36622 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36625 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36632 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36636 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36640 */     // (intrinsic_w_chain:{ *:[v2i16] } 8573:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36640 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH),
     /* 36643 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36645 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36647 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36649 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 36652 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36656 */     GIR_RootConstrainSelectedInstOperands,
     /* 36657 */     // GIR_Coverage, 520,
     /* 36657 */     GIR_EraseRootFromParent_Done,
     /* 36658 */   // Label 998: @36658
     /* 36658 */   GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(36710), // Rule ID 521 //
     /* 36663 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36666 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
     /* 36671 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36674 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36677 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36680 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36684 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36688 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36692 */     // (intrinsic_w_chain:{ *:[v2i16] } 8575:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36692 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH),
     /* 36695 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36697 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36699 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36701 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 36704 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36708 */     GIR_RootConstrainSelectedInstOperands,
     /* 36709 */     // GIR_Coverage, 521,
     /* 36709 */     GIR_EraseRootFromParent_Done,
     /* 36710 */   // Label 999: @36710
     /* 36710 */   GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36762), // Rule ID 522 //
     /* 36715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36718 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
     /* 36723 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36726 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36729 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36732 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36736 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36740 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36744 */     // (intrinsic_w_chain:{ *:[i32] } 8095:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36744 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB),
     /* 36747 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36749 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36751 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36753 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 36756 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36760 */     GIR_RootConstrainSelectedInstOperands,
     /* 36761 */     // GIR_Coverage, 522,
     /* 36761 */     GIR_EraseRootFromParent_Done,
     /* 36762 */   // Label 1000: @36762
     /* 36762 */   GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36814), // Rule ID 523 //
     /* 36767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36770 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
     /* 36775 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36778 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36781 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36784 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36792 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36796 */     // (intrinsic_w_chain:{ *:[i32] } 8097:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB),
     /* 36799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36801 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36803 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36805 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 36808 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36812 */     GIR_RootConstrainSelectedInstOperands,
     /* 36813 */     // GIR_Coverage, 523,
     /* 36813 */     GIR_EraseRootFromParent_Done,
     /* 36814 */   // Label 1001: @36814
     /* 36814 */   GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36866), // Rule ID 524 //
     /* 36819 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36822 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
     /* 36827 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36830 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 36833 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 36836 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36840 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36844 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36848 */     // (intrinsic_w_chain:{ *:[i32] } 8096:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 36848 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB),
     /* 36851 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36853 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36855 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36857 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 36860 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36864 */     GIR_RootConstrainSelectedInstOperands,
     /* 36865 */     // GIR_Coverage, 524,
     /* 36865 */     GIR_EraseRootFromParent_Done,
     /* 36866 */   // Label 1002: @36866
     /* 36866 */   GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36918), // Rule ID 538 //
     /* 36871 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36874 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
     /* 36879 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 36882 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 36885 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 36888 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36892 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36896 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 36900 */     // (intrinsic_w_chain:{ *:[v2i16] } 8397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 36900 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH),
     /* 36903 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36905 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36907 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36909 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36912 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36916 */     GIR_RootConstrainSelectedInstOperands,
     /* 36917 */     // GIR_Coverage, 538,
     /* 36917 */     GIR_EraseRootFromParent_Done,
     /* 36918 */   // Label 1003: @36918
     /* 36918 */   GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36970), // Rule ID 539 //
     /* 36923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36926 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
     /* 36931 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36934 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 36937 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 36940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36944 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36948 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36952 */     // (intrinsic_w_chain:{ *:[i32] } 8405:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 36952 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W),
     /* 36955 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 36957 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 36959 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 36961 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 36964 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 36968 */     GIR_RootConstrainSelectedInstOperands,
     /* 36969 */     // GIR_Coverage, 539,
     /* 36969 */     GIR_EraseRootFromParent_Done,
     /* 36970 */   // Label 1004: @36970
     /* 36970 */   GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(37022), // Rule ID 540 //
     /* 36975 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 36978 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
     /* 36983 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 36986 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 36989 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 36992 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 36996 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37000 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37004 */     // (intrinsic_w_chain:{ *:[i32] } 8403:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 37004 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W),
     /* 37007 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37009 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37011 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37013 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37020 */     GIR_RootConstrainSelectedInstOperands,
     /* 37021 */     // GIR_Coverage, 540,
     /* 37021 */     GIR_EraseRootFromParent_Done,
     /* 37022 */   // Label 1005: @37022
     /* 37022 */   GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(37074), // Rule ID 541 //
     /* 37027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 37030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
     /* 37035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37038 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37041 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37044 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37048 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37052 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37056 */     // (intrinsic_w_chain:{ *:[v2i16] } 8404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37056 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH),
     /* 37059 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37061 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37063 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37065 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37068 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37072 */     GIR_RootConstrainSelectedInstOperands,
     /* 37073 */     // GIR_Coverage, 541,
     /* 37073 */     GIR_EraseRootFromParent_Done,
     /* 37074 */   // Label 1006: @37074
     /* 37074 */   GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(37123), // Rule ID 551 //
     /* 37079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 37082 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
     /* 37087 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 37090 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37093 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37096 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37104 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37108 */     // (intrinsic_w_chain:{ *:[v4i8] } 8453:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37108 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH),
     /* 37111 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37113 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37115 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37117 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37121 */     GIR_RootConstrainSelectedInstOperands,
     /* 37122 */     // GIR_Coverage, 551,
     /* 37122 */     GIR_EraseRootFromParent_Done,
     /* 37123 */   // Label 1007: @37123
     /* 37123 */   GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(37175), // Rule ID 1299 //
     /* 37128 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37131 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addq_s_w),
     /* 37136 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37139 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 37142 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37145 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37149 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37153 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37157 */     // (intrinsic_w_chain:{ *:[i32] } 7932:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (ADDQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 37157 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDQ_S_W_MM),
     /* 37160 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37162 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37164 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37166 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 37169 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37173 */     GIR_RootConstrainSelectedInstOperands,
     /* 37174 */     // GIR_Coverage, 1299,
     /* 37174 */     GIR_EraseRootFromParent_Done,
     /* 37175 */   // Label 1008: @37175
     /* 37175 */   GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(37224), // Rule ID 1307 //
     /* 37180 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37183 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_insv),
     /* 37188 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37191 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 37194 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37197 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37201 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37205 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37209 */     // (intrinsic_w_chain:{ *:[i32] } 8300:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)  =>  (INSV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$src, GPR32Opnd:{ *:[i32] }:$rs)
     /* 37209 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSV_MM),
     /* 37212 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 37214 */     GIR_RootToRootCopy, /*OpIdx*/2, // src
     /* 37216 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 37218 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37222 */     GIR_RootConstrainSelectedInstOperands,
     /* 37223 */     // GIR_Coverage, 1307,
     /* 37223 */     GIR_EraseRootFromParent_Done,
     /* 37224 */   // Label 1009: @37224
     /* 37224 */   GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(37276), // Rule ID 1315 //
     /* 37229 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37232 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_ph),
     /* 37237 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37240 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37243 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37246 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37250 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37254 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37258 */     // (intrinsic_w_chain:{ *:[v2i16] } 8477:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 37258 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_PH_MM),
     /* 37261 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37263 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 37265 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 37267 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37270 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37274 */     GIR_RootConstrainSelectedInstOperands,
     /* 37275 */     // GIR_Coverage, 1315,
     /* 37275 */     GIR_EraseRootFromParent_Done,
     /* 37276 */   // Label 1010: @37276
     /* 37276 */   GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(37328), // Rule ID 1316 //
     /* 37281 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37284 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_ph),
     /* 37289 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37292 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37295 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37298 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37302 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37306 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37310 */     // (intrinsic_w_chain:{ *:[v2i16] } 8479:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 37310 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_PH_MM),
     /* 37313 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37315 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 37317 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 37319 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37322 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37326 */     GIR_RootConstrainSelectedInstOperands,
     /* 37327 */     // GIR_Coverage, 1316,
     /* 37327 */     GIR_EraseRootFromParent_Done,
     /* 37328 */   // Label 1011: @37328
     /* 37328 */   GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(37380), // Rule ID 1317 //
     /* 37333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37336 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_qb),
     /* 37341 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 37344 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 37347 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37350 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37354 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37358 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37362 */     // (intrinsic_w_chain:{ *:[v4i8] } 8478:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 37362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_QB_MM),
     /* 37365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37367 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 37369 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 37371 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37374 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37378 */     GIR_RootConstrainSelectedInstOperands,
     /* 37379 */     // GIR_Coverage, 1317,
     /* 37379 */     GIR_EraseRootFromParent_Done,
     /* 37380 */   // Label 1012: @37380
     /* 37380 */   GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(37432), // Rule ID 1318 //
     /* 37385 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37388 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_shll_s_w),
     /* 37393 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37396 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 37399 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37402 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37406 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37410 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37414 */     // (intrinsic_w_chain:{ *:[i32] } 8480:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SHLLV_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 37414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SHLLV_S_W_MM),
     /* 37417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37419 */     GIR_RootToRootCopy, /*OpIdx*/2, // rt
     /* 37421 */     GIR_RootToRootCopy, /*OpIdx*/3, // rs
     /* 37423 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37426 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37430 */     GIR_RootConstrainSelectedInstOperands,
     /* 37431 */     // GIR_Coverage, 1318,
     /* 37431 */     GIR_EraseRootFromParent_Done,
     /* 37432 */   // Label 1013: @37432
     /* 37432 */   GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(37484), // Rule ID 1337 //
     /* 37437 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37440 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subq_s_w),
     /* 37445 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37448 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 37451 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37454 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37458 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37462 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37466 */     // (intrinsic_w_chain:{ *:[i32] } 8552:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (SUBQ_S_W_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 37466 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBQ_S_W_MM),
     /* 37469 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37471 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37473 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37475 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 37478 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37482 */     GIR_RootConstrainSelectedInstOperands,
     /* 37483 */     // GIR_Coverage, 1337,
     /* 37483 */     GIR_EraseRootFromParent_Done,
     /* 37484 */   // Label 1014: @37484
     /* 37484 */   GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(37536), // Rule ID 1343 //
     /* 37489 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37492 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phl),
     /* 37497 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37500 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37503 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37510 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37514 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37518 */     // (intrinsic_w_chain:{ *:[i32] } 8398:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHL_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37518 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHL_MM),
     /* 37521 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37523 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37525 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37527 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37530 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37534 */     GIR_RootConstrainSelectedInstOperands,
     /* 37535 */     // GIR_Coverage, 1343,
     /* 37535 */     GIR_EraseRootFromParent_Done,
     /* 37536 */   // Label 1015: @37536
     /* 37536 */   GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(37588), // Rule ID 1344 //
     /* 37541 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37544 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleq_s_w_phr),
     /* 37549 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37552 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37555 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37558 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37566 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37570 */     // (intrinsic_w_chain:{ *:[i32] } 8399:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEQ_S_W_PHR_MM:{ *:[i32] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEQ_S_W_PHR_MM),
     /* 37573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37575 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37577 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37579 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37582 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37586 */     GIR_RootConstrainSelectedInstOperands,
     /* 37587 */     // GIR_Coverage, 1344,
     /* 37587 */     GIR_EraseRootFromParent_Done,
     /* 37588 */   // Label 1016: @37588
     /* 37588 */   GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37640), // Rule ID 1345 //
     /* 37593 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37596 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbl),
     /* 37601 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37604 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 37607 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37610 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37614 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37618 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37622 */     // (intrinsic_w_chain:{ *:[v2i16] } 8400:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBL_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37622 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBL_MM),
     /* 37625 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37627 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37629 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37631 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37634 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37638 */     GIR_RootConstrainSelectedInstOperands,
     /* 37639 */     // GIR_Coverage, 1345,
     /* 37639 */     GIR_EraseRootFromParent_Done,
     /* 37640 */   // Label 1017: @37640
     /* 37640 */   GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(37692), // Rule ID 1346 //
     /* 37645 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37648 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_muleu_s_ph_qbr),
     /* 37653 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37656 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 37659 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37662 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37666 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37670 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37674 */     // (intrinsic_w_chain:{ *:[v2i16] } 8401:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULEU_S_PH_QBR_MM:{ *:[v2i16] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37674 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULEU_S_PH_QBR_MM),
     /* 37677 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37679 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37681 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37683 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37686 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37690 */     GIR_RootConstrainSelectedInstOperands,
     /* 37691 */     // GIR_Coverage, 1346,
     /* 37691 */     GIR_EraseRootFromParent_Done,
     /* 37692 */   // Label 1018: @37692
     /* 37692 */   GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(37744), // Rule ID 1347 //
     /* 37697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37700 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_ph),
     /* 37705 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37708 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37711 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37714 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37722 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37726 */     // (intrinsic_w_chain:{ *:[v2i16] } 8402:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_RS_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37726 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_PH_MM),
     /* 37729 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37731 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37733 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37735 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 37738 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37742 */     GIR_RootConstrainSelectedInstOperands,
     /* 37743 */     // GIR_Coverage, 1347,
     /* 37743 */     GIR_EraseRootFromParent_Done,
     /* 37744 */   // Label 1019: @37744
     /* 37744 */   GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(37796), // Rule ID 1350 //
     /* 37749 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37752 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrqu_s_qb_ph),
     /* 37757 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 37760 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37763 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37766 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37770 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37774 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37778 */     // (intrinsic_w_chain:{ *:[v4i8] } 8459:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECRQU_S_QB_PH_MM:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37778 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQU_S_QB_PH_MM),
     /* 37781 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37783 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37785 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37787 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37790 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37794 */     GIR_RootConstrainSelectedInstOperands,
     /* 37795 */     // GIR_Coverage, 1350,
     /* 37795 */     GIR_EraseRootFromParent_Done,
     /* 37796 */   // Label 1020: @37796
     /* 37796 */   GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(37848), // Rule ID 1351 //
     /* 37801 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37804 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precrq_rs_ph_w),
     /* 37809 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37812 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 37815 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 37818 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37822 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37826 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37830 */     // (intrinsic_w_chain:{ *:[v2i16] } 8458:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (PRECRQ_RS_PH_W_MM:{ *:[v2i16] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 37830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECRQ_RS_PH_W_MM),
     /* 37833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37835 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37837 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37839 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag22*/0,
     /* 37842 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37846 */     GIR_RootConstrainSelectedInstOperands,
     /* 37847 */     // GIR_Coverage, 1351,
     /* 37847 */     GIR_EraseRootFromParent_Done,
     /* 37848 */   // Label 1021: @37848
     /* 37848 */   GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37897), // Rule ID 1369 //
     /* 37853 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37856 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_ph),
     /* 37861 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 37864 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 37867 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 37870 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37874 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37878 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37882 */     // (intrinsic_w_chain:{ *:[v2i16] } 8441:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PICK_PH_MM:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 37882 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_PH_MM),
     /* 37885 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37887 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37889 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37891 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37895 */     GIR_RootConstrainSelectedInstOperands,
     /* 37896 */     // GIR_Coverage, 1369,
     /* 37896 */     GIR_EraseRootFromParent_Done,
     /* 37897 */   // Label 1022: @37897
     /* 37897 */   GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37946), // Rule ID 1370 //
     /* 37902 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37905 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_pick_qb),
     /* 37910 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 37913 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 37916 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 37919 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37923 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37927 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37931 */     // (intrinsic_w_chain:{ *:[v4i8] } 8442:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (PICK_QB_MM:{ *:[v4i8] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 37931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PICK_QB_MM),
     /* 37934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37936 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37938 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37940 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37944 */     GIR_RootConstrainSelectedInstOperands,
     /* 37945 */     // GIR_Coverage, 1370,
     /* 37945 */     GIR_EraseRootFromParent_Done,
     /* 37946 */   // Label 1023: @37946
     /* 37946 */   GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37995), // Rule ID 1380 //
     /* 37951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 37954 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_eq_qb),
     /* 37959 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 37962 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 37965 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 37968 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 37972 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37976 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 37980 */     // (intrinsic_w_chain:{ *:[i32] } 8098:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_EQ_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 37980 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_EQ_QB_MM),
     /* 37983 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 37985 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 37987 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 37989 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 37993 */     GIR_RootConstrainSelectedInstOperands,
     /* 37994 */     // GIR_Coverage, 1380,
     /* 37994 */     GIR_EraseRootFromParent_Done,
     /* 37995 */   // Label 1024: @37995
     /* 37995 */   GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(38044), // Rule ID 1381 //
     /* 38000 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 38003 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_lt_qb),
     /* 38008 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38011 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 38014 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 38017 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38021 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38025 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38029 */     // (intrinsic_w_chain:{ *:[i32] } 8100:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LT_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 38029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LT_QB_MM),
     /* 38032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38034 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38036 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38038 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38042 */     GIR_RootConstrainSelectedInstOperands,
     /* 38043 */     // GIR_Coverage, 1381,
     /* 38043 */     GIR_EraseRootFromParent_Done,
     /* 38044 */   // Label 1025: @38044
     /* 38044 */   GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(38093), // Rule ID 1382 //
     /* 38049 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 38052 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgu_le_qb),
     /* 38057 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38060 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 38063 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 38066 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38070 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38074 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38078 */     // (intrinsic_w_chain:{ *:[i32] } 8099:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGU_LE_QB_MM:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 38078 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGU_LE_QB_MM),
     /* 38081 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38083 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38085 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38087 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38091 */     GIR_RootConstrainSelectedInstOperands,
     /* 38092 */     // GIR_Coverage, 1382,
     /* 38092 */     GIR_EraseRootFromParent_Done,
     /* 38093 */   // Label 1026: @38093
     /* 38093 */   GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(38145), // Rule ID 1391 //
     /* 38098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38101 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_ph),
     /* 38106 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38109 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38112 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38115 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38119 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38123 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38127 */     // (intrinsic_w_chain:{ *:[v2i16] } 7950:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38127 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_PH_MMR2),
     /* 38130 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38132 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38134 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38136 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 38139 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38143 */     GIR_RootConstrainSelectedInstOperands,
     /* 38144 */     // GIR_Coverage, 1391,
     /* 38144 */     GIR_EraseRootFromParent_Done,
     /* 38145 */   // Label 1027: @38145
     /* 38145 */   GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(38197), // Rule ID 1392 //
     /* 38150 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38153 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addu_s_ph),
     /* 38158 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38161 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38175 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38179 */     // (intrinsic_w_chain:{ *:[v2i16] } 7952:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (ADDU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDU_S_PH_MMR2),
     /* 38182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38184 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38186 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38188 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 38191 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38195 */     GIR_RootConstrainSelectedInstOperands,
     /* 38196 */     // GIR_Coverage, 1392,
     /* 38196 */     GIR_EraseRootFromParent_Done,
     /* 38197 */   // Label 1028: @38197
     /* 38197 */   GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(38249), // Rule ID 1403 //
     /* 38202 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38205 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_eq_qb),
     /* 38210 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38213 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 38216 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 38219 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38223 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38227 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38231 */     // (intrinsic_w_chain:{ *:[i32] } 8095:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_EQ_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 38231 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_EQ_QB_MMR2),
     /* 38234 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38236 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38238 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38240 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 38243 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38247 */     GIR_RootConstrainSelectedInstOperands,
     /* 38248 */     // GIR_Coverage, 1403,
     /* 38248 */     GIR_EraseRootFromParent_Done,
     /* 38249 */   // Label 1029: @38249
     /* 38249 */   GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(38301), // Rule ID 1404 //
     /* 38254 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38257 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_lt_qb),
     /* 38262 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38265 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 38268 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 38271 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38275 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38279 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38283 */     // (intrinsic_w_chain:{ *:[i32] } 8097:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LT_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 38283 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LT_QB_MMR2),
     /* 38286 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38288 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38290 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38292 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 38295 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38299 */     GIR_RootConstrainSelectedInstOperands,
     /* 38300 */     // GIR_Coverage, 1404,
     /* 38300 */     GIR_EraseRootFromParent_Done,
     /* 38301 */   // Label 1030: @38301
     /* 38301 */   GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(38353), // Rule ID 1405 //
     /* 38306 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38309 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_cmpgdu_le_qb),
     /* 38314 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38317 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s8,
     /* 38320 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s8,
     /* 38323 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38327 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38331 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38335 */     // (intrinsic_w_chain:{ *:[i32] } 8096:{ *:[iPTR] }, DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)  =>  (CMPGDU_LE_QB_MMR2:{ *:[i32] } DSPROpnd:{ *:[v4i8] }:$rs, DSPROpnd:{ *:[v4i8] }:$rt)
     /* 38335 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMPGDU_LE_QB_MMR2),
     /* 38338 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38340 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38342 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38344 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCCond*/0,
     /* 38347 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38351 */     GIR_RootConstrainSelectedInstOperands,
     /* 38352 */     // GIR_Coverage, 1405,
     /* 38352 */     GIR_EraseRootFromParent_Done,
     /* 38353 */   // Label 1031: @38353
     /* 38353 */   GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(38405), // Rule ID 1411 //
     /* 38358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38361 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_ph),
     /* 38366 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38369 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38372 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38375 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38379 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38383 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38387 */     // (intrinsic_w_chain:{ *:[v2i16] } 8573:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38387 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_PH_MMR2),
     /* 38390 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38392 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38394 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38396 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 38399 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38403 */     GIR_RootConstrainSelectedInstOperands,
     /* 38404 */     // GIR_Coverage, 1411,
     /* 38404 */     GIR_EraseRootFromParent_Done,
     /* 38405 */   // Label 1032: @38405
     /* 38405 */   GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(38457), // Rule ID 1412 //
     /* 38410 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38413 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_subu_s_ph),
     /* 38418 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38421 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38424 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38427 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38431 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38435 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38439 */     // (intrinsic_w_chain:{ *:[v2i16] } 8575:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (SUBU_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38439 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SUBU_S_PH_MMR2),
     /* 38442 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38444 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38446 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38448 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 38451 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38455 */     GIR_RootConstrainSelectedInstOperands,
     /* 38456 */     // GIR_Coverage, 1412,
     /* 38456 */     GIR_EraseRootFromParent_Done,
     /* 38457 */   // Label 1033: @38457
     /* 38457 */   GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(38509), // Rule ID 1419 //
     /* 38462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38465 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_s_ph),
     /* 38470 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38473 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38476 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38479 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38483 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38487 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38491 */     // (intrinsic_w_chain:{ *:[v2i16] } 8397:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MUL_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38491 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_S_PH_MMR2),
     /* 38494 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38496 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38498 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38500 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 38503 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38507 */     GIR_RootConstrainSelectedInstOperands,
     /* 38508 */     // GIR_Coverage, 1419,
     /* 38508 */     GIR_EraseRootFromParent_Done,
     /* 38509 */   // Label 1034: @38509
     /* 38509 */   GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(38561), // Rule ID 1420 //
     /* 38514 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38517 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_rs_w),
     /* 38522 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38525 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 38528 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38531 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38535 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38539 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38543 */     // (intrinsic_w_chain:{ *:[i32] } 8403:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_RS_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 38543 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_RS_W_MMR2),
     /* 38546 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38548 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38550 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38552 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 38555 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38559 */     GIR_RootConstrainSelectedInstOperands,
     /* 38560 */     // GIR_Coverage, 1420,
     /* 38560 */     GIR_EraseRootFromParent_Done,
     /* 38561 */   // Label 1035: @38561
     /* 38561 */   GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(38613), // Rule ID 1421 //
     /* 38566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38569 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_ph),
     /* 38574 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38577 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38580 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38583 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38587 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38591 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38595 */     // (intrinsic_w_chain:{ *:[v2i16] } 8404:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (MULQ_S_PH_MMR2:{ *:[v2i16] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38595 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_PH_MMR2),
     /* 38598 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38600 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38602 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38604 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 38607 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38611 */     GIR_RootConstrainSelectedInstOperands,
     /* 38612 */     // GIR_Coverage, 1421,
     /* 38612 */     GIR_EraseRootFromParent_Done,
     /* 38613 */   // Label 1036: @38613
     /* 38613 */   GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(38665), // Rule ID 1422 //
     /* 38618 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38621 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mulq_s_w),
     /* 38626 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38629 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 38632 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38635 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38639 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38643 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38647 */     // (intrinsic_w_chain:{ *:[i32] } 8405:{ *:[iPTR] }, GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MULQ_S_W_MMR2:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 38647 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MULQ_S_W_MMR2),
     /* 38650 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38652 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38654 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38656 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 38659 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38663 */     GIR_RootConstrainSelectedInstOperands,
     /* 38664 */     // GIR_Coverage, 1422,
     /* 38664 */     GIR_EraseRootFromParent_Done,
     /* 38665 */   // Label 1037: @38665
     /* 38665 */   GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(38714), // Rule ID 1423 //
     /* 38670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2_InMicroMips),
     /* 38673 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_precr_qb_ph),
     /* 38678 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s8,
     /* 38681 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38691 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38695 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38699 */     // (intrinsic_w_chain:{ *:[v4i8] } 8453:{ *:[iPTR] }, DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)  =>  (PRECR_QB_PH_MMR2:{ *:[v4i8] } DSPROpnd:{ *:[v2i16] }:$rs, DSPROpnd:{ *:[v2i16] }:$rt)
     /* 38699 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::PRECR_QB_PH_MMR2),
     /* 38702 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38704 */     GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 38706 */     GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 38708 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38712 */     GIR_RootConstrainSelectedInstOperands,
     /* 38713 */     // GIR_Coverage, 1423,
     /* 38713 */     GIR_EraseRootFromParent_Done,
     /* 38714 */   // Label 1038: @38714
     /* 38714 */   GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(38758), // Rule ID 2056 //
     /* 38719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSPR2),
     /* 38722 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_mul_ph),
     /* 38727 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16,
     /* 38730 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16,
     /* 38733 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16,
     /* 38736 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::DSPRRegClassID),
     /* 38740 */     // (intrinsic_w_chain:{ *:[v2i16] } 8394:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)  =>  (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
     /* 38740 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MUL_PH),
     /* 38743 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38745 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 38747 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 38749 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag21*/0,
     /* 38752 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38756 */     GIR_RootConstrainSelectedInstOperands,
     /* 38757 */     // GIR_Coverage, 2056,
     /* 38757 */     GIR_EraseRootFromParent_Done,
     /* 38758 */   // Label 1039: @38758
     /* 38758 */   GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(38802), // Rule ID 2062 //
     /* 38763 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 38766 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addsc),
     /* 38771 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38774 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 38777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38784 */     // (intrinsic_w_chain:{ *:[i32] } 7949:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDSC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
     /* 38784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDSC),
     /* 38787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38789 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 38791 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 38793 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPCarry*/0,
     /* 38796 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38800 */     GIR_RootConstrainSelectedInstOperands,
     /* 38801 */     // GIR_Coverage, 2062,
     /* 38801 */     GIR_EraseRootFromParent_Done,
     /* 38802 */   // Label 1040: @38802
     /* 38802 */   GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(38846), // Rule ID 2064 //
     /* 38807 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 38810 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_addwc),
     /* 38815 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38818 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 38821 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38824 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38828 */     // (intrinsic_w_chain:{ *:[i32] } 7964:{ *:[iPTR] }, i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)  =>  (ADDWC:{ *:[i32] } i32:{ *:[i32] }:$a, i32:{ *:[i32] }:$b)
     /* 38828 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ADDWC),
     /* 38831 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38833 */     GIR_RootToRootCopy, /*OpIdx*/2, // a
     /* 38835 */     GIR_RootToRootCopy, /*OpIdx*/3, // b
     /* 38837 */     GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for Mips::DSPOutFlag20*/0,
     /* 38840 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38844 */     GIR_RootConstrainSelectedInstOperands,
     /* 38845 */     // GIR_Coverage, 2064,
     /* 38845 */     GIR_EraseRootFromParent_Done,
     /* 38846 */   // Label 1041: @38846
     /* 38846 */   GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(38892), // Rule ID 562 //
     /* 38851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 38854 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_d),
     /* 38859 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
     /* 38862 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38865 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 38869 */     // MIs[0] ptr
     /* 38869 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 38873 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38877 */     // (intrinsic_w_chain:{ *:[v2i64] } 8314:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)  =>  (LDR_D:{ *:[v2i64] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
     /* 38877 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_D),
     /* 38880 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 38882 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 38884 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 38886 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38890 */     GIR_RootConstrainSelectedInstOperands,
     /* 38891 */     // GIR_Coverage, 562,
     /* 38891 */     GIR_EraseRootFromParent_Done,
     /* 38892 */   // Label 1042: @38892
     /* 38892 */   GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(38938), // Rule ID 563 //
     /* 38897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 38900 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_ldr_w),
     /* 38905 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
     /* 38908 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38911 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 38915 */     // MIs[0] ptr
     /* 38915 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 38919 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38923 */     // (intrinsic_w_chain:{ *:[v4i32] } 8315:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)  =>  (LDR_W:{ *:[v4i32] } iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
     /* 38923 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LDR_W),
     /* 38926 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 38928 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 38930 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 38932 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38936 */     GIR_RootConstrainSelectedInstOperands,
     /* 38937 */     // GIR_Coverage, 563,
     /* 38937 */     GIR_EraseRootFromParent_Done,
     /* 38938 */   // Label 1043: @38938
     /* 38938 */   GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(38980), // Rule ID 509 //
     /* 38943 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 38946 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
     /* 38951 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38954 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38957 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 38961 */     // MIs[0] base
     /* 38961 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 38965 */     // (intrinsic_w_chain:{ *:[i32] } 8318:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LWX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 38965 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX),
     /* 38968 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 38970 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 38972 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 38974 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 38978 */     GIR_RootConstrainSelectedInstOperands,
     /* 38979 */     // GIR_Coverage, 509,
     /* 38979 */     GIR_EraseRootFromParent_Done,
     /* 38980 */   // Label 1044: @38980
     /* 38980 */   GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(39022), // Rule ID 510 //
     /* 38985 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 38988 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
     /* 38993 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 38996 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 38999 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39003 */     // MIs[0] base
     /* 39003 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39007 */     // (intrinsic_w_chain:{ *:[i32] } 8316:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LHX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 39007 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX),
     /* 39010 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39012 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 39014 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 39016 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39020 */     GIR_RootConstrainSelectedInstOperands,
     /* 39021 */     // GIR_Coverage, 510,
     /* 39021 */     GIR_EraseRootFromParent_Done,
     /* 39022 */   // Label 1045: @39022
     /* 39022 */   GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(39064), // Rule ID 511 //
     /* 39027 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP),
     /* 39030 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
     /* 39035 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39038 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39041 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39045 */     // MIs[0] base
     /* 39045 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39049 */     // (intrinsic_w_chain:{ *:[i32] } 8305:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LBUX:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 39049 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX),
     /* 39052 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39054 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 39056 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 39058 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39062 */     GIR_RootConstrainSelectedInstOperands,
     /* 39063 */     // GIR_Coverage, 511,
     /* 39063 */     GIR_EraseRootFromParent_Done,
     /* 39064 */   // Label 1046: @39064
     /* 39064 */   GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(39106), // Rule ID 1352 //
     /* 39069 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 39072 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lbux),
     /* 39077 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39080 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39083 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39087 */     // MIs[0] base
     /* 39087 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39091 */     // (intrinsic_w_chain:{ *:[i32] } 8305:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LBUX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 39091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LBUX_MM),
     /* 39094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39096 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 39098 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 39100 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39104 */     GIR_RootConstrainSelectedInstOperands,
     /* 39105 */     // GIR_Coverage, 1352,
     /* 39105 */     GIR_EraseRootFromParent_Done,
     /* 39106 */   // Label 1047: @39106
     /* 39106 */   GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(39148), // Rule ID 1353 //
     /* 39111 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 39114 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lhx),
     /* 39119 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39122 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39125 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39129 */     // MIs[0] base
     /* 39129 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39133 */     // (intrinsic_w_chain:{ *:[i32] } 8316:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LHX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 39133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LHX_MM),
     /* 39136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39138 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 39140 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 39142 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39146 */     GIR_RootConstrainSelectedInstOperands,
     /* 39147 */     // GIR_Coverage, 1353,
     /* 39147 */     GIR_EraseRootFromParent_Done,
     /* 39148 */   // Label 1048: @39148
     /* 39148 */   GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(39190), // Rule ID 1354 //
     /* 39153 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_InMicroMips),
     /* 39156 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mips_lwx),
     /* 39161 */     GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39164 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39167 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39171 */     // MIs[0] base
     /* 39171 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39175 */     // (intrinsic_w_chain:{ *:[i32] } 8318:{ *:[iPTR] }, iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)  =>  (LWX_MM:{ *:[i32] } iPTR:{ *:[iPTR] }:$base, iPTR:{ *:[i32] }:$index)
     /* 39175 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LWX_MM),
     /* 39178 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39180 */     GIR_RootToRootCopy, /*OpIdx*/2, // base
     /* 39182 */     GIR_RootToRootCopy, /*OpIdx*/3, // index
     /* 39184 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39188 */     GIR_RootConstrainSelectedInstOperands,
     /* 39189 */     // GIR_Coverage, 1354,
     /* 39189 */     GIR_EraseRootFromParent_Done,
     /* 39190 */   // Label 1049: @39190
     /* 39190 */   GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(39236), // Rule ID 564 //
     /* 39195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 39198 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_d),
     /* 39203 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 39206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39209 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 39213 */     // MIs[0] ptr
     /* 39213 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39217 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39221 */     // (intrinsic_void 8548:{ *:[iPTR] }, MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)  =>  (STR_D MSA128DOpnd:{ *:[v2i64] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
     /* 39221 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_D),
     /* 39224 */     GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 39226 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 39228 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 39230 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39234 */     GIR_RootConstrainSelectedInstOperands,
     /* 39235 */     // GIR_Coverage, 564,
     /* 39235 */     GIR_EraseRootFromParent_Done,
     /* 39236 */   // Label 1050: @39236
     /* 39236 */   GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(39282), // Rule ID 565 //
     /* 39241 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotInMips16Mode),
     /* 39244 */     GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::mips_str_w),
     /* 39249 */     GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 39252 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 39255 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 39259 */     // MIs[0] ptr
     /* 39259 */     GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
     /* 39263 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39267 */     // (intrinsic_void 8549:{ *:[iPTR] }, MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)  =>  (STR_W MSA128WOpnd:{ *:[v4i32] }:$dst, iPTR:{ *:[iPTR] }:$ptr, GPR32:{ *:[i32] }:$imm)
     /* 39267 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::STR_W),
     /* 39270 */     GIR_RootToRootCopy, /*OpIdx*/1, // dst
     /* 39272 */     GIR_RootToRootCopy, /*OpIdx*/2, // ptr
     /* 39274 */     GIR_RootToRootCopy, /*OpIdx*/3, // imm
     /* 39276 */     GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
     /* 39280 */     GIR_RootConstrainSelectedInstOperands,
     /* 39281 */     // GIR_Coverage, 565,
     /* 39281 */     GIR_EraseRootFromParent_Done,
     /* 39282 */   // Label 1051: @39282
     /* 39282 */   GIM_Reject,
     /* 39283 */ // Label 970: @39283
     /* 39283 */ GIM_Reject,
     /* 39284 */ // Label 31: @39284
     /* 39284 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(39349), // Rule ID 1685 //
     /* 39289 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 39292 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 39295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 39298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39302 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39306 */   // (anyext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), GPR32:{ *:[i32] }:$src, sub_32:{ *:[i32] })
     /* 39306 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39309 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39313 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39318 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39320 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39323 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39325 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39328 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 39330 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39333 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39338 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39343 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39348 */   // GIR_Coverage, 1685,
     /* 39348 */   GIR_EraseRootFromParent_Done,
     /* 39349 */ // Label 1052: @39349
     /* 39349 */ GIM_Reject,
     /* 39350 */ // Label 32: @39350
     /* 39350 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(39413), // Rule ID 1678 //
     /* 39355 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 39358 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39361 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 39364 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39368 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39372 */   // (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$src)  =>  (SLL:{ *:[i32] } (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$src, sub_32:{ *:[i32] }), 0:{ *:[i32] })
     /* 39372 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 39375 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 39379 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39384 */   GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src
     /* 39390 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /* 39395 */   GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39400 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
     /* 39403 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39405 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39408 */   GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 39411 */   GIR_RootConstrainSelectedInstOperands,
     /* 39412 */   // GIR_Coverage, 1678,
     /* 39412 */   GIR_EraseRootFromParent_Done,
     /* 39413 */ // Label 1053: @39413
     /* 39413 */ GIM_Reject,
     /* 39414 */ // Label 33: @39414
     /* 39414 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(39474),
     /* 39419 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 39422 */   GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(39448), // Rule ID 2289 //
     /* 39427 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 39430 */     GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immLi16),
     /* 39434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /* 39438 */     // MIs[0] Operand 1
     /* 39438 */     // No operand predicates
     /* 39438 */     // (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm  =>  (LI16_MM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_immLi16>>:$imm)
     /* 39438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LI16_MM),
     /* 39441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 39443 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /* 39446 */     GIR_RootConstrainSelectedInstOperands,
     /* 39447 */     // GIR_Coverage, 2289,
     /* 39447 */     GIR_EraseRootFromParent_Done,
     /* 39448 */   // Label 1055: @39448
     /* 39448 */   GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(39473), // Rule ID 1980 //
     /* 39453 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 39456 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 39460 */     // MIs[0] Operand 1
     /* 39460 */     // No operand predicates
     /* 39460 */     // (imm:{ *:[i32] }):$imm  =>  (LwConstant32:{ *:[i32] } (imm:{ *:[i32] }):$imm, -1:{ *:[i32] })
     /* 39460 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::LwConstant32),
     /* 39463 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 39465 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
     /* 39468 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/255,
     /* 39471 */     GIR_RootConstrainSelectedInstOperands,
     /* 39472 */     // GIR_Coverage, 1980,
     /* 39472 */     GIR_EraseRootFromParent_Done,
     /* 39473 */   // Label 1056: @39473
     /* 39473 */   GIM_Reject,
     /* 39474 */ // Label 1054: @39474
     /* 39474 */ GIM_Reject,
     /* 39475 */ // Label 34: @39475
     /* 39475 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(40938),
     /* 39480 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 39483 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 39486 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39490 */   GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(39595), // Rule ID 1734 //
     /* 39495 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 39499 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 39503 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 39507 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 39511 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39516 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 39520 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 39524 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 39528 */     // MIs[2] Operand 1
     /* 39528 */     // No operand predicates
     /* 39528 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 39530 */     // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRA:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
     /* 39530 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 39533 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRA),
     /* 39537 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39542 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 39546 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
     /* 39549 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 39551 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39554 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39558 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39563 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39565 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39568 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39570 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39573 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 39576 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39579 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39584 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39589 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39594 */     // GIR_Coverage, 1734,
     /* 39594 */     GIR_EraseRootFromParent_Done,
     /* 39595 */   // Label 1058: @39595
     /* 39595 */   GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(39700), // Rule ID 1730 //
     /* 39600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 39604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /* 39608 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 39612 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 39616 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39621 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 39625 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 39629 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 39633 */     // MIs[2] Operand 1
     /* 39633 */     // No operand predicates
     /* 39633 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 39635 */     // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
     /* 39635 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 39638 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRL),
     /* 39642 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39647 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 39651 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
     /* 39654 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 39656 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39659 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39663 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39668 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39670 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39673 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39675 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39678 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 39681 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39684 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39689 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39694 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39699 */     // GIR_Coverage, 1730,
     /* 39699 */     GIR_EraseRootFromParent_Done,
     /* 39700 */   // Label 1059: @39700
     /* 39700 */   GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(39805), // Rule ID 1726 //
     /* 39705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 39709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 39713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 39717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 39721 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39726 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 39730 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 39734 */     GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 39738 */     // MIs[2] Operand 1
     /* 39738 */     // No operand predicates
     /* 39738 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 39740 */     // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLL:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm5), sub_32:{ *:[i32] })
     /* 39740 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 39743 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL),
     /* 39747 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39752 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 39756 */     GIR_CopyConstantAsSImm, /*NewInsnID*/2, /*OldInsnID*/2, // imm5
     /* 39759 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 39761 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39764 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39768 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39773 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39775 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39778 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39780 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39783 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 39786 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39789 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39794 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39799 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39804 */     // GIR_Coverage, 1726,
     /* 39804 */     GIR_EraseRootFromParent_Done,
     /* 39805 */   // Label 1060: @39805
     /* 39805 */   GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(39904), // Rule ID 1716 //
     /* 39810 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 39814 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
     /* 39818 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 39822 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 39826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39831 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39836 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 39838 */     // (sext:{ *:[i64] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (ADDu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 39838 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 39841 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::ADDu),
     /* 39845 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39850 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 39854 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 39858 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 39860 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39863 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39867 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39872 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39874 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39877 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39879 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39882 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 39885 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39888 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39893 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39898 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39903 */     // GIR_Coverage, 1716,
     /* 39903 */     GIR_EraseRootFromParent_Done,
     /* 39904 */   // Label 1061: @39904
     /* 39904 */   GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(40003), // Rule ID 1736 //
     /* 39909 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 39913 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
     /* 39917 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 39921 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 39925 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39930 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 39935 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 39937 */     // (sext:{ *:[i64] } (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRAV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 39937 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 39940 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRAV),
     /* 39944 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39949 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 39953 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 39957 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 39959 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 39962 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 39966 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 39971 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 39973 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 39976 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 39978 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 39981 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 39984 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 39987 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39992 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 39997 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40002 */     // GIR_Coverage, 1736,
     /* 40002 */     GIR_EraseRootFromParent_Done,
     /* 40003 */   // Label 1062: @40003
     /* 40003 */   GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(40102), // Rule ID 1732 //
     /* 40008 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40012 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
     /* 40016 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40020 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40024 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40029 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40034 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40036 */     // (sext:{ *:[i64] } (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SRLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40036 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40039 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SRLV),
     /* 40043 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40048 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40052 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40056 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40058 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40061 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40065 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40070 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40072 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40075 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40077 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40080 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40083 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40086 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40091 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40096 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40101 */     // GIR_Coverage, 1732,
     /* 40101 */     GIR_EraseRootFromParent_Done,
     /* 40102 */   // Label 1063: @40102
     /* 40102 */   GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(40210), // Rule ID 1720 //
     /* 40107 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotMips32r6_NotMips64r6),
     /* 40110 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40114 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 40118 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40122 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40126 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40131 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40136 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40138 */     // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40138 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40141 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL),
     /* 40145 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40150 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40154 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40158 */     GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::HI0*/0,
     /* 40161 */     GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for Mips::LO0*/1,
     /* 40164 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40166 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40169 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40173 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40178 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40180 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40183 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40185 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40188 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40191 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40194 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40199 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40204 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40209 */     // GIR_Coverage, 1720,
     /* 40209 */     GIR_EraseRootFromParent_Done,
     /* 40210 */   // Label 1064: @40210
     /* 40210 */   GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(40312), // Rule ID 1931 //
     /* 40215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 40218 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40222 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
     /* 40226 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40230 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40234 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40239 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40244 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40246 */     // (sext:{ *:[i64] } (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MUL_R6:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40246 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40249 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MUL_R6),
     /* 40253 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40258 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40262 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40266 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40268 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40271 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40275 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40280 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40282 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40285 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40287 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40290 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40293 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40296 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40301 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40306 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40311 */     // GIR_Coverage, 1931,
     /* 40311 */     GIR_EraseRootFromParent_Done,
     /* 40312 */   // Label 1065: @40312
     /* 40312 */   GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(40414), // Rule ID 1932 //
     /* 40317 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 40320 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40324 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SDIV),
     /* 40328 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40332 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40336 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40341 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40346 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40348 */     // (sext:{ *:[i64] } (sdiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40348 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40351 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIV),
     /* 40355 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40360 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40364 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40368 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40370 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40373 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40377 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40382 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40384 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40387 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40389 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40392 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40395 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40398 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40403 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40408 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40413 */     // GIR_Coverage, 1932,
     /* 40413 */     GIR_EraseRootFromParent_Done,
     /* 40414 */   // Label 1066: @40414
     /* 40414 */   GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(40513), // Rule ID 1728 //
     /* 40419 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40423 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
     /* 40427 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40431 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40435 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40440 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40445 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40447 */     // (sext:{ *:[i64] } (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SLLV:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40447 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40450 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLLV),
     /* 40454 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40459 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40463 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40467 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40469 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40472 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40476 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40481 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40483 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40486 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40488 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40491 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40494 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40497 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40502 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40507 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40512 */     // GIR_Coverage, 1728,
     /* 40512 */     GIR_EraseRootFromParent_Done,
     /* 40513 */   // Label 1067: @40513
     /* 40513 */   GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(40615), // Rule ID 1934 //
     /* 40518 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 40521 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40525 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SREM),
     /* 40529 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40533 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40537 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40542 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40547 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40549 */     // (sext:{ *:[i64] } (srem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MOD:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40549 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40552 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MOD),
     /* 40556 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40561 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40565 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40569 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40571 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40574 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40578 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40583 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40585 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40588 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40590 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40593 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40596 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40599 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40604 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40609 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40614 */     // GIR_Coverage, 1934,
     /* 40614 */     GIR_EraseRootFromParent_Done,
     /* 40615 */   // Label 1068: @40615
     /* 40615 */   GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(40714), // Rule ID 1718 //
     /* 40620 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40624 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
     /* 40628 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40632 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40636 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40641 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40646 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40648 */     // (sext:{ *:[i64] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (SUBu:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40648 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40651 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SUBu),
     /* 40655 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40660 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40664 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40668 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40670 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40673 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40677 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40682 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40684 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40687 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40689 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40692 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40695 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40698 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40703 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40708 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40713 */     // GIR_Coverage, 1718,
     /* 40713 */     GIR_EraseRootFromParent_Done,
     /* 40714 */   // Label 1069: @40714
     /* 40714 */   GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(40816), // Rule ID 1933 //
     /* 40719 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 40722 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40726 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UDIV),
     /* 40730 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40734 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40738 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40743 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40748 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40750 */     // (sext:{ *:[i64] } (udiv:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (DIVU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40750 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40753 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::DIVU),
     /* 40757 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40762 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40766 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40770 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40772 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40775 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40779 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40784 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40791 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40794 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40797 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40800 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40805 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40810 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40815 */     // GIR_Coverage, 1933,
     /* 40815 */     GIR_EraseRootFromParent_Done,
     /* 40816 */   // Label 1070: @40816
     /* 40816 */   GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(40918), // Rule ID 1935 //
     /* 40821 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 40824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 40828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UREM),
     /* 40832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 40836 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 40840 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40845 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40850 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 40852 */     // (sext:{ *:[i64] } (urem:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2))  =>  (INSERT_SUBREG:{ *:[i64] } (IMPLICIT_DEF:{ *:[i64] }), (MODU:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src2), sub_32:{ *:[i32] })
     /* 40852 */     GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 40855 */     GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::MODU),
     /* 40859 */     GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40864 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // src
     /* 40868 */     GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // src2
     /* 40872 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 40874 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 40877 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
     /* 40881 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 40886 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 40888 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
     /* 40891 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 40893 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 40896 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 40899 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 40902 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40907 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 40912 */     GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40917 */     // GIR_Coverage, 1935,
     /* 40917 */     GIR_EraseRootFromParent_Done,
     /* 40918 */   // Label 1071: @40918
     /* 40918 */   GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(40937), // Rule ID 1688 //
     /* 40923 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 40926 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40930 */     // (sext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (SLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src)
     /* 40930 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
     /* 40935 */     GIR_RootConstrainSelectedInstOperands,
     /* 40936 */     // GIR_Coverage, 1688,
     /* 40936 */     GIR_Done,
     /* 40937 */   // Label 1072: @40937
     /* 40937 */   GIM_Reject,
     /* 40938 */ // Label 1057: @40938
     /* 40938 */ GIM_Reject,
     /* 40939 */ // Label 35: @40939
     /* 40939 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1075*/ GIMT_Encode4(41286),
     /* 40950 */ /*GILLT_s32*//*Label 1073*/ GIMT_Encode4(40958),
     /* 40954 */ /*GILLT_s64*//*Label 1074*/ GIMT_Encode4(41184),
     /* 40958 */ // Label 1073: @40958
     /* 40958 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(41183),
     /* 40963 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 40966 */   GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(41002), // Rule ID 106 //
     /* 40971 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
     /* 40974 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40978 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 40982 */     // MIs[0] Operand 2
     /* 40982 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 40993 */     // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] })  =>  (SEB:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 40993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB),
     /* 40996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 40998 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41000 */     GIR_RootConstrainSelectedInstOperands,
     /* 41001 */     // GIR_Coverage, 106,
     /* 41001 */     GIR_EraseRootFromParent_Done,
     /* 41002 */   // Label 1077: @41002
     /* 41002 */   GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(41038), // Rule ID 107 //
     /* 41007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
     /* 41010 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41014 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41018 */     // MIs[0] Operand 2
     /* 41018 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 41029 */     // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] })  =>  (SEH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 41029 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH),
     /* 41032 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41034 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41036 */     GIR_RootConstrainSelectedInstOperands,
     /* 41037 */     // GIR_Coverage, 107,
     /* 41037 */     GIR_EraseRootFromParent_Done,
     /* 41038 */   // Label 1078: @41038
     /* 41038 */   GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(41074), // Rule ID 1176 //
     /* 41043 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 41046 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41050 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41054 */     // MIs[0] Operand 2
     /* 41054 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 41065 */     // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i8:{ *:[Other] })  =>  (SEB_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 41065 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB_MM),
     /* 41068 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41070 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41072 */     GIR_RootConstrainSelectedInstOperands,
     /* 41073 */     // GIR_Coverage, 1176,
     /* 41073 */     GIR_EraseRootFromParent_Done,
     /* 41074 */   // Label 1079: @41074
     /* 41074 */   GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(41110), // Rule ID 1177 //
     /* 41079 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 41082 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41086 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41090 */     // MIs[0] Operand 2
     /* 41090 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 41101 */     // (sext_inreg:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, i16:{ *:[Other] })  =>  (SEH_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt)
     /* 41101 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH_MM),
     /* 41104 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41106 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41108 */     GIR_RootConstrainSelectedInstOperands,
     /* 41109 */     // GIR_Coverage, 1177,
     /* 41109 */     GIR_EraseRootFromParent_Done,
     /* 41110 */   // Label 1080: @41110
     /* 41110 */   GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(41146), // Rule ID 2038 //
     /* 41115 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 41118 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41122 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41126 */     // MIs[0] Operand 2
     /* 41126 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 41137 */     // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i8:{ *:[Other] })  =>  (SebRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
     /* 41137 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SebRx16),
     /* 41140 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 41142 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 41144 */     GIR_RootConstrainSelectedInstOperands,
     /* 41145 */     // GIR_Coverage, 2038,
     /* 41145 */     GIR_EraseRootFromParent_Done,
     /* 41146 */   // Label 1081: @41146
     /* 41146 */   GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(41182), // Rule ID 2039 //
     /* 41151 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 41154 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41158 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41162 */     // MIs[0] Operand 2
     /* 41162 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 41173 */     // (sext_inreg:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val, i16:{ *:[Other] })  =>  (SehRx16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$val)
     /* 41173 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SehRx16),
     /* 41176 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 41178 */     GIR_RootToRootCopy, /*OpIdx*/1, // val
     /* 41180 */     GIR_RootConstrainSelectedInstOperands,
     /* 41181 */     // GIR_Coverage, 2039,
     /* 41181 */     GIR_EraseRootFromParent_Done,
     /* 41182 */   // Label 1082: @41182
     /* 41182 */   GIM_Reject,
     /* 41183 */ // Label 1076: @41183
     /* 41183 */ GIM_Reject,
     /* 41184 */ // Label 1074: @41184
     /* 41184 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(41285),
     /* 41189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 41192 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41196 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41200 */   GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(41228), // Rule ID 336 //
     /* 41205 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
     /* 41208 */     // MIs[0] Operand 2
     /* 41208 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
     /* 41219 */     // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i8:{ *:[Other] })  =>  (SEB64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
     /* 41219 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEB64),
     /* 41222 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41224 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41226 */     GIR_RootConstrainSelectedInstOperands,
     /* 41227 */     // GIR_Coverage, 336,
     /* 41227 */     GIR_EraseRootFromParent_Done,
     /* 41228 */   // Label 1084: @41228
     /* 41228 */   GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(41256), // Rule ID 337 //
     /* 41233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_IsGP64bit),
     /* 41236 */     // MIs[0] Operand 2
     /* 41236 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
     /* 41247 */     // (sext_inreg:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, i16:{ *:[Other] })  =>  (SEH64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt)
     /* 41247 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEH64),
     /* 41250 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41252 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41254 */     GIR_RootConstrainSelectedInstOperands,
     /* 41255 */     // GIR_Coverage, 337,
     /* 41255 */     GIR_EraseRootFromParent_Done,
     /* 41256 */   // Label 1085: @41256
     /* 41256 */   GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(41284), // Rule ID 1691 //
     /* 41261 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 41264 */     // MIs[0] Operand 2
     /* 41264 */     GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(32),
     /* 41275 */     // (sext_inreg:{ *:[i64] } GPR64:{ *:[i64] }:$src, i32:{ *:[Other] })  =>  (SLL64_64:{ *:[i64] } GPR64:{ *:[i64] }:$src)
     /* 41275 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL64_64),
     /* 41278 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41280 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 41282 */     GIR_RootConstrainSelectedInstOperands,
     /* 41283 */     // GIR_Coverage, 1691,
     /* 41283 */     GIR_EraseRootFromParent_Done,
     /* 41284 */   // Label 1086: @41284
     /* 41284 */   GIM_Reject,
     /* 41285 */ // Label 1083: @41285
     /* 41285 */ GIM_Reject,
     /* 41286 */ // Label 1075: @41286
     /* 41286 */ GIM_Reject,
     /* 41287 */ // Label 36: @41287
     /* 41287 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(41487),
     /* 41292 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
     /* 41295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 41298 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41302 */   GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(41358), // Rule ID 355 //
     /* 41307 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 41310 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 41314 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 41318 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 41322 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 41326 */     // MIs[1] Operand 1
     /* 41326 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 41331 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41336 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41341 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41343 */     // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETEQ:{ *:[Other] }))  =>  (SEQ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 41343 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEQ),
     /* 41346 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41348 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 41352 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 41356 */     GIR_RootConstrainSelectedInstOperands,
     /* 41357 */     // GIR_Coverage, 355,
     /* 41357 */     GIR_EraseRootFromParent_Done,
     /* 41358 */   // Label 1088: @41358
     /* 41358 */   GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(41414), // Rule ID 357 //
     /* 41363 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 41366 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 41370 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 41374 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 41378 */     GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 41382 */     // MIs[1] Operand 1
     /* 41382 */     GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 41387 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41392 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41397 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41399 */     // (zext:{ *:[i64] } (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETNE:{ *:[Other] }))  =>  (SNE:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 41399 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SNE),
     /* 41402 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41404 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rs
     /* 41408 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // rt
     /* 41412 */     GIR_RootConstrainSelectedInstOperands,
     /* 41413 */     // GIR_Coverage, 357,
     /* 41413 */     GIR_EraseRootFromParent_Done,
     /* 41414 */   // Label 1089: @41414
     /* 41414 */   GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(41486),
     /* 41419 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41423 */     GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(41462), // Rule ID 1686 //
     /* 41428 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 41431 */       // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DSRL:{ *:[i64] } (DSLL64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src), 32:{ *:[i32] })
     /* 41431 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 41434 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSLL64_32),
     /* 41438 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 41443 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 41447 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 41449 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
     /* 41452 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41454 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 41457 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
     /* 41460 */       GIR_RootConstrainSelectedInstOperands,
     /* 41461 */       // GIR_Coverage, 1686,
     /* 41461 */       GIR_EraseRootFromParent_Done,
     /* 41462 */     // Label 1091: @41462
     /* 41462 */     GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(41485), // Rule ID 1689 //
     /* 41467 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 41470 */       // (zext:{ *:[i64] } GPR32:{ *:[i32] }:$src)  =>  (DEXT64_32:{ *:[i64] } GPR32:{ *:[i32] }:$src, 0:{ *:[i32] }, 32:{ *:[i32] })
     /* 41470 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DEXT64_32),
     /* 41473 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 41475 */       GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 41477 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
     /* 41480 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/32,
     /* 41483 */       GIR_RootConstrainSelectedInstOperands,
     /* 41484 */       // GIR_Coverage, 1689,
     /* 41484 */       GIR_EraseRootFromParent_Done,
     /* 41485 */     // Label 1092: @41485
     /* 41485 */     GIM_Reject,
     /* 41486 */   // Label 1090: @41486
     /* 41486 */   GIM_Reject,
     /* 41487 */ // Label 1087: @41487
     /* 41487 */ GIM_Reject,
     /* 41488 */ // Label 37: @41488
     /* 41488 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1099*/ GIMT_Encode4(43284),
     /* 41499 */ /*GILLT_s32*//*Label 1093*/ GIMT_Encode4(41531),
     /* 41503 */ /*GILLT_s64*//*Label 1094*/ GIMT_Encode4(41793), GIMT_Encode4(0),
     /* 41511 */ /*GILLT_v2s64*//*Label 1095*/ GIMT_Encode4(41934), GIMT_Encode4(0),
     /* 41519 */ /*GILLT_v4s32*//*Label 1096*/ GIMT_Encode4(41968),
     /* 41523 */ /*GILLT_v8s16*//*Label 1097*/ GIMT_Encode4(42236),
     /* 41527 */ /*GILLT_v16s8*//*Label 1098*/ GIMT_Encode4(42632),
     /* 41531 */ // Label 1093: @41531
     /* 41531 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(41792),
     /* 41536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 41539 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 41542 */   GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(41584), // Rule ID 55 //
     /* 41547 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 41550 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41554 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41558 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41562 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 41566 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 41570 */     // MIs[1] Operand 1
     /* 41570 */     // No operand predicates
     /* 41570 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41572 */     // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SLL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 41572 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL),
     /* 41575 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41577 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41579 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 41582 */     GIR_RootConstrainSelectedInstOperands,
     /* 41583 */     // GIR_Coverage, 55,
     /* 41583 */     GIR_EraseRootFromParent_Done,
     /* 41584 */   // Label 1101: @41584
     /* 41584 */   GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(41626), // Rule ID 1962 //
     /* 41589 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 41592 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41596 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41600 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41604 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 41608 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 41612 */     // MIs[1] Operand 1
     /* 41612 */     // No operand predicates
     /* 41612 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41614 */     // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SllX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 41614 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SllX16),
     /* 41617 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 41619 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /* 41621 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 41624 */     GIR_RootConstrainSelectedInstOperands,
     /* 41625 */     // GIR_Coverage, 1962,
     /* 41625 */     GIR_EraseRootFromParent_Done,
     /* 41626 */   // Label 1102: @41626
     /* 41626 */   GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(41668), // Rule ID 2301 //
     /* 41631 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 41634 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /* 41638 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /* 41642 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41646 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 41650 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
     /* 41654 */     // MIs[1] Operand 1
     /* 41654 */     // No operand predicates
     /* 41654 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41656 */     // (shl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SLL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
     /* 41656 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL16_MM),
     /* 41659 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41661 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 41663 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 41666 */     GIR_RootConstrainSelectedInstOperands,
     /* 41667 */     // GIR_Coverage, 2301,
     /* 41667 */     GIR_EraseRootFromParent_Done,
     /* 41668 */   // Label 1103: @41668
     /* 41668 */   GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(41710), // Rule ID 2302 //
     /* 41673 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 41676 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41680 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41684 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41688 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 41692 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 41696 */     // MIs[1] Operand 1
     /* 41696 */     // No operand predicates
     /* 41696 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41698 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SLL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 41698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_MM),
     /* 41701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41703 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 41705 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 41708 */     GIR_RootConstrainSelectedInstOperands,
     /* 41709 */     // GIR_Coverage, 2302,
     /* 41709 */     GIR_EraseRootFromParent_Done,
     /* 41710 */   // Label 1104: @41710
     /* 41710 */   GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(41737), // Rule ID 61 //
     /* 41715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 41718 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41722 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41726 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41730 */     // (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SLLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 41730 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV),
     /* 41735 */     GIR_RootConstrainSelectedInstOperands,
     /* 41736 */     // GIR_Coverage, 61,
     /* 41736 */     GIR_Done,
     /* 41737 */   // Label 1105: @41737
     /* 41737 */   GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(41764), // Rule ID 1965 //
     /* 41742 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 41745 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41749 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41753 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 41757 */     // (shl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SllvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
     /* 41757 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SllvRxRy16),
     /* 41762 */     GIR_RootConstrainSelectedInstOperands,
     /* 41763 */     // GIR_Coverage, 1965,
     /* 41763 */     GIR_Done,
     /* 41764 */   // Label 1106: @41764
     /* 41764 */   GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(41791), // Rule ID 2303 //
     /* 41769 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 41772 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41776 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41780 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41784 */     // (shl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SLLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
     /* 41784 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLLV_MM),
     /* 41789 */     GIR_RootConstrainSelectedInstOperands,
     /* 41790 */     // GIR_Coverage, 2303,
     /* 41790 */     GIR_Done,
     /* 41791 */   // Label 1107: @41791
     /* 41791 */   GIM_Reject,
     /* 41792 */ // Label 1100: @41792
     /* 41792 */ GIM_Reject,
     /* 41793 */ // Label 1094: @41793
     /* 41793 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(41933),
     /* 41798 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 41801 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 41804 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41808 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41812 */   GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(41846), // Rule ID 285 //
     /* 41817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 41820 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41824 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 41828 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
     /* 41832 */     // MIs[1] Operand 1
     /* 41832 */     // No operand predicates
     /* 41832 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41834 */     // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSLL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 41834 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLL),
     /* 41837 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41839 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41841 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 41844 */     GIR_RootConstrainSelectedInstOperands,
     /* 41845 */     // GIR_Coverage, 285,
     /* 41845 */     GIR_EraseRootFromParent_Done,
     /* 41846 */   // Label 1109: @41846
     /* 41846 */   GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(41913), // Rule ID 1679 //
     /* 41851 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 41854 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41858 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 41862 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 41866 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41871 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 41873 */     // (shl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSLLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
     /* 41873 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 41876 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 41880 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 41885 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
     /* 41891 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /* 41896 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 41901 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
     /* 41904 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 41906 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 41908 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 41911 */     GIR_RootConstrainSelectedInstOperands,
     /* 41912 */     // GIR_Coverage, 1679,
     /* 41912 */     GIR_EraseRootFromParent_Done,
     /* 41913 */   // Label 1110: @41913
     /* 41913 */   GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(41932), // Rule ID 291 //
     /* 41918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 41921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 41925 */     // (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSLLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 41925 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSLLV),
     /* 41930 */     GIR_RootConstrainSelectedInstOperands,
     /* 41931 */     // GIR_Coverage, 291,
     /* 41931 */     GIR_Done,
     /* 41932 */   // Label 1111: @41932
     /* 41932 */   GIM_Reject,
     /* 41933 */ // Label 1108: @41933
     /* 41933 */ GIM_Reject,
     /* 41934 */ // Label 1095: @41934
     /* 41934 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(41967), // Rule ID 1035 //
     /* 41939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 41942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 41945 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 41948 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 41952 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 41956 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 41960 */   // (shl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SLL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 41960 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_D),
     /* 41965 */   GIR_RootConstrainSelectedInstOperands,
     /* 41966 */   // GIR_Coverage, 1035,
     /* 41966 */   GIR_Done,
     /* 41967 */ // Label 1112: @41967
     /* 41967 */ GIM_Reject,
     /* 41968 */ // Label 1096: @41968
     /* 41968 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(42235),
     /* 41973 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 41976 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 41979 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 41983 */   GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(42097), // Rule ID 2636 //
     /* 41988 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 41991 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 41995 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 41999 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 42003 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 42007 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 42011 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42015 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 42018 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42022 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42026 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 42030 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 42034 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 42038 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42042 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42046 */     // MIs[3] Operand 1
     /* 42046 */     // No operand predicates
     /* 42046 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 42050 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42054 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42058 */     // MIs[4] Operand 1
     /* 42058 */     // No operand predicates
     /* 42058 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 42062 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42066 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42070 */     // MIs[5] Operand 1
     /* 42070 */     // No operand predicates
     /* 42070 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 42074 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42078 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42082 */     // MIs[6] Operand 1
     /* 42082 */     // No operand predicates
     /* 42082 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 42084 */     // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 42084 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
     /* 42087 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 42089 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 42091 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 42095 */     GIR_RootConstrainSelectedInstOperands,
     /* 42096 */     // GIR_Coverage, 2636,
     /* 42096 */     GIR_EraseRootFromParent_Done,
     /* 42097 */   // Label 1114: @42097
     /* 42097 */   GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(42211), // Rule ID 2202 //
     /* 42102 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 42105 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 42109 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 42113 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 42117 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 42121 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 42125 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42129 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 42132 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42136 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42140 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 42144 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 42148 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 42152 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42156 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42160 */     // MIs[3] Operand 1
     /* 42160 */     // No operand predicates
     /* 42160 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 42164 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42168 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42172 */     // MIs[4] Operand 1
     /* 42172 */     // No operand predicates
     /* 42172 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 42176 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42180 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42184 */     // MIs[5] Operand 1
     /* 42184 */     // No operand predicates
     /* 42184 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 42188 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42192 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 42196 */     // MIs[6] Operand 1
     /* 42196 */     // No operand predicates
     /* 42196 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 42198 */     // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SLL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 42198 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
     /* 42201 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 42203 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 42205 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 42209 */     GIR_RootConstrainSelectedInstOperands,
     /* 42210 */     // GIR_Coverage, 2202,
     /* 42210 */     GIR_EraseRootFromParent_Done,
     /* 42211 */   // Label 1115: @42211
     /* 42211 */   GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(42234), // Rule ID 1034 //
     /* 42216 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 42219 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 42223 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 42227 */     // (shl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SLL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 42227 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_W),
     /* 42232 */     GIR_RootConstrainSelectedInstOperands,
     /* 42233 */     // GIR_Coverage, 1034,
     /* 42233 */     GIR_Done,
     /* 42234 */   // Label 1116: @42234
     /* 42234 */   GIM_Reject,
     /* 42235 */ // Label 1113: @42235
     /* 42235 */ GIM_Reject,
     /* 42236 */ // Label 1097: @42236
     /* 42236 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(42631),
     /* 42241 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 42244 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 42247 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 42251 */   GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(42429), // Rule ID 2635 //
     /* 42256 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 42259 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 42263 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 42267 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 42271 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 42275 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 42279 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42283 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 42286 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42290 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42294 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 42298 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 42302 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 42306 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 42310 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 42314 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 42318 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 42322 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42326 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42330 */     // MIs[3] Operand 1
     /* 42330 */     // No operand predicates
     /* 42330 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 42334 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42338 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42342 */     // MIs[4] Operand 1
     /* 42342 */     // No operand predicates
     /* 42342 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 42346 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42350 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42354 */     // MIs[5] Operand 1
     /* 42354 */     // No operand predicates
     /* 42354 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 42358 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42362 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42366 */     // MIs[6] Operand 1
     /* 42366 */     // No operand predicates
     /* 42366 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 42370 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42374 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42378 */     // MIs[7] Operand 1
     /* 42378 */     // No operand predicates
     /* 42378 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 42382 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42386 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42390 */     // MIs[8] Operand 1
     /* 42390 */     // No operand predicates
     /* 42390 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 42394 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42398 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42402 */     // MIs[9] Operand 1
     /* 42402 */     // No operand predicates
     /* 42402 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 42406 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42410 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42414 */     // MIs[10] Operand 1
     /* 42414 */     // No operand predicates
     /* 42414 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 42416 */     // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 42416 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
     /* 42419 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 42421 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 42423 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 42427 */     GIR_RootConstrainSelectedInstOperands,
     /* 42428 */     // GIR_Coverage, 2635,
     /* 42428 */     GIR_EraseRootFromParent_Done,
     /* 42429 */   // Label 1118: @42429
     /* 42429 */   GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(42607), // Rule ID 2201 //
     /* 42434 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 42437 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 42441 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 42445 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 42449 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 42453 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 42457 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42461 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 42464 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42468 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42472 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 42476 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 42480 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 42484 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 42488 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 42492 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 42496 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 42500 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42504 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42508 */     // MIs[3] Operand 1
     /* 42508 */     // No operand predicates
     /* 42508 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 42512 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42516 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42520 */     // MIs[4] Operand 1
     /* 42520 */     // No operand predicates
     /* 42520 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 42524 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42528 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42532 */     // MIs[5] Operand 1
     /* 42532 */     // No operand predicates
     /* 42532 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 42536 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42540 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42544 */     // MIs[6] Operand 1
     /* 42544 */     // No operand predicates
     /* 42544 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 42548 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42552 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42556 */     // MIs[7] Operand 1
     /* 42556 */     // No operand predicates
     /* 42556 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 42560 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42564 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42568 */     // MIs[8] Operand 1
     /* 42568 */     // No operand predicates
     /* 42568 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 42572 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42576 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42580 */     // MIs[9] Operand 1
     /* 42580 */     // No operand predicates
     /* 42580 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 42584 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42588 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 42592 */     // MIs[10] Operand 1
     /* 42592 */     // No operand predicates
     /* 42592 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 42594 */     // (shl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SLL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 42594 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
     /* 42597 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 42599 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 42601 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 42605 */     GIR_RootConstrainSelectedInstOperands,
     /* 42606 */     // GIR_Coverage, 2201,
     /* 42606 */     GIR_EraseRootFromParent_Done,
     /* 42607 */   // Label 1119: @42607
     /* 42607 */   GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(42630), // Rule ID 1033 //
     /* 42612 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 42615 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 42619 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 42623 */     // (shl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SLL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 42623 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_H),
     /* 42628 */     GIR_RootConstrainSelectedInstOperands,
     /* 42629 */     // GIR_Coverage, 1033,
     /* 42629 */     GIR_Done,
     /* 42630 */   // Label 1120: @42630
     /* 42630 */   GIM_Reject,
     /* 42631 */ // Label 1117: @42631
     /* 42631 */ GIM_Reject,
     /* 42632 */ // Label 1098: @42632
     /* 42632 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(43283),
     /* 42637 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 42640 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 42643 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 42647 */   GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(42953), // Rule ID 2634 //
     /* 42652 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 42655 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 42659 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 42663 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 42667 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 42671 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 42675 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42679 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 42682 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42686 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42690 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 42694 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 42698 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 42702 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 42706 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 42710 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 42714 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 42718 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 42722 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 42726 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 42730 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 42734 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 42738 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 42742 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 42746 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 42750 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42754 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42758 */     // MIs[3] Operand 1
     /* 42758 */     // No operand predicates
     /* 42758 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 42762 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42766 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42770 */     // MIs[4] Operand 1
     /* 42770 */     // No operand predicates
     /* 42770 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 42774 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42778 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42782 */     // MIs[5] Operand 1
     /* 42782 */     // No operand predicates
     /* 42782 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 42786 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42790 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42794 */     // MIs[6] Operand 1
     /* 42794 */     // No operand predicates
     /* 42794 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 42798 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42802 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42806 */     // MIs[7] Operand 1
     /* 42806 */     // No operand predicates
     /* 42806 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 42810 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42814 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42818 */     // MIs[8] Operand 1
     /* 42818 */     // No operand predicates
     /* 42818 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 42822 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42826 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42830 */     // MIs[9] Operand 1
     /* 42830 */     // No operand predicates
     /* 42830 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 42834 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42838 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42842 */     // MIs[10] Operand 1
     /* 42842 */     // No operand predicates
     /* 42842 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 42846 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42850 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42854 */     // MIs[11] Operand 1
     /* 42854 */     // No operand predicates
     /* 42854 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 42858 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42862 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42866 */     // MIs[12] Operand 1
     /* 42866 */     // No operand predicates
     /* 42866 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 42870 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42874 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42878 */     // MIs[13] Operand 1
     /* 42878 */     // No operand predicates
     /* 42878 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 42882 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42886 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42890 */     // MIs[14] Operand 1
     /* 42890 */     // No operand predicates
     /* 42890 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 42894 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42898 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42902 */     // MIs[15] Operand 1
     /* 42902 */     // No operand predicates
     /* 42902 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 42906 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42910 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42914 */     // MIs[16] Operand 1
     /* 42914 */     // No operand predicates
     /* 42914 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 42918 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42922 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42926 */     // MIs[17] Operand 1
     /* 42926 */     // No operand predicates
     /* 42926 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 42930 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 42934 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 42938 */     // MIs[18] Operand 1
     /* 42938 */     // No operand predicates
     /* 42938 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 42940 */     // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 42940 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
     /* 42943 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 42945 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 42947 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 42951 */     GIR_RootConstrainSelectedInstOperands,
     /* 42952 */     // GIR_Coverage, 2634,
     /* 42952 */     GIR_EraseRootFromParent_Done,
     /* 42953 */   // Label 1122: @42953
     /* 42953 */   GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(43259), // Rule ID 2200 //
     /* 42958 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 42961 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 42965 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 42969 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 42973 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 42977 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 42981 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 42985 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 42988 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 42992 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 42996 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 43000 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 43004 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 43008 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 43012 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 43016 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 43020 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 43024 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 43028 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 43032 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 43036 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 43040 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 43044 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 43048 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 43052 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 43056 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43060 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43064 */     // MIs[3] Operand 1
     /* 43064 */     // No operand predicates
     /* 43064 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 43068 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43072 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43076 */     // MIs[4] Operand 1
     /* 43076 */     // No operand predicates
     /* 43076 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 43080 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43084 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43088 */     // MIs[5] Operand 1
     /* 43088 */     // No operand predicates
     /* 43088 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 43092 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43096 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43100 */     // MIs[6] Operand 1
     /* 43100 */     // No operand predicates
     /* 43100 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 43104 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43108 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43112 */     // MIs[7] Operand 1
     /* 43112 */     // No operand predicates
     /* 43112 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 43116 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43120 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43124 */     // MIs[8] Operand 1
     /* 43124 */     // No operand predicates
     /* 43124 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 43128 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43132 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43136 */     // MIs[9] Operand 1
     /* 43136 */     // No operand predicates
     /* 43136 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 43140 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43144 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43148 */     // MIs[10] Operand 1
     /* 43148 */     // No operand predicates
     /* 43148 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 43152 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43156 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43160 */     // MIs[11] Operand 1
     /* 43160 */     // No operand predicates
     /* 43160 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 43164 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43168 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43172 */     // MIs[12] Operand 1
     /* 43172 */     // No operand predicates
     /* 43172 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 43176 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43180 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43184 */     // MIs[13] Operand 1
     /* 43184 */     // No operand predicates
     /* 43184 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 43188 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43192 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43196 */     // MIs[14] Operand 1
     /* 43196 */     // No operand predicates
     /* 43196 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 43200 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43204 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43208 */     // MIs[15] Operand 1
     /* 43208 */     // No operand predicates
     /* 43208 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 43212 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43216 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43220 */     // MIs[16] Operand 1
     /* 43220 */     // No operand predicates
     /* 43220 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 43224 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43228 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43232 */     // MIs[17] Operand 1
     /* 43232 */     // No operand predicates
     /* 43232 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 43236 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43240 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 43244 */     // MIs[18] Operand 1
     /* 43244 */     // No operand predicates
     /* 43244 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 43246 */     // (shl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SLL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 43246 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
     /* 43249 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 43251 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 43253 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 43257 */     GIR_RootConstrainSelectedInstOperands,
     /* 43258 */     // GIR_Coverage, 2200,
     /* 43258 */     GIR_EraseRootFromParent_Done,
     /* 43259 */   // Label 1123: @43259
     /* 43259 */   GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(43282), // Rule ID 1032 //
     /* 43264 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 43267 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 43271 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 43275 */     // (shl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SLL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 43275 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SLL_B),
     /* 43280 */     GIR_RootConstrainSelectedInstOperands,
     /* 43281 */     // GIR_Coverage, 1032,
     /* 43281 */     GIR_Done,
     /* 43282 */   // Label 1124: @43282
     /* 43282 */   GIM_Reject,
     /* 43283 */ // Label 1121: @43283
     /* 43283 */ GIM_Reject,
     /* 43284 */ // Label 1099: @43284
     /* 43284 */ GIM_Reject,
     /* 43285 */ // Label 38: @43285
     /* 43285 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1131*/ GIMT_Encode4(45081),
     /* 43296 */ /*GILLT_s32*//*Label 1125*/ GIMT_Encode4(43328),
     /* 43300 */ /*GILLT_s64*//*Label 1126*/ GIMT_Encode4(43590), GIMT_Encode4(0),
     /* 43308 */ /*GILLT_v2s64*//*Label 1127*/ GIMT_Encode4(43731), GIMT_Encode4(0),
     /* 43316 */ /*GILLT_v4s32*//*Label 1128*/ GIMT_Encode4(43765),
     /* 43320 */ /*GILLT_v8s16*//*Label 1129*/ GIMT_Encode4(44033),
     /* 43324 */ /*GILLT_v16s8*//*Label 1130*/ GIMT_Encode4(44429),
     /* 43328 */ // Label 1125: @43328
     /* 43328 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(43589),
     /* 43333 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 43336 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 43339 */   GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(43381), // Rule ID 57 //
     /* 43344 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 43347 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43351 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43355 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43359 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43363 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 43367 */     // MIs[1] Operand 1
     /* 43367 */     // No operand predicates
     /* 43367 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43369 */     // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRL:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 43369 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL),
     /* 43372 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 43374 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 43376 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 43379 */     GIR_RootConstrainSelectedInstOperands,
     /* 43380 */     // GIR_Coverage, 57,
     /* 43380 */     GIR_EraseRootFromParent_Done,
     /* 43381 */   // Label 1133: @43381
     /* 43381 */   GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(43423), // Rule ID 1963 //
     /* 43386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 43389 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 43393 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 43397 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43401 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43405 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 43409 */     // MIs[1] Operand 1
     /* 43409 */     // No operand predicates
     /* 43409 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43411 */     // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SrlX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 43411 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SrlX16),
     /* 43414 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 43416 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /* 43418 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 43421 */     GIR_RootConstrainSelectedInstOperands,
     /* 43422 */     // GIR_Coverage, 1963,
     /* 43422 */     GIR_EraseRootFromParent_Done,
     /* 43423 */   // Label 1134: @43423
     /* 43423 */   GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(43465), // Rule ID 2304 //
     /* 43428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 43431 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /* 43435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPRMM16RegClassID),
     /* 43439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43447 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt2Shift),
     /* 43451 */     // MIs[1] Operand 1
     /* 43451 */     // No operand predicates
     /* 43451 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43453 */     // (srl:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)  =>  (SRL16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt2Shift>>:$imm)
     /* 43453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL16_MM),
     /* 43456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 43458 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 43460 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 43463 */     GIR_RootConstrainSelectedInstOperands,
     /* 43464 */     // GIR_Coverage, 2304,
     /* 43464 */     GIR_EraseRootFromParent_Done,
     /* 43465 */   // Label 1135: @43465
     /* 43465 */   GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(43507), // Rule ID 2305 //
     /* 43470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 43473 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43477 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43481 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43485 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43489 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 43493 */     // MIs[1] Operand 1
     /* 43493 */     // No operand predicates
     /* 43493 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43495 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRL_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 43495 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_MM),
     /* 43498 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 43500 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 43502 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 43505 */     GIR_RootConstrainSelectedInstOperands,
     /* 43506 */     // GIR_Coverage, 2305,
     /* 43506 */     GIR_EraseRootFromParent_Done,
     /* 43507 */   // Label 1136: @43507
     /* 43507 */   GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(43534), // Rule ID 63 //
     /* 43512 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 43515 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43519 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43523 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43527 */     // (srl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRLV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 43527 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV),
     /* 43532 */     GIR_RootConstrainSelectedInstOperands,
     /* 43533 */     // GIR_Coverage, 63,
     /* 43533 */     GIR_Done,
     /* 43534 */   // Label 1137: @43534
     /* 43534 */   GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(43561), // Rule ID 1967 //
     /* 43539 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 43542 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 43546 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 43550 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 43554 */     // (srl:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SrlvRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
     /* 43554 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SrlvRxRy16),
     /* 43559 */     GIR_RootConstrainSelectedInstOperands,
     /* 43560 */     // GIR_Coverage, 1967,
     /* 43560 */     GIR_Done,
     /* 43561 */   // Label 1138: @43561
     /* 43561 */   GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(43588), // Rule ID 2306 //
     /* 43566 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 43569 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43573 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43577 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43581 */     // (srl:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRLV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
     /* 43581 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRLV_MM),
     /* 43586 */     GIR_RootConstrainSelectedInstOperands,
     /* 43587 */     // GIR_Coverage, 2306,
     /* 43587 */     GIR_Done,
     /* 43588 */   // Label 1139: @43588
     /* 43588 */   GIM_Reject,
     /* 43589 */ // Label 1132: @43589
     /* 43589 */ GIM_Reject,
     /* 43590 */ // Label 1126: @43590
     /* 43590 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(43730),
     /* 43595 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 43598 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 43601 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 43605 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 43609 */   GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(43643), // Rule ID 287 //
     /* 43614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 43617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43625 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
     /* 43629 */     // MIs[1] Operand 1
     /* 43629 */     // No operand predicates
     /* 43629 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43631 */     // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRL:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 43631 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRL),
     /* 43634 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 43636 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 43638 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 43641 */     GIR_RootConstrainSelectedInstOperands,
     /* 43642 */     // GIR_Coverage, 287,
     /* 43642 */     GIR_EraseRootFromParent_Done,
     /* 43643 */   // Label 1141: @43643
     /* 43643 */   GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(43710), // Rule ID 1680 //
     /* 43648 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 43651 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43655 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 43659 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 43663 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 43668 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 43670 */     // (srl:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRLV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
     /* 43670 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 43673 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 43677 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 43682 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
     /* 43688 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /* 43693 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 43698 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
     /* 43701 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 43703 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 43705 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 43708 */     GIR_RootConstrainSelectedInstOperands,
     /* 43709 */     // GIR_Coverage, 1680,
     /* 43709 */     GIR_EraseRootFromParent_Done,
     /* 43710 */   // Label 1142: @43710
     /* 43710 */   GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(43729), // Rule ID 295 //
     /* 43715 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 43718 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 43722 */     // (srl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRLV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 43722 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRLV),
     /* 43727 */     GIR_RootConstrainSelectedInstOperands,
     /* 43728 */     // GIR_Coverage, 295,
     /* 43728 */     GIR_Done,
     /* 43729 */   // Label 1143: @43729
     /* 43729 */   GIM_Reject,
     /* 43730 */ // Label 1140: @43730
     /* 43730 */ GIM_Reject,
     /* 43731 */ // Label 1127: @43731
     /* 43731 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(43764), // Rule ID 1067 //
     /* 43736 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 43739 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 43742 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 43745 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 43749 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 43753 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 43757 */   // (srl:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRL_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 43757 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_D),
     /* 43762 */   GIR_RootConstrainSelectedInstOperands,
     /* 43763 */   // GIR_Coverage, 1067,
     /* 43763 */   GIR_Done,
     /* 43764 */ // Label 1144: @43764
     /* 43764 */ GIM_Reject,
     /* 43765 */ // Label 1128: @43765
     /* 43765 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(44032),
     /* 43770 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 43773 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 43776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 43780 */   GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(43894), // Rule ID 2652 //
     /* 43785 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 43788 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43792 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 43796 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 43800 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 43804 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 43808 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 43812 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 43815 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 43819 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 43823 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 43827 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 43831 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 43835 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43839 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43843 */     // MIs[3] Operand 1
     /* 43843 */     // No operand predicates
     /* 43843 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 43847 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43851 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43855 */     // MIs[4] Operand 1
     /* 43855 */     // No operand predicates
     /* 43855 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 43859 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43863 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43867 */     // MIs[5] Operand 1
     /* 43867 */     // No operand predicates
     /* 43867 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 43871 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43875 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43879 */     // MIs[6] Operand 1
     /* 43879 */     // No operand predicates
     /* 43879 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 43881 */     // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 43881 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
     /* 43884 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 43886 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 43888 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 43892 */     GIR_RootConstrainSelectedInstOperands,
     /* 43893 */     // GIR_Coverage, 2652,
     /* 43893 */     GIR_EraseRootFromParent_Done,
     /* 43894 */   // Label 1146: @43894
     /* 43894 */   GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(44008), // Rule ID 2210 //
     /* 43899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 43902 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 43906 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 43910 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 43914 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 43918 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 43922 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 43926 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 43929 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 43933 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 43937 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 43941 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 43945 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 43949 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43953 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43957 */     // MIs[3] Operand 1
     /* 43957 */     // No operand predicates
     /* 43957 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 43961 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43965 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43969 */     // MIs[4] Operand 1
     /* 43969 */     // No operand predicates
     /* 43969 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 43973 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43977 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43981 */     // MIs[5] Operand 1
     /* 43981 */     // No operand predicates
     /* 43981 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 43985 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 43989 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 43993 */     // MIs[6] Operand 1
     /* 43993 */     // No operand predicates
     /* 43993 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 43995 */     // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRL_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 43995 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
     /* 43998 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 44000 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 44002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 44006 */     GIR_RootConstrainSelectedInstOperands,
     /* 44007 */     // GIR_Coverage, 2210,
     /* 44007 */     GIR_EraseRootFromParent_Done,
     /* 44008 */   // Label 1147: @44008
     /* 44008 */   GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(44031), // Rule ID 1066 //
     /* 44013 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 44016 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 44020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 44024 */     // (srl:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRL_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 44024 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_W),
     /* 44029 */     GIR_RootConstrainSelectedInstOperands,
     /* 44030 */     // GIR_Coverage, 1066,
     /* 44030 */     GIR_Done,
     /* 44031 */   // Label 1148: @44031
     /* 44031 */   GIM_Reject,
     /* 44032 */ // Label 1145: @44032
     /* 44032 */ GIM_Reject,
     /* 44033 */ // Label 1129: @44033
     /* 44033 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(44428),
     /* 44038 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 44041 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 44044 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 44048 */   GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(44226), // Rule ID 2651 //
     /* 44053 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 44056 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 44060 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 44064 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 44068 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 44072 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 44076 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 44080 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 44083 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 44087 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 44091 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 44095 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 44099 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 44103 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 44107 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 44111 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 44115 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 44119 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44123 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44127 */     // MIs[3] Operand 1
     /* 44127 */     // No operand predicates
     /* 44127 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 44131 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44135 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44139 */     // MIs[4] Operand 1
     /* 44139 */     // No operand predicates
     /* 44139 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 44143 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44147 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44151 */     // MIs[5] Operand 1
     /* 44151 */     // No operand predicates
     /* 44151 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 44155 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44159 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44163 */     // MIs[6] Operand 1
     /* 44163 */     // No operand predicates
     /* 44163 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 44167 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44171 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44175 */     // MIs[7] Operand 1
     /* 44175 */     // No operand predicates
     /* 44175 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 44179 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44183 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44187 */     // MIs[8] Operand 1
     /* 44187 */     // No operand predicates
     /* 44187 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 44191 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44195 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44199 */     // MIs[9] Operand 1
     /* 44199 */     // No operand predicates
     /* 44199 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 44203 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44207 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44211 */     // MIs[10] Operand 1
     /* 44211 */     // No operand predicates
     /* 44211 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 44213 */     // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 44213 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
     /* 44216 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 44218 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 44220 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 44224 */     GIR_RootConstrainSelectedInstOperands,
     /* 44225 */     // GIR_Coverage, 2651,
     /* 44225 */     GIR_EraseRootFromParent_Done,
     /* 44226 */   // Label 1150: @44226
     /* 44226 */   GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(44404), // Rule ID 2209 //
     /* 44231 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 44234 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 44238 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 44242 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 44246 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 44250 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 44254 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 44258 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 44261 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 44265 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 44269 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 44273 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 44277 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 44281 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 44285 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 44289 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 44293 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 44297 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44301 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44305 */     // MIs[3] Operand 1
     /* 44305 */     // No operand predicates
     /* 44305 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 44309 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44313 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44317 */     // MIs[4] Operand 1
     /* 44317 */     // No operand predicates
     /* 44317 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 44321 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44325 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44329 */     // MIs[5] Operand 1
     /* 44329 */     // No operand predicates
     /* 44329 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 44333 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44337 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44341 */     // MIs[6] Operand 1
     /* 44341 */     // No operand predicates
     /* 44341 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 44345 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44349 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44353 */     // MIs[7] Operand 1
     /* 44353 */     // No operand predicates
     /* 44353 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 44357 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44361 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44365 */     // MIs[8] Operand 1
     /* 44365 */     // No operand predicates
     /* 44365 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 44369 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44373 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44377 */     // MIs[9] Operand 1
     /* 44377 */     // No operand predicates
     /* 44377 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 44381 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44385 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 44389 */     // MIs[10] Operand 1
     /* 44389 */     // No operand predicates
     /* 44389 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 44391 */     // (srl:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRL_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 44391 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
     /* 44394 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 44396 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 44398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 44402 */     GIR_RootConstrainSelectedInstOperands,
     /* 44403 */     // GIR_Coverage, 2209,
     /* 44403 */     GIR_EraseRootFromParent_Done,
     /* 44404 */   // Label 1151: @44404
     /* 44404 */   GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(44427), // Rule ID 1065 //
     /* 44409 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 44412 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 44416 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 44420 */     // (srl:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRL_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 44420 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_H),
     /* 44425 */     GIR_RootConstrainSelectedInstOperands,
     /* 44426 */     // GIR_Coverage, 1065,
     /* 44426 */     GIR_Done,
     /* 44427 */   // Label 1152: @44427
     /* 44427 */   GIM_Reject,
     /* 44428 */ // Label 1149: @44428
     /* 44428 */ GIM_Reject,
     /* 44429 */ // Label 1130: @44429
     /* 44429 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(45080),
     /* 44434 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 44437 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 44440 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 44444 */   GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(44750), // Rule ID 2650 //
     /* 44449 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 44452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 44456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 44460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 44464 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 44468 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 44472 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 44476 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 44479 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 44483 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 44487 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 44491 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 44495 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 44499 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 44503 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 44507 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 44511 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 44515 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 44519 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 44523 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 44527 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 44531 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 44535 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 44539 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 44543 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 44547 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44551 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44555 */     // MIs[3] Operand 1
     /* 44555 */     // No operand predicates
     /* 44555 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 44559 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44563 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44567 */     // MIs[4] Operand 1
     /* 44567 */     // No operand predicates
     /* 44567 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 44571 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44575 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44579 */     // MIs[5] Operand 1
     /* 44579 */     // No operand predicates
     /* 44579 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 44583 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44587 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44591 */     // MIs[6] Operand 1
     /* 44591 */     // No operand predicates
     /* 44591 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 44595 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44599 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44603 */     // MIs[7] Operand 1
     /* 44603 */     // No operand predicates
     /* 44603 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 44607 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44611 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44615 */     // MIs[8] Operand 1
     /* 44615 */     // No operand predicates
     /* 44615 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 44619 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44623 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44627 */     // MIs[9] Operand 1
     /* 44627 */     // No operand predicates
     /* 44627 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 44631 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44635 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44639 */     // MIs[10] Operand 1
     /* 44639 */     // No operand predicates
     /* 44639 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 44643 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44647 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44651 */     // MIs[11] Operand 1
     /* 44651 */     // No operand predicates
     /* 44651 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 44655 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44659 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44663 */     // MIs[12] Operand 1
     /* 44663 */     // No operand predicates
     /* 44663 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 44667 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44671 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44675 */     // MIs[13] Operand 1
     /* 44675 */     // No operand predicates
     /* 44675 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 44679 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44683 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44687 */     // MIs[14] Operand 1
     /* 44687 */     // No operand predicates
     /* 44687 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 44691 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44695 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44699 */     // MIs[15] Operand 1
     /* 44699 */     // No operand predicates
     /* 44699 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 44703 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44707 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44711 */     // MIs[16] Operand 1
     /* 44711 */     // No operand predicates
     /* 44711 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 44715 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44719 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44723 */     // MIs[17] Operand 1
     /* 44723 */     // No operand predicates
     /* 44723 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 44727 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44731 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44735 */     // MIs[18] Operand 1
     /* 44735 */     // No operand predicates
     /* 44735 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 44737 */     // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 44737 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
     /* 44740 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 44742 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 44744 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 44748 */     GIR_RootConstrainSelectedInstOperands,
     /* 44749 */     // GIR_Coverage, 2650,
     /* 44749 */     GIR_EraseRootFromParent_Done,
     /* 44750 */   // Label 1154: @44750
     /* 44750 */   GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(45056), // Rule ID 2208 //
     /* 44755 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 44758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 44762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 44766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 44770 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 44774 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 44778 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 44782 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 44785 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 44789 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 44793 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 44797 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 44801 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 44805 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 44809 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 44813 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 44817 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 44821 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 44825 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 44829 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 44833 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 44837 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 44841 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 44845 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 44849 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 44853 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44857 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44861 */     // MIs[3] Operand 1
     /* 44861 */     // No operand predicates
     /* 44861 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 44865 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44869 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44873 */     // MIs[4] Operand 1
     /* 44873 */     // No operand predicates
     /* 44873 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 44877 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44881 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44885 */     // MIs[5] Operand 1
     /* 44885 */     // No operand predicates
     /* 44885 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 44889 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44893 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44897 */     // MIs[6] Operand 1
     /* 44897 */     // No operand predicates
     /* 44897 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 44901 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44905 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44909 */     // MIs[7] Operand 1
     /* 44909 */     // No operand predicates
     /* 44909 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 44913 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44917 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44921 */     // MIs[8] Operand 1
     /* 44921 */     // No operand predicates
     /* 44921 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 44925 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44929 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44933 */     // MIs[9] Operand 1
     /* 44933 */     // No operand predicates
     /* 44933 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 44937 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44941 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44945 */     // MIs[10] Operand 1
     /* 44945 */     // No operand predicates
     /* 44945 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 44949 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44953 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44957 */     // MIs[11] Operand 1
     /* 44957 */     // No operand predicates
     /* 44957 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 44961 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44965 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44969 */     // MIs[12] Operand 1
     /* 44969 */     // No operand predicates
     /* 44969 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 44973 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44977 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44981 */     // MIs[13] Operand 1
     /* 44981 */     // No operand predicates
     /* 44981 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 44985 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 44989 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 44993 */     // MIs[14] Operand 1
     /* 44993 */     // No operand predicates
     /* 44993 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 44997 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45001 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 45005 */     // MIs[15] Operand 1
     /* 45005 */     // No operand predicates
     /* 45005 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 45009 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45013 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 45017 */     // MIs[16] Operand 1
     /* 45017 */     // No operand predicates
     /* 45017 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 45021 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45025 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 45029 */     // MIs[17] Operand 1
     /* 45029 */     // No operand predicates
     /* 45029 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 45033 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45037 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 45041 */     // MIs[18] Operand 1
     /* 45041 */     // No operand predicates
     /* 45041 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 45043 */     // (srl:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRL_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 45043 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
     /* 45046 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 45048 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 45050 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 45054 */     GIR_RootConstrainSelectedInstOperands,
     /* 45055 */     // GIR_Coverage, 2208,
     /* 45055 */     GIR_EraseRootFromParent_Done,
     /* 45056 */   // Label 1155: @45056
     /* 45056 */   GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(45079), // Rule ID 1064 //
     /* 45061 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 45064 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 45068 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 45072 */     // (srl:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRL_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 45072 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRL_B),
     /* 45077 */     GIR_RootConstrainSelectedInstOperands,
     /* 45078 */     // GIR_Coverage, 1064,
     /* 45078 */     GIR_Done,
     /* 45079 */   // Label 1156: @45079
     /* 45079 */   GIM_Reject,
     /* 45080 */ // Label 1153: @45080
     /* 45080 */ GIM_Reject,
     /* 45081 */ // Label 1131: @45081
     /* 45081 */ GIM_Reject,
     /* 45082 */ // Label 39: @45082
     /* 45082 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1163*/ GIMT_Encode4(46836),
     /* 45093 */ /*GILLT_s32*//*Label 1157*/ GIMT_Encode4(45125),
     /* 45097 */ /*GILLT_s64*//*Label 1158*/ GIMT_Encode4(45345), GIMT_Encode4(0),
     /* 45105 */ /*GILLT_v2s64*//*Label 1159*/ GIMT_Encode4(45486), GIMT_Encode4(0),
     /* 45113 */ /*GILLT_v4s32*//*Label 1160*/ GIMT_Encode4(45520),
     /* 45117 */ /*GILLT_v8s16*//*Label 1161*/ GIMT_Encode4(45788),
     /* 45121 */ /*GILLT_v16s8*//*Label 1162*/ GIMT_Encode4(46184),
     /* 45125 */ // Label 1157: @45125
     /* 45125 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(45344),
     /* 45130 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 45133 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 45136 */   GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(45178), // Rule ID 59 //
     /* 45141 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 45144 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45148 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45152 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45156 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45160 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 45164 */     // MIs[1] Operand 1
     /* 45164 */     // No operand predicates
     /* 45164 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 45166 */     // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (SRA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 45166 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA),
     /* 45169 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 45171 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 45173 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 45176 */     GIR_RootConstrainSelectedInstOperands,
     /* 45177 */     // GIR_Coverage, 59,
     /* 45177 */     GIR_EraseRootFromParent_Done,
     /* 45178 */   // Label 1165: @45178
     /* 45178 */   GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(45220), // Rule ID 1964 //
     /* 45183 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 45186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 45190 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 45194 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45198 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45202 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 45206 */     // MIs[1] Operand 1
     /* 45206 */     // No operand predicates
     /* 45206 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 45208 */     // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SraX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$in, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 45208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SraX16),
     /* 45211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rx]
     /* 45213 */     GIR_RootToRootCopy, /*OpIdx*/1, // in
     /* 45215 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 45218 */     GIR_RootConstrainSelectedInstOperands,
     /* 45219 */     // GIR_Coverage, 1964,
     /* 45219 */     GIR_EraseRootFromParent_Done,
     /* 45220 */   // Label 1166: @45220
     /* 45220 */   GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(45262), // Rule ID 2307 //
     /* 45225 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 45228 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45232 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45236 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45240 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45244 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 45248 */     // MIs[1] Operand 1
     /* 45248 */     // No operand predicates
     /* 45248 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 45250 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)  =>  (SRA_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$imm)
     /* 45250 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_MM),
     /* 45253 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 45255 */     GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 45257 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
     /* 45260 */     GIR_RootConstrainSelectedInstOperands,
     /* 45261 */     // GIR_Coverage, 2307,
     /* 45261 */     GIR_EraseRootFromParent_Done,
     /* 45262 */   // Label 1167: @45262
     /* 45262 */   GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(45289), // Rule ID 65 //
     /* 45267 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 45270 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45274 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45278 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45282 */     // (sra:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (SRAV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 45282 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV),
     /* 45287 */     GIR_RootConstrainSelectedInstOperands,
     /* 45288 */     // GIR_Coverage, 65,
     /* 45288 */     GIR_Done,
     /* 45289 */   // Label 1168: @45289
     /* 45289 */   GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(45316), // Rule ID 1966 //
     /* 45294 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 45297 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 45301 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 45305 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 45309 */     // (sra:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)  =>  (SravRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r, CPU16Regs:{ *:[i32] }:$ra)
     /* 45309 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SravRxRy16),
     /* 45314 */     GIR_RootConstrainSelectedInstOperands,
     /* 45315 */     // GIR_Coverage, 1966,
     /* 45315 */     GIR_Done,
     /* 45316 */   // Label 1169: @45316
     /* 45316 */   GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(45343), // Rule ID 2308 //
     /* 45321 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 45324 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45328 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45332 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45336 */     // (sra:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)  =>  (SRAV_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs)
     /* 45336 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRAV_MM),
     /* 45341 */     GIR_RootConstrainSelectedInstOperands,
     /* 45342 */     // GIR_Coverage, 2308,
     /* 45342 */     GIR_Done,
     /* 45343 */   // Label 1170: @45343
     /* 45343 */   GIM_Reject,
     /* 45344 */ // Label 1164: @45344
     /* 45344 */ GIM_Reject,
     /* 45345 */ // Label 1158: @45345
     /* 45345 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(45485),
     /* 45350 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 45353 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 45356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 45360 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 45364 */   GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(45398), // Rule ID 289 //
     /* 45369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 45372 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45376 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45380 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
     /* 45384 */     // MIs[1] Operand 1
     /* 45384 */     // No operand predicates
     /* 45384 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 45386 */     // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DSRA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 45386 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRA),
     /* 45389 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 45391 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 45393 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 45396 */     GIR_RootConstrainSelectedInstOperands,
     /* 45397 */     // GIR_Coverage, 289,
     /* 45397 */     GIR_EraseRootFromParent_Done,
     /* 45398 */   // Label 1172: @45398
     /* 45398 */   GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(45465), // Rule ID 1681 //
     /* 45403 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 45406 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45410 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 45414 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 45418 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 45423 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 45425 */     // (sra:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DSRAV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
     /* 45425 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 45428 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 45432 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 45437 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
     /* 45443 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /* 45448 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 45453 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
     /* 45456 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 45458 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 45460 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 45463 */     GIR_RootConstrainSelectedInstOperands,
     /* 45464 */     // GIR_Coverage, 1681,
     /* 45464 */     GIR_EraseRootFromParent_Done,
     /* 45465 */   // Label 1173: @45465
     /* 45465 */   GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(45484), // Rule ID 293 //
     /* 45470 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_NotInMicroMips),
     /* 45473 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 45477 */     // (sra:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DSRAV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 45477 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DSRAV),
     /* 45482 */     GIR_RootConstrainSelectedInstOperands,
     /* 45483 */     // GIR_Coverage, 293,
     /* 45483 */     GIR_Done,
     /* 45484 */   // Label 1174: @45484
     /* 45484 */   GIM_Reject,
     /* 45485 */ // Label 1171: @45485
     /* 45485 */ GIM_Reject,
     /* 45486 */ // Label 1159: @45486
     /* 45486 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(45519), // Rule ID 1051 //
     /* 45491 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 45494 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 45497 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 45500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 45504 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 45508 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 45512 */   // (sra:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (SRA_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 45512 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_D),
     /* 45517 */   GIR_RootConstrainSelectedInstOperands,
     /* 45518 */   // GIR_Coverage, 1051,
     /* 45518 */   GIR_Done,
     /* 45519 */ // Label 1175: @45519
     /* 45519 */ GIM_Reject,
     /* 45520 */ // Label 1160: @45520
     /* 45520 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(45787),
     /* 45525 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 45528 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 45531 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 45535 */   GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(45649), // Rule ID 2656 //
     /* 45540 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 45543 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45547 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 45551 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 45555 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 45559 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 45563 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 45567 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 45570 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 45574 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 45578 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 45582 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 45586 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 45590 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45594 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45598 */     // MIs[3] Operand 1
     /* 45598 */     // No operand predicates
     /* 45598 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 45602 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45606 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45610 */     // MIs[4] Operand 1
     /* 45610 */     // No operand predicates
     /* 45610 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 45614 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45618 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45622 */     // MIs[5] Operand 1
     /* 45622 */     // No operand predicates
     /* 45622 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 45626 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45630 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45634 */     // MIs[6] Operand 1
     /* 45634 */     // No operand predicates
     /* 45634 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 45636 */     // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>), v4i32:{ *:[v4i32] }:$wt))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 45636 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
     /* 45639 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 45641 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 45643 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 45647 */     GIR_RootConstrainSelectedInstOperands,
     /* 45648 */     // GIR_Coverage, 2656,
     /* 45648 */     GIR_EraseRootFromParent_Done,
     /* 45649 */   // Label 1177: @45649
     /* 45649 */   GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(45763), // Rule ID 2214 //
     /* 45654 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 45657 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45661 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 45665 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 45669 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 45673 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 45677 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 45681 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/5,
     /* 45684 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 45688 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 45692 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 45696 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 45700 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 45704 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45708 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45712 */     // MIs[3] Operand 1
     /* 45712 */     // No operand predicates
     /* 45712 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 45716 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45720 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45724 */     // MIs[4] Operand 1
     /* 45724 */     // No operand predicates
     /* 45724 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 45728 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45732 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45736 */     // MIs[5] Operand 1
     /* 45736 */     // No operand predicates
     /* 45736 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 45740 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45744 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst31),
     /* 45748 */     // MIs[6] Operand 1
     /* 45748 */     // No operand predicates
     /* 45748 */     GIM_CheckIsSafeToFold, /*NumInsns*/6,
     /* 45750 */     // (sra:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, (and:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$wt, (build_vector:{ *:[v4i32] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst31>>)))  =>  (SRA_W:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$ws, v4i32:{ *:[v4i32] }:$wt)
     /* 45750 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
     /* 45753 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 45755 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 45757 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 45761 */     GIR_RootConstrainSelectedInstOperands,
     /* 45762 */     // GIR_Coverage, 2214,
     /* 45762 */     GIR_EraseRootFromParent_Done,
     /* 45763 */   // Label 1178: @45763
     /* 45763 */   GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(45786), // Rule ID 1050 //
     /* 45768 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 45771 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 45775 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 45779 */     // (sra:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (SRA_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 45779 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_W),
     /* 45784 */     GIR_RootConstrainSelectedInstOperands,
     /* 45785 */     // GIR_Coverage, 1050,
     /* 45785 */     GIR_Done,
     /* 45786 */   // Label 1179: @45786
     /* 45786 */   GIM_Reject,
     /* 45787 */ // Label 1176: @45787
     /* 45787 */ GIM_Reject,
     /* 45788 */ // Label 1161: @45788
     /* 45788 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(46183),
     /* 45793 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 45796 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 45799 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 45803 */   GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(45981), // Rule ID 2655 //
     /* 45808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 45811 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45815 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 45819 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 45823 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 45827 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 45831 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 45835 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 45838 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 45842 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 45846 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 45850 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 45854 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 45858 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 45862 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 45866 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 45870 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 45874 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45878 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45882 */     // MIs[3] Operand 1
     /* 45882 */     // No operand predicates
     /* 45882 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 45886 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45890 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45894 */     // MIs[4] Operand 1
     /* 45894 */     // No operand predicates
     /* 45894 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 45898 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45902 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45906 */     // MIs[5] Operand 1
     /* 45906 */     // No operand predicates
     /* 45906 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 45910 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45914 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45918 */     // MIs[6] Operand 1
     /* 45918 */     // No operand predicates
     /* 45918 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 45922 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45926 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45930 */     // MIs[7] Operand 1
     /* 45930 */     // No operand predicates
     /* 45930 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 45934 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45938 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45942 */     // MIs[8] Operand 1
     /* 45942 */     // No operand predicates
     /* 45942 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 45946 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45950 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45954 */     // MIs[9] Operand 1
     /* 45954 */     // No operand predicates
     /* 45954 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 45958 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 45962 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 45966 */     // MIs[10] Operand 1
     /* 45966 */     // No operand predicates
     /* 45966 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 45968 */     // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>), v8i16:{ *:[v8i16] }:$wt))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 45968 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
     /* 45971 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 45973 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 45975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 45979 */     GIR_RootConstrainSelectedInstOperands,
     /* 45980 */     // GIR_Coverage, 2655,
     /* 45980 */     GIR_EraseRootFromParent_Done,
     /* 45981 */   // Label 1181: @45981
     /* 45981 */   GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(46159), // Rule ID 2213 //
     /* 45986 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 45989 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 45993 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 45997 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 46001 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 46005 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 46009 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 46013 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/9,
     /* 46016 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 46020 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 46024 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 46028 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 46032 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 46036 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 46040 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 46044 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 46048 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 46052 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46056 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46060 */     // MIs[3] Operand 1
     /* 46060 */     // No operand predicates
     /* 46060 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 46064 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46068 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46072 */     // MIs[4] Operand 1
     /* 46072 */     // No operand predicates
     /* 46072 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 46076 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46080 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46084 */     // MIs[5] Operand 1
     /* 46084 */     // No operand predicates
     /* 46084 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 46088 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46092 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46096 */     // MIs[6] Operand 1
     /* 46096 */     // No operand predicates
     /* 46096 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 46100 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46104 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46108 */     // MIs[7] Operand 1
     /* 46108 */     // No operand predicates
     /* 46108 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 46112 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46116 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46120 */     // MIs[8] Operand 1
     /* 46120 */     // No operand predicates
     /* 46120 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 46124 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46128 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46132 */     // MIs[9] Operand 1
     /* 46132 */     // No operand predicates
     /* 46132 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 46136 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46140 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst15),
     /* 46144 */     // MIs[10] Operand 1
     /* 46144 */     // No operand predicates
     /* 46144 */     GIM_CheckIsSafeToFold, /*NumInsns*/10,
     /* 46146 */     // (sra:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, (and:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$wt, (build_vector:{ *:[v8i16] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst15>>)))  =>  (SRA_H:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$ws, v8i16:{ *:[v8i16] }:$wt)
     /* 46146 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
     /* 46149 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 46151 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 46153 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 46157 */     GIR_RootConstrainSelectedInstOperands,
     /* 46158 */     // GIR_Coverage, 2213,
     /* 46158 */     GIR_EraseRootFromParent_Done,
     /* 46159 */   // Label 1182: @46159
     /* 46159 */   GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(46182), // Rule ID 1049 //
     /* 46164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 46167 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 46171 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 46175 */     // (sra:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (SRA_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 46175 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_H),
     /* 46180 */     GIR_RootConstrainSelectedInstOperands,
     /* 46181 */     // GIR_Coverage, 1049,
     /* 46181 */     GIR_Done,
     /* 46182 */   // Label 1183: @46182
     /* 46182 */   GIM_Reject,
     /* 46183 */ // Label 1180: @46183
     /* 46183 */ GIM_Reject,
     /* 46184 */ // Label 1162: @46184
     /* 46184 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(46835),
     /* 46189 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 46192 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 46195 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 46199 */   GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(46505), // Rule ID 2654 //
     /* 46204 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 46207 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 46211 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 46215 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 46219 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 46223 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 46227 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 46231 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 46234 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 46238 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 46242 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 46246 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 46250 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 46254 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 46258 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 46262 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 46266 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 46270 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 46274 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 46278 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 46282 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 46286 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 46290 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 46294 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 46298 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 46302 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46306 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46310 */     // MIs[3] Operand 1
     /* 46310 */     // No operand predicates
     /* 46310 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 46314 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46318 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46322 */     // MIs[4] Operand 1
     /* 46322 */     // No operand predicates
     /* 46322 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 46326 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46330 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46334 */     // MIs[5] Operand 1
     /* 46334 */     // No operand predicates
     /* 46334 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 46338 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46342 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46346 */     // MIs[6] Operand 1
     /* 46346 */     // No operand predicates
     /* 46346 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 46350 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46354 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46358 */     // MIs[7] Operand 1
     /* 46358 */     // No operand predicates
     /* 46358 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 46362 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46366 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46370 */     // MIs[8] Operand 1
     /* 46370 */     // No operand predicates
     /* 46370 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 46374 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46378 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46382 */     // MIs[9] Operand 1
     /* 46382 */     // No operand predicates
     /* 46382 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 46386 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46390 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46394 */     // MIs[10] Operand 1
     /* 46394 */     // No operand predicates
     /* 46394 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 46398 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46402 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46406 */     // MIs[11] Operand 1
     /* 46406 */     // No operand predicates
     /* 46406 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 46410 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46414 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46418 */     // MIs[12] Operand 1
     /* 46418 */     // No operand predicates
     /* 46418 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 46422 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46426 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46430 */     // MIs[13] Operand 1
     /* 46430 */     // No operand predicates
     /* 46430 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 46434 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46438 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46442 */     // MIs[14] Operand 1
     /* 46442 */     // No operand predicates
     /* 46442 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 46446 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46450 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46454 */     // MIs[15] Operand 1
     /* 46454 */     // No operand predicates
     /* 46454 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 46458 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46462 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46466 */     // MIs[16] Operand 1
     /* 46466 */     // No operand predicates
     /* 46466 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 46470 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46474 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46478 */     // MIs[17] Operand 1
     /* 46478 */     // No operand predicates
     /* 46478 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 46482 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46486 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46490 */     // MIs[18] Operand 1
     /* 46490 */     // No operand predicates
     /* 46490 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 46492 */     // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>), v16i8:{ *:[v16i8] }:$wt))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 46492 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
     /* 46495 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 46497 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 46499 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 46503 */     GIR_RootConstrainSelectedInstOperands,
     /* 46504 */     // GIR_Coverage, 2654,
     /* 46504 */     GIR_EraseRootFromParent_Done,
     /* 46505 */   // Label 1185: @46505
     /* 46505 */   GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(46811), // Rule ID 2212 //
     /* 46510 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 46513 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 46517 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
     /* 46521 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 46525 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 46529 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 46533 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
     /* 46537 */     GIM_CheckNumOperands, /*MI*/2, /*Expected*/17,
     /* 46540 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 46544 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 46548 */     GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
     /* 46552 */     GIM_CheckType, /*MI*/2, /*Op*/4, /*Type*/GILLT_s32,
     /* 46556 */     GIM_CheckType, /*MI*/2, /*Op*/5, /*Type*/GILLT_s32,
     /* 46560 */     GIM_CheckType, /*MI*/2, /*Op*/6, /*Type*/GILLT_s32,
     /* 46564 */     GIM_CheckType, /*MI*/2, /*Op*/7, /*Type*/GILLT_s32,
     /* 46568 */     GIM_CheckType, /*MI*/2, /*Op*/8, /*Type*/GILLT_s32,
     /* 46572 */     GIM_CheckType, /*MI*/2, /*Op*/9, /*Type*/GILLT_s32,
     /* 46576 */     GIM_CheckType, /*MI*/2, /*Op*/10, /*Type*/GILLT_s32,
     /* 46580 */     GIM_CheckType, /*MI*/2, /*Op*/11, /*Type*/GILLT_s32,
     /* 46584 */     GIM_CheckType, /*MI*/2, /*Op*/12, /*Type*/GILLT_s32,
     /* 46588 */     GIM_CheckType, /*MI*/2, /*Op*/13, /*Type*/GILLT_s32,
     /* 46592 */     GIM_CheckType, /*MI*/2, /*Op*/14, /*Type*/GILLT_s32,
     /* 46596 */     GIM_CheckType, /*MI*/2, /*Op*/15, /*Type*/GILLT_s32,
     /* 46600 */     GIM_CheckType, /*MI*/2, /*Op*/16, /*Type*/GILLT_s32,
     /* 46604 */     GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
     /* 46608 */     GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46612 */     GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46616 */     // MIs[3] Operand 1
     /* 46616 */     // No operand predicates
     /* 46616 */     GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
     /* 46620 */     GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46624 */     GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46628 */     // MIs[4] Operand 1
     /* 46628 */     // No operand predicates
     /* 46628 */     GIM_RecordInsn, /*DefineMI*/5, /*MI*/2, /*OpIdx*/3, // MIs[5]
     /* 46632 */     GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46636 */     GIM_CheckI64ImmPredicate, /*MI*/5, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46640 */     // MIs[5] Operand 1
     /* 46640 */     // No operand predicates
     /* 46640 */     GIM_RecordInsn, /*DefineMI*/6, /*MI*/2, /*OpIdx*/4, // MIs[6]
     /* 46644 */     GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46648 */     GIM_CheckI64ImmPredicate, /*MI*/6, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46652 */     // MIs[6] Operand 1
     /* 46652 */     // No operand predicates
     /* 46652 */     GIM_RecordInsn, /*DefineMI*/7, /*MI*/2, /*OpIdx*/5, // MIs[7]
     /* 46656 */     GIM_CheckOpcode, /*MI*/7, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46660 */     GIM_CheckI64ImmPredicate, /*MI*/7, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46664 */     // MIs[7] Operand 1
     /* 46664 */     // No operand predicates
     /* 46664 */     GIM_RecordInsn, /*DefineMI*/8, /*MI*/2, /*OpIdx*/6, // MIs[8]
     /* 46668 */     GIM_CheckOpcode, /*MI*/8, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46672 */     GIM_CheckI64ImmPredicate, /*MI*/8, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46676 */     // MIs[8] Operand 1
     /* 46676 */     // No operand predicates
     /* 46676 */     GIM_RecordInsn, /*DefineMI*/9, /*MI*/2, /*OpIdx*/7, // MIs[9]
     /* 46680 */     GIM_CheckOpcode, /*MI*/9, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46684 */     GIM_CheckI64ImmPredicate, /*MI*/9, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46688 */     // MIs[9] Operand 1
     /* 46688 */     // No operand predicates
     /* 46688 */     GIM_RecordInsn, /*DefineMI*/10, /*MI*/2, /*OpIdx*/8, // MIs[10]
     /* 46692 */     GIM_CheckOpcode, /*MI*/10, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46696 */     GIM_CheckI64ImmPredicate, /*MI*/10, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46700 */     // MIs[10] Operand 1
     /* 46700 */     // No operand predicates
     /* 46700 */     GIM_RecordInsn, /*DefineMI*/11, /*MI*/2, /*OpIdx*/9, // MIs[11]
     /* 46704 */     GIM_CheckOpcode, /*MI*/11, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46708 */     GIM_CheckI64ImmPredicate, /*MI*/11, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46712 */     // MIs[11] Operand 1
     /* 46712 */     // No operand predicates
     /* 46712 */     GIM_RecordInsn, /*DefineMI*/12, /*MI*/2, /*OpIdx*/10, // MIs[12]
     /* 46716 */     GIM_CheckOpcode, /*MI*/12, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46720 */     GIM_CheckI64ImmPredicate, /*MI*/12, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46724 */     // MIs[12] Operand 1
     /* 46724 */     // No operand predicates
     /* 46724 */     GIM_RecordInsn, /*DefineMI*/13, /*MI*/2, /*OpIdx*/11, // MIs[13]
     /* 46728 */     GIM_CheckOpcode, /*MI*/13, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46732 */     GIM_CheckI64ImmPredicate, /*MI*/13, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46736 */     // MIs[13] Operand 1
     /* 46736 */     // No operand predicates
     /* 46736 */     GIM_RecordInsn, /*DefineMI*/14, /*MI*/2, /*OpIdx*/12, // MIs[14]
     /* 46740 */     GIM_CheckOpcode, /*MI*/14, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46744 */     GIM_CheckI64ImmPredicate, /*MI*/14, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46748 */     // MIs[14] Operand 1
     /* 46748 */     // No operand predicates
     /* 46748 */     GIM_RecordInsn, /*DefineMI*/15, /*MI*/2, /*OpIdx*/13, // MIs[15]
     /* 46752 */     GIM_CheckOpcode, /*MI*/15, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46756 */     GIM_CheckI64ImmPredicate, /*MI*/15, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46760 */     // MIs[15] Operand 1
     /* 46760 */     // No operand predicates
     /* 46760 */     GIM_RecordInsn, /*DefineMI*/16, /*MI*/2, /*OpIdx*/14, // MIs[16]
     /* 46764 */     GIM_CheckOpcode, /*MI*/16, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46768 */     GIM_CheckI64ImmPredicate, /*MI*/16, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46772 */     // MIs[16] Operand 1
     /* 46772 */     // No operand predicates
     /* 46772 */     GIM_RecordInsn, /*DefineMI*/17, /*MI*/2, /*OpIdx*/15, // MIs[17]
     /* 46776 */     GIM_CheckOpcode, /*MI*/17, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46780 */     GIM_CheckI64ImmPredicate, /*MI*/17, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46784 */     // MIs[17] Operand 1
     /* 46784 */     // No operand predicates
     /* 46784 */     GIM_RecordInsn, /*DefineMI*/18, /*MI*/2, /*OpIdx*/16, // MIs[18]
     /* 46788 */     GIM_CheckOpcode, /*MI*/18, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46792 */     GIM_CheckI64ImmPredicate, /*MI*/18, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immi32Cst7),
     /* 46796 */     // MIs[18] Operand 1
     /* 46796 */     // No operand predicates
     /* 46796 */     GIM_CheckIsSafeToFold, /*NumInsns*/18,
     /* 46798 */     // (sra:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, (and:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$wt, (build_vector:{ *:[v16i8] } (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>, (imm:{ *:[i32] })<<P:Predicate_immi32Cst7>>)))  =>  (SRA_B:{ *:[v16i8] } v16i8:{ *:[v16i8] }:$ws, v16i8:{ *:[v16i8] }:$wt)
     /* 46798 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
     /* 46801 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 46803 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 46805 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 46809 */     GIR_RootConstrainSelectedInstOperands,
     /* 46810 */     // GIR_Coverage, 2212,
     /* 46810 */     GIR_EraseRootFromParent_Done,
     /* 46811 */   // Label 1186: @46811
     /* 46811 */   GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(46834), // Rule ID 1048 //
     /* 46816 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 46819 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 46823 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 46827 */     // (sra:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (SRA_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 46827 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::SRA_B),
     /* 46832 */     GIR_RootConstrainSelectedInstOperands,
     /* 46833 */     // GIR_Coverage, 1048,
     /* 46833 */     GIR_Done,
     /* 46834 */   // Label 1187: @46834
     /* 46834 */   GIM_Reject,
     /* 46835 */ // Label 1184: @46835
     /* 46835 */ GIM_Reject,
     /* 46836 */ // Label 1163: @46836
     /* 46836 */ GIM_Reject,
     /* 46837 */ // Label 40: @46837
     /* 46837 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(47124),
     /* 46848 */ /*GILLT_s32*//*Label 1188*/ GIMT_Encode4(46856),
     /* 46852 */ /*GILLT_s64*//*Label 1189*/ GIMT_Encode4(46983),
     /* 46856 */ // Label 1188: @46856
     /* 46856 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(46982),
     /* 46861 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 46864 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 46867 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 46871 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 46875 */   GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(46909), // Rule ID 67 //
     /* 46880 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
     /* 46883 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 46887 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46891 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 46895 */     // MIs[1] Operand 1
     /* 46895 */     // No operand predicates
     /* 46895 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 46897 */     // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (ROTR:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 46897 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
     /* 46900 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 46902 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 46904 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 46907 */     GIR_RootConstrainSelectedInstOperands,
     /* 46908 */     // GIR_Coverage, 67,
     /* 46908 */     GIR_EraseRootFromParent_Done,
     /* 46909 */   // Label 1192: @46909
     /* 46909 */   GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(46943), // Rule ID 1156 //
     /* 46914 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 46917 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 46921 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 46925 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt5),
     /* 46929 */     // MIs[1] Operand 1
     /* 46929 */     // No operand predicates
     /* 46929 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 46931 */     // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt5>>:$shamt)  =>  (ROTR_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 46931 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
     /* 46934 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 46936 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 46938 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 46941 */     GIR_RootConstrainSelectedInstOperands,
     /* 46942 */     // GIR_Coverage, 1156,
     /* 46942 */     GIR_EraseRootFromParent_Done,
     /* 46943 */   // Label 1193: @46943
     /* 46943 */   GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(46962), // Rule ID 68 //
     /* 46948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
     /* 46951 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 46955 */     // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ROTRV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 46955 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV),
     /* 46960 */     GIR_RootConstrainSelectedInstOperands,
     /* 46961 */     // GIR_Coverage, 68,
     /* 46961 */     GIR_Done,
     /* 46962 */   // Label 1194: @46962
     /* 46962 */   GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(46981), // Rule ID 1157 //
     /* 46967 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 46970 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 46974 */     // (rotr:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (ROTRV_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 46974 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::ROTRV_MM),
     /* 46979 */     GIR_RootConstrainSelectedInstOperands,
     /* 46980 */     // GIR_Coverage, 1157,
     /* 46980 */     GIR_Done,
     /* 46981 */   // Label 1195: @46981
     /* 46981 */   GIM_Reject,
     /* 46982 */ // Label 1191: @46982
     /* 46982 */ GIM_Reject,
     /* 46983 */ // Label 1189: @46983
     /* 46983 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(47123),
     /* 46988 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 46991 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 46994 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 46998 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47002 */   GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(47036), // Rule ID 297 //
     /* 47007 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
     /* 47010 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 47014 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 47018 */     GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt6),
     /* 47022 */     // MIs[1] Operand 1
     /* 47022 */     // No operand predicates
     /* 47022 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 47024 */     // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] })<<P:Predicate_immZExt6>>:$shamt)  =>  (DROTR:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$shamt)
     /* 47024 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTR),
     /* 47027 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47029 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 47031 */     GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt
     /* 47034 */     GIR_RootConstrainSelectedInstOperands,
     /* 47035 */     // GIR_Coverage, 297,
     /* 47035 */     GIR_EraseRootFromParent_Done,
     /* 47036 */   // Label 1197: @47036
     /* 47036 */   GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(47103), // Rule ID 1682 //
     /* 47041 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit),
     /* 47044 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 47048 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
     /* 47052 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 47056 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47061 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 47063 */     // (rotr:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (trunc:{ *:[i32] } GPR64:{ *:[i64] }:$rs))  =>  (DROTRV:{ *:[i64] } GPR64:{ *:[i64] }:$rt, (EXTRACT_SUBREG:{ *:[i32] } GPR64:{ *:[i64] }:$rs, sub_32:{ *:[i32] }))
     /* 47063 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47066 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 47070 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47075 */     GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // rs
     /* 47081 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Mips::DSPRRegClassID),
     /* 47086 */     GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47091 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
     /* 47094 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47096 */     GIR_RootToRootCopy, /*OpIdx*/1, // rt
     /* 47098 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 47101 */     GIR_RootConstrainSelectedInstOperands,
     /* 47102 */     // GIR_Coverage, 1682,
     /* 47102 */     GIR_EraseRootFromParent_Done,
     /* 47103 */   // Label 1198: @47103
     /* 47103 */   GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(47122), // Rule ID 298 //
     /* 47108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips),
     /* 47111 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47115 */     // (rotr:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)  =>  (DROTRV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, GPR32Opnd:{ *:[i32] }:$rs)
     /* 47115 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DROTRV),
     /* 47120 */     GIR_RootConstrainSelectedInstOperands,
     /* 47121 */     // GIR_Coverage, 298,
     /* 47121 */     GIR_Done,
     /* 47122 */   // Label 1199: @47122
     /* 47122 */   GIM_Reject,
     /* 47123 */ // Label 1196: @47123
     /* 47123 */ GIM_Reject,
     /* 47124 */ // Label 1190: @47124
     /* 47124 */ GIM_Reject,
     /* 47125 */ // Label 41: @47125
     /* 47125 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(49655),
     /* 47130 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 47133 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1203*/ GIMT_Encode4(47318),
     /* 47144 */   /*GILLT_s32*//*Label 1201*/ GIMT_Encode4(47152),
     /* 47148 */   /*GILLT_s64*//*Label 1202*/ GIMT_Encode4(47235),
     /* 47152 */   // Label 1201: @47152
     /* 47152 */   GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(47234),
     /* 47157 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 47160 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47164 */     GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(47197), // Rule ID 1490 //
     /* 47169 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47172 */       // MIs[0] Operand 1
     /* 47172 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 47177 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47181 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47185 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
     /* 47185 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
     /* 47188 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 47190 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47192 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47195 */       GIR_RootConstrainSelectedInstOperands,
     /* 47196 */       // GIR_Coverage, 1490,
     /* 47196 */       GIR_EraseRootFromParent_Done,
     /* 47197 */     // Label 1205: @47197
     /* 47197 */     GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(47233), // Rule ID 1491 //
     /* 47202 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47205 */       // MIs[0] Operand 1
     /* 47205 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 47210 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47214 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47218 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
     /* 47218 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 47221 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47223 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 47229 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47231 */       GIR_RootConstrainSelectedInstOperands,
     /* 47232 */       // GIR_Coverage, 1491,
     /* 47232 */       GIR_EraseRootFromParent_Done,
     /* 47233 */     // Label 1206: @47233
     /* 47233 */     GIM_Reject,
     /* 47234 */   // Label 1204: @47234
     /* 47234 */   GIM_Reject,
     /* 47235 */   // Label 1202: @47235
     /* 47235 */   GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(47317),
     /* 47240 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 47243 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47247 */     GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(47280), // Rule ID 1664 //
     /* 47252 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 47255 */       // MIs[0] Operand 1
     /* 47255 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 47260 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47264 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47268 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 1:{ *:[i64] })
     /* 47268 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
     /* 47271 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 47273 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47275 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47278 */       GIR_RootConstrainSelectedInstOperands,
     /* 47279 */       // GIR_Coverage, 1664,
     /* 47279 */       GIR_EraseRootFromParent_Done,
     /* 47280 */     // Label 1208: @47280
     /* 47280 */     GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(47316), // Rule ID 1665 //
     /* 47285 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 47288 */       // MIs[0] Operand 1
     /* 47288 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 47293 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47297 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47301 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, GPR64:{ *:[i64] }:$lhs)
     /* 47301 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 47304 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47306 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 47312 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47314 */       GIR_RootConstrainSelectedInstOperands,
     /* 47315 */       // GIR_Coverage, 1665,
     /* 47315 */       GIR_EraseRootFromParent_Done,
     /* 47316 */     // Label 1209: @47316
     /* 47316 */     GIM_Reject,
     /* 47317 */   // Label 1207: @47317
     /* 47317 */   GIM_Reject,
     /* 47318 */   // Label 1203: @47318
     /* 47318 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1212*/ GIMT_Encode4(47701),
     /* 47329 */   /*GILLT_s32*//*Label 1210*/ GIMT_Encode4(47337),
     /* 47333 */   /*GILLT_s64*//*Label 1211*/ GIMT_Encode4(47623),
     /* 47337 */   // Label 1210: @47337
     /* 47337 */   GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(47622),
     /* 47342 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 47345 */     GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(47382), // Rule ID 2014 //
     /* 47350 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 47353 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 47357 */       // MIs[0] Operand 1
     /* 47357 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 47362 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 47366 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47370 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, 1:{ *:[i32] })
     /* 47370 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
     /* 47373 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 47375 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47377 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47380 */       GIR_RootConstrainSelectedInstOperands,
     /* 47381 */       // GIR_Coverage, 2014,
     /* 47381 */       GIR_EraseRootFromParent_Done,
     /* 47382 */     // Label 1214: @47382
     /* 47382 */     GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(47472), // Rule ID 2016 //
     /* 47387 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 47390 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 47394 */       // MIs[0] Operand 1
     /* 47394 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 47399 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 47403 */       GIM_CheckConstantInt, /*MI*/0, /*Op*/3, GIMT_Encode8(18446744073709518847u),
     /* 47414 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32769:{ *:[i32] }, SETGT:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltiCCRxImmX16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, -32768:{ *:[i32] }), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
     /* 47414 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 47417 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
     /* 47421 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47426 */       GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 47429 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 47431 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47434 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltiCCRxImmX16),
     /* 47438 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47443 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 47447 */       GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
     /* 47457 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 47459 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 47462 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
     /* 47464 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 47467 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 47470 */       GIR_RootConstrainSelectedInstOperands,
     /* 47471 */       // GIR_Coverage, 2016,
     /* 47471 */       GIR_EraseRootFromParent_Done,
     /* 47472 */     // Label 1215: @47472
     /* 47472 */     GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(47509), // Rule ID 2335 //
     /* 47477 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 47480 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47484 */       // MIs[0] Operand 1
     /* 47484 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 47489 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47493 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47497 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 1:{ *:[i32] })
     /* 47497 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
     /* 47500 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 47502 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47504 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47507 */       GIR_RootConstrainSelectedInstOperands,
     /* 47508 */       // GIR_Coverage, 2335,
     /* 47508 */       GIR_EraseRootFromParent_Done,
     /* 47509 */     // Label 1216: @47509
     /* 47509 */     GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(47549), // Rule ID 2336 //
     /* 47514 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 47517 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47521 */       // MIs[0] Operand 1
     /* 47521 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 47526 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47530 */       GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
     /* 47534 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, GPR32:{ *:[i32] }:$lhs)
     /* 47534 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 47537 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47539 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 47545 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 47547 */       GIR_RootConstrainSelectedInstOperands,
     /* 47548 */       // GIR_Coverage, 2336,
     /* 47548 */       GIR_EraseRootFromParent_Done,
     /* 47549 */     // Label 1217: @47549
     /* 47549 */     GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(47585), // Rule ID 49 //
     /* 47554 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47557 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47561 */       // MIs[0] Operand 1
     /* 47561 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 47566 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47570 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47574 */       // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 47574 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 47577 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47579 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47581 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47583 */       GIR_RootConstrainSelectedInstOperands,
     /* 47584 */       // GIR_Coverage, 49,
     /* 47584 */       GIR_EraseRootFromParent_Done,
     /* 47585 */     // Label 1218: @47585
     /* 47585 */     GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(47621), // Rule ID 50 //
     /* 47590 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47593 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47597 */       // MIs[0] Operand 1
     /* 47597 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 47602 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47606 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47610 */       // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 47610 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 47613 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47615 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47617 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47619 */       GIR_RootConstrainSelectedInstOperands,
     /* 47620 */       // GIR_Coverage, 50,
     /* 47620 */       GIR_EraseRootFromParent_Done,
     /* 47621 */     // Label 1219: @47621
     /* 47621 */     GIM_Reject,
     /* 47622 */   // Label 1213: @47622
     /* 47622 */   GIM_Reject,
     /* 47623 */   // Label 1211: @47623
     /* 47623 */   GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(47700),
     /* 47628 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 47631 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47635 */     GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(47667), // Rule ID 279 //
     /* 47640 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 47643 */       // MIs[0] Operand 1
     /* 47643 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 47648 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47652 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47656 */       // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETLT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 47656 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 47659 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47661 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47663 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47665 */       GIR_RootConstrainSelectedInstOperands,
     /* 47666 */       // GIR_Coverage, 279,
     /* 47666 */       GIR_EraseRootFromParent_Done,
     /* 47667 */     // Label 1221: @47667
     /* 47667 */     GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(47699), // Rule ID 280 //
     /* 47672 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsGP64bit_NotInMips16Mode),
     /* 47675 */       // MIs[0] Operand 1
     /* 47675 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 47680 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47684 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 47688 */       // (setcc:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 47688 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 47691 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47693 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47695 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47697 */       GIR_RootConstrainSelectedInstOperands,
     /* 47698 */       // GIR_Coverage, 280,
     /* 47698 */       GIR_EraseRootFromParent_Done,
     /* 47699 */     // Label 1222: @47699
     /* 47699 */     GIM_Reject,
     /* 47700 */   // Label 1220: @47700
     /* 47700 */   GIM_Reject,
     /* 47701 */   // Label 1212: @47701
     /* 47701 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1225*/ GIMT_Encode4(48618),
     /* 47712 */   /*GILLT_s32*//*Label 1223*/ GIMT_Encode4(47720),
     /* 47716 */   /*GILLT_s64*//*Label 1224*/ GIMT_Encode4(48201),
     /* 47720 */   // Label 1223: @47720
     /* 47720 */   GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(48200),
     /* 47725 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 47728 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47732 */     GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(47764), // Rule ID 1150 //
     /* 47737 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 47740 */       // MIs[0] Operand 1
     /* 47740 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 47745 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47749 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47753 */       // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETLT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 47753 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 47756 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47758 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47760 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47762 */       GIR_RootConstrainSelectedInstOperands,
     /* 47763 */       // GIR_Coverage, 1150,
     /* 47763 */       GIR_EraseRootFromParent_Done,
     /* 47764 */     // Label 1227: @47764
     /* 47764 */     GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(47796), // Rule ID 1151 //
     /* 47769 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 47772 */       // MIs[0] Operand 1
     /* 47772 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 47777 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47781 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47785 */       // (setcc:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, SETULT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 47785 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 47788 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47790 */       GIR_RootToRootCopy, /*OpIdx*/2, // rs
     /* 47792 */       GIR_RootToRootCopy, /*OpIdx*/3, // rt
     /* 47794 */       GIR_RootConstrainSelectedInstOperands,
     /* 47795 */       // GIR_Coverage, 1151,
     /* 47795 */       GIR_EraseRootFromParent_Done,
     /* 47796 */     // Label 1228: @47796
     /* 47796 */     GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(47852), // Rule ID 1492 //
     /* 47801 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47804 */       // MIs[0] Operand 1
     /* 47804 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 47809 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47813 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47817 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu:{ *:[i32] } (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 47817 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47820 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 47824 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47829 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 47833 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 47837 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 47839 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu),
     /* 47842 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 47844 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 47847 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47850 */       GIR_RootConstrainSelectedInstOperands,
     /* 47851 */       // GIR_Coverage, 1492,
     /* 47851 */       GIR_EraseRootFromParent_Done,
     /* 47852 */     // Label 1229: @47852
     /* 47852 */     GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(47911), // Rule ID 1493 //
     /* 47857 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47860 */       // MIs[0] Operand 1
     /* 47860 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 47865 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47869 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47873 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu:{ *:[i32] } ZERO:{ *:[i32] }, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
     /* 47873 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47876 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 47880 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47885 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 47889 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 47893 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 47895 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 47898 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 47900 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 47906 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 47909 */       GIR_RootConstrainSelectedInstOperands,
     /* 47910 */       // GIR_Coverage, 1493,
     /* 47910 */       GIR_EraseRootFromParent_Done,
     /* 47911 */     // Label 1230: @47911
     /* 47911 */     GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(47967), // Rule ID 1494 //
     /* 47916 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47919 */       // MIs[0] Operand 1
     /* 47919 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 47924 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47928 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47932 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
     /* 47932 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47935 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 47939 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 47944 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 47948 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 47952 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 47954 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 47957 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 47959 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 47962 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 47965 */       GIR_RootConstrainSelectedInstOperands,
     /* 47966 */       // GIR_Coverage, 1494,
     /* 47966 */       GIR_EraseRootFromParent_Done,
     /* 47967 */     // Label 1231: @47967
     /* 47967 */     GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(48023), // Rule ID 1495 //
     /* 47972 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 47975 */       // MIs[0] Operand 1
     /* 47975 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 47980 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47984 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 47988 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
     /* 47988 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 47991 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 47995 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48000 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48004 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48008 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48010 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48013 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48015 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48018 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48021 */       GIR_RootConstrainSelectedInstOperands,
     /* 48022 */       // GIR_Coverage, 1495,
     /* 48022 */       GIR_EraseRootFromParent_Done,
     /* 48023 */     // Label 1232: @48023
     /* 48023 */     GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(48055), // Rule ID 1496 //
     /* 48028 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 48031 */       // MIs[0] Operand 1
     /* 48031 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 48036 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48040 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48044 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
     /* 48044 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 48047 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 48049 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 48051 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 48053 */       GIR_RootConstrainSelectedInstOperands,
     /* 48054 */       // GIR_Coverage, 1496,
     /* 48054 */       GIR_EraseRootFromParent_Done,
     /* 48055 */     // Label 1233: @48055
     /* 48055 */     GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(48087), // Rule ID 1497 //
     /* 48060 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 48063 */       // MIs[0] Operand 1
     /* 48063 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 48068 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48072 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48076 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
     /* 48076 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 48079 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 48081 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 48083 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 48085 */       GIR_RootConstrainSelectedInstOperands,
     /* 48086 */       // GIR_Coverage, 1497,
     /* 48086 */       GIR_EraseRootFromParent_Done,
     /* 48087 */     // Label 1234: @48087
     /* 48087 */     GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(48143), // Rule ID 1498 //
     /* 48092 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 48095 */       // MIs[0] Operand 1
     /* 48095 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 48100 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48104 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48108 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 48108 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48111 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 48115 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48120 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48124 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48128 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48130 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48133 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48135 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48138 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48141 */       GIR_RootConstrainSelectedInstOperands,
     /* 48142 */       // GIR_Coverage, 1498,
     /* 48142 */       GIR_EraseRootFromParent_Done,
     /* 48143 */     // Label 1235: @48143
     /* 48143 */     GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(48199), // Rule ID 1499 //
     /* 48148 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 48151 */       // MIs[0] Operand 1
     /* 48151 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 48156 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48160 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48164 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 48164 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48167 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 48171 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48176 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48180 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48184 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48186 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48189 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48191 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48194 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48197 */       GIR_RootConstrainSelectedInstOperands,
     /* 48198 */       // GIR_Coverage, 1499,
     /* 48198 */       GIR_EraseRootFromParent_Done,
     /* 48199 */     // Label 1236: @48199
     /* 48199 */     GIM_Reject,
     /* 48200 */   // Label 1226: @48200
     /* 48200 */   GIM_Reject,
     /* 48201 */   // Label 1224: @48201
     /* 48201 */   GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(48617),
     /* 48206 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 48209 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 48213 */     GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(48269), // Rule ID 1666 //
     /* 48218 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48221 */       // MIs[0] Operand 1
     /* 48221 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 48226 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48230 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48234 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu64:{ *:[i32] } (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i64] })
     /* 48234 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 48237 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 48241 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48246 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48250 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48254 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48256 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu64),
     /* 48259 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48261 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48264 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48267 */       GIR_RootConstrainSelectedInstOperands,
     /* 48268 */       // GIR_Coverage, 1666,
     /* 48268 */       GIR_EraseRootFromParent_Done,
     /* 48269 */     // Label 1238: @48269
     /* 48269 */     GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(48328), // Rule ID 1667 //
     /* 48274 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48277 */       // MIs[0] Operand 1
     /* 48277 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 48282 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48286 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48290 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } ZERO_64:{ *:[i64] }, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs))
     /* 48290 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 48293 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 48297 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48302 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48306 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48310 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48312 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 48315 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 48317 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO_64), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 48323 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48326 */       GIR_RootConstrainSelectedInstOperands,
     /* 48327 */       // GIR_Coverage, 1667,
     /* 48327 */       GIR_EraseRootFromParent_Done,
     /* 48328 */     // Label 1239: @48328
     /* 48328 */     GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(48384), // Rule ID 1668 //
     /* 48333 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48336 */       // MIs[0] Operand 1
     /* 48336 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 48341 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48345 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48349 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
     /* 48349 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48352 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 48356 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48361 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48365 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48369 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48371 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48374 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48376 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48379 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48382 */       GIR_RootConstrainSelectedInstOperands,
     /* 48383 */       // GIR_Coverage, 1668,
     /* 48383 */       GIR_EraseRootFromParent_Done,
     /* 48384 */     // Label 1240: @48384
     /* 48384 */     GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(48440), // Rule ID 1669 //
     /* 48389 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48392 */       // MIs[0] Operand 1
     /* 48392 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 48397 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48401 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48405 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), 1:{ *:[i32] })
     /* 48405 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48408 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 48412 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48417 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48421 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48425 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48427 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48430 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48432 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48435 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48438 */       GIR_RootConstrainSelectedInstOperands,
     /* 48439 */       // GIR_Coverage, 1669,
     /* 48439 */       GIR_EraseRootFromParent_Done,
     /* 48440 */     // Label 1241: @48440
     /* 48440 */     GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(48472), // Rule ID 1670 //
     /* 48445 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48448 */       // MIs[0] Operand 1
     /* 48448 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 48453 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48457 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48461 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
     /* 48461 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 48464 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 48466 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 48468 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 48470 */       GIR_RootConstrainSelectedInstOperands,
     /* 48471 */       // GIR_Coverage, 1670,
     /* 48471 */       GIR_EraseRootFromParent_Done,
     /* 48472 */     // Label 1242: @48472
     /* 48472 */     GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(48504), // Rule ID 1671 //
     /* 48477 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48480 */       // MIs[0] Operand 1
     /* 48480 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 48485 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48489 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48493 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs)
     /* 48493 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 48496 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 48498 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 48500 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 48502 */       GIR_RootConstrainSelectedInstOperands,
     /* 48503 */       // GIR_Coverage, 1671,
     /* 48503 */       GIR_EraseRootFromParent_Done,
     /* 48504 */     // Label 1243: @48504
     /* 48504 */     GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(48560), // Rule ID 1672 //
     /* 48509 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48512 */       // MIs[0] Operand 1
     /* 48512 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 48517 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48521 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48525 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
     /* 48525 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48528 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 48532 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48537 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48541 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48545 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48547 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48550 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48552 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48555 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48558 */       GIR_RootConstrainSelectedInstOperands,
     /* 48559 */       // GIR_Coverage, 1672,
     /* 48559 */       GIR_EraseRootFromParent_Done,
     /* 48560 */     // Label 1244: @48560
     /* 48560 */     GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(48616), // Rule ID 1673 //
     /* 48565 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips),
     /* 48568 */       // MIs[0] Operand 1
     /* 48568 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 48573 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48577 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 48581 */       // (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi:{ *:[i32] } (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), 1:{ *:[i32] })
     /* 48581 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48584 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 48588 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48593 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48597 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48601 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48603 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi),
     /* 48606 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 48608 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48611 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48614 */       GIR_RootConstrainSelectedInstOperands,
     /* 48615 */       // GIR_Coverage, 1673,
     /* 48615 */       GIR_EraseRootFromParent_Done,
     /* 48616 */     // Label 1245: @48616
     /* 48616 */     GIM_Reject,
     /* 48617 */   // Label 1237: @48617
     /* 48617 */   GIM_Reject,
     /* 48618 */   // Label 1225: @48618
     /* 48618 */   GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(49654),
     /* 48623 */     GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 48626 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 48629 */     GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(48689), // Rule ID 2013 //
     /* 48634 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48637 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48641 */       // MIs[0] Operand 1
     /* 48641 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 48646 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48650 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48654 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SltiuCCRxImmX16:{ *:[i32] } (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 48654 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48657 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 48661 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48666 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48670 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48674 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48676 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltiuCCRxImmX16),
     /* 48679 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 48681 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48684 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 48687 */       GIR_RootConstrainSelectedInstOperands,
     /* 48688 */       // GIR_Coverage, 2013,
     /* 48688 */       GIR_EraseRootFromParent_Done,
     /* 48689 */     // Label 1247: @48689
     /* 48689 */     GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(48766), // Rule ID 2015 //
     /* 48694 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48697 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48701 */       // MIs[0] Operand 1
     /* 48701 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 48706 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48710 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48714 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
     /* 48714 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 48717 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
     /* 48721 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48726 */       GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 48729 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 48731 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48734 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
     /* 48738 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48743 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48747 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48751 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48753 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 48756 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
     /* 48758 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48761 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 48764 */       GIR_RootConstrainSelectedInstOperands,
     /* 48765 */       // GIR_Coverage, 2015,
     /* 48765 */       GIR_EraseRootFromParent_Done,
     /* 48766 */     // Label 1248: @48766
     /* 48766 */     GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(48802), // Rule ID 2017 //
     /* 48771 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48774 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48778 */       // MIs[0] Operand 1
     /* 48778 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 48783 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48787 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48791 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
     /* 48791 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
     /* 48794 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 48796 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 48798 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 48800 */       GIR_RootConstrainSelectedInstOperands,
     /* 48801 */       // GIR_Coverage, 2017,
     /* 48801 */       GIR_EraseRootFromParent_Done,
     /* 48802 */     // Label 1249: @48802
     /* 48802 */     GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(48879), // Rule ID 2018 //
     /* 48807 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48810 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48814 */       // MIs[0] Operand 1
     /* 48814 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 48819 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48823 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48827 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImm16:{ *:[i32] } 1:{ *:[i32] }))
     /* 48827 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 48830 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImm16),
     /* 48834 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48839 */       GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 48842 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 48844 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48847 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
     /* 48851 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48856 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48860 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48864 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48866 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 48869 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
     /* 48871 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48874 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 48877 */       GIR_RootConstrainSelectedInstOperands,
     /* 48878 */       // GIR_Coverage, 2018,
     /* 48878 */       GIR_EraseRootFromParent_Done,
     /* 48879 */     // Label 1250: @48879
     /* 48879 */     GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(48915), // Rule ID 2019 //
     /* 48884 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48887 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48891 */       // MIs[0] Operand 1
     /* 48891 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
     /* 48896 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48900 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48904 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETLT:{ *:[Other] })  =>  (SltCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
     /* 48904 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltCCRxRy16),
     /* 48907 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 48909 */       GIR_RootToRootCopy, /*OpIdx*/2, // rx
     /* 48911 */       GIR_RootToRootCopy, /*OpIdx*/3, // ry
     /* 48913 */       GIR_RootConstrainSelectedInstOperands,
     /* 48914 */       // GIR_Coverage, 2019,
     /* 48914 */       GIR_EraseRootFromParent_Done,
     /* 48915 */     // Label 1251: @48915
     /* 48915 */     GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(48992), // Rule ID 2021 //
     /* 48920 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 48923 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48927 */       // MIs[0] Operand 1
     /* 48927 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 48932 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48936 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 48940 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } (LiRxImmX16:{ *:[i32] } 0:{ *:[i32] }), (XorRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs))
     /* 48940 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 48943 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 48947 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48952 */       GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 48956 */       GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 48960 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 48962 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 48965 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
     /* 48969 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 48974 */       GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
     /* 48977 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 48979 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
     /* 48982 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 48984 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 48987 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 48990 */       GIR_RootConstrainSelectedInstOperands,
     /* 48991 */       // GIR_Coverage, 2021,
     /* 48991 */       GIR_EraseRootFromParent_Done,
     /* 48992 */     // Label 1252: @48992
     /* 48992 */     GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(49069), // Rule ID 2022 //
     /* 48997 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 49000 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49004 */       // MIs[0] Operand 1
     /* 49004 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 49009 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49013 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49017 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
     /* 49017 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 49020 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
     /* 49024 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49029 */       GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 49032 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 49034 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49037 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
     /* 49041 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49046 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49050 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49054 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49056 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 49059 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
     /* 49061 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49064 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 49067 */       GIR_RootConstrainSelectedInstOperands,
     /* 49068 */       // GIR_Coverage, 2022,
     /* 49068 */       GIR_EraseRootFromParent_Done,
     /* 49069 */     // Label 1253: @49069
     /* 49069 */     GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(49105), // Rule ID 2023 //
     /* 49074 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 49077 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49081 */       // MIs[0] Operand 1
     /* 49081 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 49086 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49090 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49094 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs)
     /* 49094 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
     /* 49097 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 49099 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 49101 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 49103 */       GIR_RootConstrainSelectedInstOperands,
     /* 49104 */       // GIR_Coverage, 2023,
     /* 49104 */       GIR_EraseRootFromParent_Done,
     /* 49105 */     // Label 1254: @49105
     /* 49105 */     GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(49182), // Rule ID 2024 //
     /* 49110 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 49113 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49117 */       // MIs[0] Operand 1
     /* 49117 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 49122 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49126 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49130 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$lhs, CPU16Regs:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XorRxRxRy16:{ *:[i32] } (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rhs, CPU16Regs:{ *:[i32] }:$lhs), (LiRxImmX16:{ *:[i32] } 1:{ *:[i32] }))
     /* 49130 */       GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 49133 */       GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::LiRxImmX16),
     /* 49137 */       GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49142 */       GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
     /* 49145 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 49147 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49150 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
     /* 49154 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49159 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49163 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49167 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49169 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XorRxRxRy16),
     /* 49172 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rz]
     /* 49174 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49177 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 49180 */       GIR_RootConstrainSelectedInstOperands,
     /* 49181 */       // GIR_Coverage, 2024,
     /* 49181 */       GIR_EraseRootFromParent_Done,
     /* 49182 */     // Label 1255: @49182
     /* 49182 */     GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(49218), // Rule ID 2025 //
     /* 49187 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 49190 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49194 */       // MIs[0] Operand 1
     /* 49194 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
     /* 49199 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49203 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 49207 */       // (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry, SETULT:{ *:[Other] })  =>  (SltuCCRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$rx, CPU16Regs:{ *:[i32] }:$ry)
     /* 49207 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SltuCCRxRy16),
     /* 49210 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[cc]
     /* 49212 */       GIR_RootToRootCopy, /*OpIdx*/2, // rx
     /* 49214 */       GIR_RootToRootCopy, /*OpIdx*/3, // ry
     /* 49216 */       GIR_RootConstrainSelectedInstOperands,
     /* 49217 */       // GIR_Coverage, 2025,
     /* 49217 */       GIR_EraseRootFromParent_Done,
     /* 49218 */     // Label 1256: @49218
     /* 49218 */     GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(49278), // Rule ID 2337 //
     /* 49223 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49226 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49230 */       // MIs[0] Operand 1
     /* 49230 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 49235 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49239 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49243 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] })  =>  (SLTiu_MM:{ *:[i32] } (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 49243 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49246 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 49250 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49255 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49259 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49263 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49265 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTiu_MM),
     /* 49268 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 49270 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49273 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 49276 */       GIR_RootConstrainSelectedInstOperands,
     /* 49277 */       // GIR_Coverage, 2337,
     /* 49277 */       GIR_EraseRootFromParent_Done,
     /* 49278 */     // Label 1257: @49278
     /* 49278 */     GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(49341), // Rule ID 2338 //
     /* 49283 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49286 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49290 */       // MIs[0] Operand 1
     /* 49290 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 49295 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49299 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49303 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } ZERO:{ *:[i32] }, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs))
     /* 49303 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49306 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 49310 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49315 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49319 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49323 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49325 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 49328 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 49330 */       GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(Mips::ZERO), /*AddRegisterRegFlags*/GIMT_Encode2(0),
     /* 49336 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49339 */       GIR_RootConstrainSelectedInstOperands,
     /* 49340 */       // GIR_Coverage, 2338,
     /* 49340 */       GIR_EraseRootFromParent_Done,
     /* 49341 */     // Label 1258: @49341
     /* 49341 */     GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(49401), // Rule ID 2339 //
     /* 49346 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49349 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49353 */       // MIs[0] Operand 1
     /* 49353 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 49358 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49362 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49366 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
     /* 49366 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49369 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 49373 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49378 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49382 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49386 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49388 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
     /* 49391 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 49393 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49396 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 49399 */       GIR_RootConstrainSelectedInstOperands,
     /* 49400 */       // GIR_Coverage, 2339,
     /* 49400 */       GIR_EraseRootFromParent_Done,
     /* 49401 */     // Label 1259: @49401
     /* 49401 */     GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(49461), // Rule ID 2340 //
     /* 49406 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49409 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49413 */       // MIs[0] Operand 1
     /* 49413 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 49418 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49422 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49426 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), 1:{ *:[i32] })
     /* 49426 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49429 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 49433 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49438 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49442 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49446 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49448 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
     /* 49451 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 49453 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49456 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 49459 */       GIR_RootConstrainSelectedInstOperands,
     /* 49460 */       // GIR_Coverage, 2340,
     /* 49460 */       GIR_EraseRootFromParent_Done,
     /* 49461 */     // Label 1260: @49461
     /* 49461 */     GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(49497), // Rule ID 2341 //
     /* 49466 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49469 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49473 */       // MIs[0] Operand 1
     /* 49473 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 49478 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49482 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49486 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGT:{ *:[Other] })  =>  (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
     /* 49486 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 49489 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 49491 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 49493 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 49495 */       GIR_RootConstrainSelectedInstOperands,
     /* 49496 */       // GIR_Coverage, 2341,
     /* 49496 */       GIR_EraseRootFromParent_Done,
     /* 49497 */     // Label 1261: @49497
     /* 49497 */     GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(49533), // Rule ID 2342 //
     /* 49502 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49505 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49509 */       // MIs[0] Operand 1
     /* 49509 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 49514 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49518 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49522 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGT:{ *:[Other] })  =>  (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs)
     /* 49522 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 49525 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 49527 */       GIR_RootToRootCopy, /*OpIdx*/3, // rhs
     /* 49529 */       GIR_RootToRootCopy, /*OpIdx*/2, // lhs
     /* 49531 */       GIR_RootConstrainSelectedInstOperands,
     /* 49532 */       // GIR_Coverage, 2342,
     /* 49532 */       GIR_EraseRootFromParent_Done,
     /* 49533 */     // Label 1262: @49533
     /* 49533 */     GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(49593), // Rule ID 2343 //
     /* 49538 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49541 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49545 */       // MIs[0] Operand 1
     /* 49545 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 49550 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49554 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49558 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 49558 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49561 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 49565 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49570 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49574 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49578 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49580 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
     /* 49583 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 49585 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49588 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 49591 */       GIR_RootConstrainSelectedInstOperands,
     /* 49592 */       // GIR_Coverage, 2343,
     /* 49592 */       GIR_EraseRootFromParent_Done,
     /* 49593 */     // Label 1263: @49593
     /* 49593 */     GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(49653), // Rule ID 2344 //
     /* 49598 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 49601 */       GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49605 */       // MIs[0] Operand 1
     /* 49605 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 49610 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49614 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 49618 */       // (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] })  =>  (XORi_MM:{ *:[i32] } (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), 1:{ *:[i32] })
     /* 49618 */       GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 49621 */       GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 49625 */       GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 49630 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // lhs
     /* 49634 */       GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rhs
     /* 49638 */       GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 49640 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::XORi_MM),
     /* 49643 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rt]
     /* 49645 */       GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 49648 */       GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
     /* 49651 */       GIR_RootConstrainSelectedInstOperands,
     /* 49652 */       // GIR_Coverage, 2344,
     /* 49652 */       GIR_EraseRootFromParent_Done,
     /* 49653 */     // Label 1264: @49653
     /* 49653 */     GIM_Reject,
     /* 49654 */   // Label 1246: @49654
     /* 49654 */   GIM_Reject,
     /* 49655 */ // Label 1200: @49655
     /* 49655 */ GIM_Reject,
     /* 49656 */ // Label 42: @49656
     /* 49656 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(50655),
     /* 49661 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 49664 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(50159),
     /* 49675 */   /*GILLT_s32*//*Label 1266*/ GIMT_Encode4(49683),
     /* 49679 */   /*GILLT_s64*//*Label 1267*/ GIMT_Encode4(49921),
     /* 49683 */   // Label 1266: @49683
     /* 49683 */   GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(49920),
     /* 49688 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 49691 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
     /* 49695 */     GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(49727), // Rule ID 387 //
     /* 49700 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49703 */       // MIs[0] Operand 1
     /* 49703 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
     /* 49708 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49712 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49716 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49716 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S),
     /* 49719 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49721 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49723 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49725 */       GIR_RootConstrainSelectedInstOperands,
     /* 49726 */       // GIR_Coverage, 387,
     /* 49726 */       GIR_EraseRootFromParent_Done,
     /* 49727 */     // Label 1270: @49727
     /* 49727 */     GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(49759), // Rule ID 388 //
     /* 49732 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49735 */       // MIs[0] Operand 1
     /* 49735 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
     /* 49740 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49744 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49748 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49748 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S),
     /* 49751 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49753 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49755 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49757 */       GIR_RootConstrainSelectedInstOperands,
     /* 49758 */       // GIR_Coverage, 388,
     /* 49758 */       GIR_EraseRootFromParent_Done,
     /* 49759 */     // Label 1271: @49759
     /* 49759 */     GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(49791), // Rule ID 389 //
     /* 49764 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49767 */       // MIs[0] Operand 1
     /* 49767 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
     /* 49772 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49776 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49780 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49780 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S),
     /* 49783 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49785 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49787 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49789 */       GIR_RootConstrainSelectedInstOperands,
     /* 49790 */       // GIR_Coverage, 389,
     /* 49790 */       GIR_EraseRootFromParent_Done,
     /* 49791 */     // Label 1272: @49791
     /* 49791 */     GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(49823), // Rule ID 390 //
     /* 49796 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49799 */       // MIs[0] Operand 1
     /* 49799 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
     /* 49804 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49808 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49812 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49812 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S),
     /* 49815 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49817 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49819 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49821 */       GIR_RootConstrainSelectedInstOperands,
     /* 49822 */       // GIR_Coverage, 390,
     /* 49822 */       GIR_EraseRootFromParent_Done,
     /* 49823 */     // Label 1273: @49823
     /* 49823 */     GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(49855), // Rule ID 391 //
     /* 49828 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49831 */       // MIs[0] Operand 1
     /* 49831 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
     /* 49836 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49840 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49844 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49844 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S),
     /* 49847 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49849 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49851 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49853 */       GIR_RootConstrainSelectedInstOperands,
     /* 49854 */       // GIR_Coverage, 391,
     /* 49854 */       GIR_EraseRootFromParent_Done,
     /* 49855 */     // Label 1274: @49855
     /* 49855 */     GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(49887), // Rule ID 392 //
     /* 49860 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49863 */       // MIs[0] Operand 1
     /* 49863 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
     /* 49868 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49872 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49876 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49876 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S),
     /* 49879 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49881 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49883 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49885 */       GIR_RootConstrainSelectedInstOperands,
     /* 49886 */       // GIR_Coverage, 392,
     /* 49886 */       GIR_EraseRootFromParent_Done,
     /* 49887 */     // Label 1275: @49887
     /* 49887 */     GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(49919), // Rule ID 393 //
     /* 49892 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49895 */       // MIs[0] Operand 1
     /* 49895 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
     /* 49900 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49904 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 49908 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 49908 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S),
     /* 49911 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49913 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49915 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49917 */       GIR_RootConstrainSelectedInstOperands,
     /* 49918 */       // GIR_Coverage, 393,
     /* 49918 */       GIR_EraseRootFromParent_Done,
     /* 49919 */     // Label 1276: @49919
     /* 49919 */     GIM_Reject,
     /* 49920 */   // Label 1269: @49920
     /* 49920 */   GIM_Reject,
     /* 49921 */   // Label 1267: @49921
     /* 49921 */   GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(50158),
     /* 49926 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 49929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
     /* 49933 */     GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(49965), // Rule ID 394 //
     /* 49938 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49941 */       // MIs[0] Operand 1
     /* 49941 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
     /* 49946 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 49950 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 49954 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 49954 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D),
     /* 49957 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49959 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49961 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49963 */       GIR_RootConstrainSelectedInstOperands,
     /* 49964 */       // GIR_Coverage, 394,
     /* 49964 */       GIR_EraseRootFromParent_Done,
     /* 49965 */     // Label 1278: @49965
     /* 49965 */     GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(49997), // Rule ID 395 //
     /* 49970 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 49973 */       // MIs[0] Operand 1
     /* 49973 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
     /* 49978 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 49982 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 49986 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 49986 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D),
     /* 49989 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 49991 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 49993 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 49995 */       GIR_RootConstrainSelectedInstOperands,
     /* 49996 */       // GIR_Coverage, 395,
     /* 49996 */       GIR_EraseRootFromParent_Done,
     /* 49997 */     // Label 1279: @49997
     /* 49997 */     GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(50029), // Rule ID 396 //
     /* 50002 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 50005 */       // MIs[0] Operand 1
     /* 50005 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
     /* 50010 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50014 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50018 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50018 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D),
     /* 50021 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50023 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50025 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50027 */       GIR_RootConstrainSelectedInstOperands,
     /* 50028 */       // GIR_Coverage, 396,
     /* 50028 */       GIR_EraseRootFromParent_Done,
     /* 50029 */     // Label 1280: @50029
     /* 50029 */     GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(50061), // Rule ID 397 //
     /* 50034 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 50037 */       // MIs[0] Operand 1
     /* 50037 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
     /* 50042 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50046 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50050 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50050 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D),
     /* 50053 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50055 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50057 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50059 */       GIR_RootConstrainSelectedInstOperands,
     /* 50060 */       // GIR_Coverage, 397,
     /* 50060 */       GIR_EraseRootFromParent_Done,
     /* 50061 */     // Label 1281: @50061
     /* 50061 */     GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(50093), // Rule ID 398 //
     /* 50066 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 50069 */       // MIs[0] Operand 1
     /* 50069 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
     /* 50074 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50078 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50082 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50082 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D),
     /* 50085 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50087 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50089 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50091 */       GIR_RootConstrainSelectedInstOperands,
     /* 50092 */       // GIR_Coverage, 398,
     /* 50092 */       GIR_EraseRootFromParent_Done,
     /* 50093 */     // Label 1282: @50093
     /* 50093 */     GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(50125), // Rule ID 399 //
     /* 50098 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 50101 */       // MIs[0] Operand 1
     /* 50101 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
     /* 50106 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50110 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50114 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50114 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D),
     /* 50117 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50119 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50121 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50123 */       GIR_RootConstrainSelectedInstOperands,
     /* 50124 */       // GIR_Coverage, 399,
     /* 50124 */       GIR_EraseRootFromParent_Done,
     /* 50125 */     // Label 1283: @50125
     /* 50125 */     GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(50157), // Rule ID 400 //
     /* 50130 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 50133 */       // MIs[0] Operand 1
     /* 50133 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
     /* 50138 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50142 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50146 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50146 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D),
     /* 50149 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50151 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50153 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50155 */       GIR_RootConstrainSelectedInstOperands,
     /* 50156 */       // GIR_Coverage, 400,
     /* 50156 */       GIR_EraseRootFromParent_Done,
     /* 50157 */     // Label 1284: @50157
     /* 50157 */     GIM_Reject,
     /* 50158 */   // Label 1277: @50158
     /* 50158 */   GIM_Reject,
     /* 50159 */   // Label 1268: @50159
     /* 50159 */   GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1287*/ GIMT_Encode4(50654),
     /* 50170 */   /*GILLT_s32*//*Label 1285*/ GIMT_Encode4(50178),
     /* 50174 */   /*GILLT_s64*//*Label 1286*/ GIMT_Encode4(50416),
     /* 50178 */   // Label 1285: @50178
     /* 50178 */   GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(50415),
     /* 50183 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 50186 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
     /* 50190 */     GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(50222), // Rule ID 1268 //
     /* 50195 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50198 */       // MIs[0] Operand 1
     /* 50198 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
     /* 50203 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50207 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50211 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50211 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_S_MMR6),
     /* 50214 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50216 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50218 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50220 */       GIR_RootConstrainSelectedInstOperands,
     /* 50221 */       // GIR_Coverage, 1268,
     /* 50221 */       GIR_EraseRootFromParent_Done,
     /* 50222 */     // Label 1289: @50222
     /* 50222 */     GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(50254), // Rule ID 1269 //
     /* 50227 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50230 */       // MIs[0] Operand 1
     /* 50230 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
     /* 50235 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50239 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50243 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50243 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_S_MMR6),
     /* 50246 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50248 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50250 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50252 */       GIR_RootConstrainSelectedInstOperands,
     /* 50253 */       // GIR_Coverage, 1269,
     /* 50253 */       GIR_EraseRootFromParent_Done,
     /* 50254 */     // Label 1290: @50254
     /* 50254 */     GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(50286), // Rule ID 1270 //
     /* 50259 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50262 */       // MIs[0] Operand 1
     /* 50262 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
     /* 50267 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50271 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50275 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50275 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_S_MMR6),
     /* 50278 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50280 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50282 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50284 */       GIR_RootConstrainSelectedInstOperands,
     /* 50285 */       // GIR_Coverage, 1270,
     /* 50285 */       GIR_EraseRootFromParent_Done,
     /* 50286 */     // Label 1291: @50286
     /* 50286 */     GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(50318), // Rule ID 1271 //
     /* 50291 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50294 */       // MIs[0] Operand 1
     /* 50294 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
     /* 50299 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50303 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50307 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50307 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_S_MMR6),
     /* 50310 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50312 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50314 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50316 */       GIR_RootConstrainSelectedInstOperands,
     /* 50317 */       // GIR_Coverage, 1271,
     /* 50317 */       GIR_EraseRootFromParent_Done,
     /* 50318 */     // Label 1292: @50318
     /* 50318 */     GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(50350), // Rule ID 1272 //
     /* 50323 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50326 */       // MIs[0] Operand 1
     /* 50326 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
     /* 50331 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50335 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50339 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50339 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_S_MMR6),
     /* 50342 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50344 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50346 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50348 */       GIR_RootConstrainSelectedInstOperands,
     /* 50349 */       // GIR_Coverage, 1272,
     /* 50349 */       GIR_EraseRootFromParent_Done,
     /* 50350 */     // Label 1293: @50350
     /* 50350 */     GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(50382), // Rule ID 1273 //
     /* 50355 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50358 */       // MIs[0] Operand 1
     /* 50358 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
     /* 50363 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50367 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50371 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50371 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_S_MMR6),
     /* 50374 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50376 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50378 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50380 */       GIR_RootConstrainSelectedInstOperands,
     /* 50381 */       // GIR_Coverage, 1273,
     /* 50381 */       GIR_EraseRootFromParent_Done,
     /* 50382 */     // Label 1294: @50382
     /* 50382 */     GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(50414), // Rule ID 1274 //
     /* 50387 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50390 */       // MIs[0] Operand 1
     /* 50390 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
     /* 50395 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50399 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 50403 */       // (setcc:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_S_MMR6:{ *:[i32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 50403 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_S_MMR6),
     /* 50406 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50408 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50410 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50412 */       GIR_RootConstrainSelectedInstOperands,
     /* 50413 */       // GIR_Coverage, 1274,
     /* 50413 */       GIR_EraseRootFromParent_Done,
     /* 50414 */     // Label 1295: @50414
     /* 50414 */     GIM_Reject,
     /* 50415 */   // Label 1288: @50415
     /* 50415 */   GIM_Reject,
     /* 50416 */   // Label 1286: @50416
     /* 50416 */   GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(50653),
     /* 50421 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 50424 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
     /* 50428 */     GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(50460), // Rule ID 1275 //
     /* 50433 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50436 */       // MIs[0] Operand 1
     /* 50436 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
     /* 50441 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50445 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50449 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUO:{ *:[Other] })  =>  (CMP_UN_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50449 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UN_D_MMR6),
     /* 50452 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50454 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50456 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50458 */       GIR_RootConstrainSelectedInstOperands,
     /* 50459 */       // GIR_Coverage, 1275,
     /* 50459 */       GIR_EraseRootFromParent_Done,
     /* 50460 */     // Label 1297: @50460
     /* 50460 */     GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(50492), // Rule ID 1276 //
     /* 50465 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50468 */       // MIs[0] Operand 1
     /* 50468 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
     /* 50473 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50477 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50481 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOEQ:{ *:[Other] })  =>  (CMP_EQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50481 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_EQ_D_MMR6),
     /* 50484 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50486 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50488 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50490 */       GIR_RootConstrainSelectedInstOperands,
     /* 50491 */       // GIR_Coverage, 1276,
     /* 50491 */       GIR_EraseRootFromParent_Done,
     /* 50492 */     // Label 1298: @50492
     /* 50492 */     GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(50524), // Rule ID 1277 //
     /* 50497 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50500 */       // MIs[0] Operand 1
     /* 50500 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
     /* 50505 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50509 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50513 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETUEQ:{ *:[Other] })  =>  (CMP_UEQ_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50513 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_UEQ_D_MMR6),
     /* 50516 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50518 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50520 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50522 */       GIR_RootConstrainSelectedInstOperands,
     /* 50523 */       // GIR_Coverage, 1277,
     /* 50523 */       GIR_EraseRootFromParent_Done,
     /* 50524 */     // Label 1299: @50524
     /* 50524 */     GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(50556), // Rule ID 1278 //
     /* 50529 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50532 */       // MIs[0] Operand 1
     /* 50532 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
     /* 50537 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50541 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50545 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLT:{ *:[Other] })  =>  (CMP_LT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50545 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LT_D_MMR6),
     /* 50548 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50550 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50552 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50554 */       GIR_RootConstrainSelectedInstOperands,
     /* 50555 */       // GIR_Coverage, 1278,
     /* 50555 */       GIR_EraseRootFromParent_Done,
     /* 50556 */     // Label 1300: @50556
     /* 50556 */     GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(50588), // Rule ID 1279 //
     /* 50561 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50564 */       // MIs[0] Operand 1
     /* 50564 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
     /* 50569 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50573 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50577 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULT:{ *:[Other] })  =>  (CMP_ULT_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50577 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULT_D_MMR6),
     /* 50580 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50582 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50584 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50586 */       GIR_RootConstrainSelectedInstOperands,
     /* 50587 */       // GIR_Coverage, 1279,
     /* 50587 */       GIR_EraseRootFromParent_Done,
     /* 50588 */     // Label 1301: @50588
     /* 50588 */     GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(50620), // Rule ID 1280 //
     /* 50593 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50596 */       // MIs[0] Operand 1
     /* 50596 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
     /* 50601 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50605 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50609 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETOLE:{ *:[Other] })  =>  (CMP_LE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50609 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_LE_D_MMR6),
     /* 50612 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50614 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50616 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50618 */       GIR_RootConstrainSelectedInstOperands,
     /* 50619 */       // GIR_Coverage, 1280,
     /* 50619 */       GIR_EraseRootFromParent_Done,
     /* 50620 */     // Label 1302: @50620
     /* 50620 */     GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(50652), // Rule ID 1281 //
     /* 50625 */       GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 50628 */       // MIs[0] Operand 1
     /* 50628 */       GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
     /* 50633 */       GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50637 */       GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 50641 */       // (setcc:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft, SETULE:{ *:[Other] })  =>  (CMP_ULE_D_MMR6:{ *:[i32] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 50641 */       GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CMP_ULE_D_MMR6),
     /* 50644 */       GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 50646 */       GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 50648 */       GIR_RootToRootCopy, /*OpIdx*/3, // ft
     /* 50650 */       GIR_RootConstrainSelectedInstOperands,
     /* 50651 */       // GIR_Coverage, 1281,
     /* 50651 */       GIR_EraseRootFromParent_Done,
     /* 50652 */     // Label 1303: @50652
     /* 50652 */     GIM_Reject,
     /* 50653 */   // Label 1296: @50653
     /* 50653 */   GIM_Reject,
     /* 50654 */   // Label 1287: @50654
     /* 50654 */   GIM_Reject,
     /* 50655 */ // Label 1265: @50655
     /* 50655 */ GIM_Reject,
     /* 50656 */ // Label 43: @50656
     /* 50656 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(62785),
     /* 50667 */ /*GILLT_s32*//*Label 1304*/ GIMT_Encode4(50699),
     /* 50671 */ /*GILLT_s64*//*Label 1305*/ GIMT_Encode4(57376), GIMT_Encode4(0),
     /* 50679 */ /*GILLT_v2s64*//*Label 1306*/ GIMT_Encode4(62495), GIMT_Encode4(0),
     /* 50687 */ /*GILLT_v4s32*//*Label 1307*/ GIMT_Encode4(62569),
     /* 50691 */ /*GILLT_v8s16*//*Label 1308*/ GIMT_Encode4(62643),
     /* 50695 */ /*GILLT_v16s8*//*Label 1309*/ GIMT_Encode4(62690),
     /* 50699 */ // Label 1304: @50699
     /* 50699 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(50775), // Rule ID 1746 //
     /* 50704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 50707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 50710 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 50713 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 50716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50720 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 50724 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 50728 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 50732 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 50736 */   // MIs[1] Operand 1
     /* 50736 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 50741 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50746 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 50750 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50754 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50758 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 50760 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 50760 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 50763 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 50765 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 50767 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 50771 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 50773 */   GIR_RootConstrainSelectedInstOperands,
     /* 50774 */   // GIR_Coverage, 1746,
     /* 50774 */   GIR_EraseRootFromParent_Done,
     /* 50775 */ // Label 1311: @50775
     /* 50775 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(50851), // Rule ID 1750 //
     /* 50780 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 50783 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 50786 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 50789 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 50792 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50796 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 50800 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 50804 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 50808 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 50812 */   // MIs[1] Operand 1
     /* 50812 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 50817 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50822 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 50826 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50830 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50834 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 50836 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 50836 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
     /* 50839 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 50841 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 50843 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 50847 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 50849 */   GIR_RootConstrainSelectedInstOperands,
     /* 50850 */   // GIR_Coverage, 1750,
     /* 50850 */   GIR_EraseRootFromParent_Done,
     /* 50851 */ // Label 1312: @50851
     /* 50851 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(50927), // Rule ID 1778 //
     /* 50856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 50859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 50862 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 50865 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 50868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50872 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 50876 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 50880 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 50884 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 50888 */   // MIs[1] Operand 1
     /* 50888 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 50893 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 50898 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 50902 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50906 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50910 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 50912 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 50912 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
     /* 50915 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 50917 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 50919 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 50923 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 50925 */   GIR_RootConstrainSelectedInstOperands,
     /* 50926 */   // GIR_Coverage, 1778,
     /* 50926 */   GIR_EraseRootFromParent_Done,
     /* 50927 */ // Label 1313: @50927
     /* 50927 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(51003), // Rule ID 1789 //
     /* 50932 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 50935 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 50938 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 50941 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 50944 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50948 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 50952 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 50956 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 50960 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 50964 */   // MIs[1] Operand 1
     /* 50964 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 50969 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 50974 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 50978 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50982 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 50986 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 50988 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 50988 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
     /* 50991 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 50993 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 50995 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 50999 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51001 */   GIR_RootConstrainSelectedInstOperands,
     /* 51002 */   // GIR_Coverage, 1789,
     /* 51002 */   GIR_EraseRootFromParent_Done,
     /* 51003 */ // Label 1314: @51003
     /* 51003 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(51079), // Rule ID 1802 //
     /* 51008 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 51011 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51014 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51017 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51020 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51024 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51028 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51032 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51036 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51040 */   // MIs[1] Operand 1
     /* 51040 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51045 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51050 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51054 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51058 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51062 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51064 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51064 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 51067 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51069 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51071 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51075 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51077 */   GIR_RootConstrainSelectedInstOperands,
     /* 51078 */   // GIR_Coverage, 1802,
     /* 51078 */   GIR_EraseRootFromParent_Done,
     /* 51079 */ // Label 1315: @51079
     /* 51079 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(51155), // Rule ID 1805 //
     /* 51084 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 51087 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51090 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51093 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51096 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51100 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51104 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51108 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51112 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51116 */   // MIs[1] Operand 1
     /* 51116 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51121 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51126 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51130 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51134 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51138 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51140 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51140 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
     /* 51143 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51145 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51147 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51151 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51153 */   GIR_RootConstrainSelectedInstOperands,
     /* 51154 */   // GIR_Coverage, 1805,
     /* 51154 */   GIR_EraseRootFromParent_Done,
     /* 51155 */ // Label 1316: @51155
     /* 51155 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(51231), // Rule ID 1815 //
     /* 51160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 51163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51166 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51169 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51176 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51180 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51184 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 51188 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 51192 */   // MIs[1] Operand 1
     /* 51192 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51197 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 51202 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51206 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51210 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51214 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51216 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51216 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
     /* 51219 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51221 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51223 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51227 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51229 */   GIR_RootConstrainSelectedInstOperands,
     /* 51230 */   // GIR_Coverage, 1815,
     /* 51230 */   GIR_EraseRootFromParent_Done,
     /* 51231 */ // Label 1317: @51231
     /* 51231 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(51307), // Rule ID 1818 //
     /* 51236 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 51239 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51242 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51245 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51248 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51252 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51256 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51260 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 51264 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 51268 */   // MIs[1] Operand 1
     /* 51268 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51273 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 51278 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51282 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51286 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51290 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51292 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51292 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
     /* 51295 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51297 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51299 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51303 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51305 */   GIR_RootConstrainSelectedInstOperands,
     /* 51306 */   // GIR_Coverage, 1818,
     /* 51306 */   GIR_EraseRootFromParent_Done,
     /* 51307 */ // Label 1318: @51307
     /* 51307 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(51383), // Rule ID 2007 //
     /* 51312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 51315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51318 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51321 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51328 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51332 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51336 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51340 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51344 */   // MIs[1] Operand 1
     /* 51344 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51349 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51354 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51358 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51362 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51366 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51368 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBeqZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
     /* 51368 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBeqZ),
     /* 51371 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 51373 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 51375 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 51377 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 51381 */   GIR_RootConstrainSelectedInstOperands,
     /* 51382 */   // GIR_Coverage, 2007,
     /* 51382 */   GIR_EraseRootFromParent_Done,
     /* 51383 */ // Label 1319: @51383
     /* 51383 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(51459), // Rule ID 2010 //
     /* 51388 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 51391 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51394 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51397 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51400 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51404 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51408 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51412 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51416 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51420 */   // MIs[1] Operand 1
     /* 51420 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51425 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51430 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51434 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51438 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 51442 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51444 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, 0:{ *:[i32] }, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
     /* 51444 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
     /* 51447 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 51449 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 51451 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 51453 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 51457 */   GIR_RootConstrainSelectedInstOperands,
     /* 51458 */   // GIR_Coverage, 2010,
     /* 51458 */   GIR_EraseRootFromParent_Done,
     /* 51459 */ // Label 1320: @51459
     /* 51459 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(51535), // Rule ID 2356 //
     /* 51464 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 51467 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51470 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51473 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51476 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51480 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51484 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51488 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51492 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51496 */   // MIs[1] Operand 1
     /* 51496 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51501 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51506 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51510 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51514 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51518 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51520 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 51520 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 51523 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 51525 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51527 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51531 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51533 */   GIR_RootConstrainSelectedInstOperands,
     /* 51534 */   // GIR_Coverage, 2356,
     /* 51534 */   GIR_EraseRootFromParent_Done,
     /* 51535 */ // Label 1321: @51535
     /* 51535 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(51611), // Rule ID 2360 //
     /* 51540 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
     /* 51543 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51546 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51549 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51552 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51556 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51560 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51564 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51568 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51572 */   // MIs[1] Operand 1
     /* 51572 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51577 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51582 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51586 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51590 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51594 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51596 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 51596 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 51599 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 51601 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51603 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51607 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51609 */   GIR_RootConstrainSelectedInstOperands,
     /* 51610 */   // GIR_Coverage, 2360,
     /* 51610 */   GIR_EraseRootFromParent_Done,
     /* 51611 */ // Label 1322: @51611
     /* 51611 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(51687), // Rule ID 2370 //
     /* 51616 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 51619 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51622 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51625 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51628 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51632 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51636 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51640 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51644 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51648 */   // MIs[1] Operand 1
     /* 51648 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51653 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51658 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51662 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51666 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51670 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51672 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 51672 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 51675 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 51677 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51679 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51683 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51685 */   GIR_RootConstrainSelectedInstOperands,
     /* 51686 */   // GIR_Coverage, 2370,
     /* 51686 */   GIR_EraseRootFromParent_Done,
     /* 51687 */ // Label 1323: @51687
     /* 51687 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(51763), // Rule ID 2374 //
     /* 51692 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 51695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51698 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51701 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51708 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51712 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51716 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51720 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51724 */   // MIs[1] Operand 1
     /* 51724 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51729 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51734 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51738 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51742 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51746 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51748 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$F)
     /* 51748 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 51751 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 51753 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51755 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51759 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51761 */   GIR_RootConstrainSelectedInstOperands,
     /* 51762 */   // GIR_Coverage, 2374,
     /* 51762 */   GIR_EraseRootFromParent_Done,
     /* 51763 */ // Label 1324: @51763
     /* 51763 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(51839), // Rule ID 2416 //
     /* 51768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 51771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51774 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51777 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51780 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51784 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51788 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51792 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51796 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51800 */   // MIs[1] Operand 1
     /* 51800 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 51805 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51810 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51814 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51818 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51822 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51824 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51824 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 51827 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51829 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51831 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51835 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51837 */   GIR_RootConstrainSelectedInstOperands,
     /* 51838 */   // GIR_Coverage, 2416,
     /* 51838 */   GIR_EraseRootFromParent_Done,
     /* 51839 */ // Label 1325: @51839
     /* 51839 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(51915), // Rule ID 2419 //
     /* 51844 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 51847 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51850 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51853 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51856 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51860 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51864 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51868 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51872 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51876 */   // MIs[1] Operand 1
     /* 51876 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 51881 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51886 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 51890 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51894 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 51898 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51900 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$lhs, FGR32:{ *:[f32] }:$F)
     /* 51900 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
     /* 51903 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 51905 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 51907 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51911 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 51913 */   GIR_RootConstrainSelectedInstOperands,
     /* 51914 */   // GIR_Coverage, 2419,
     /* 51914 */   GIR_EraseRootFromParent_Done,
     /* 51915 */ // Label 1326: @51915
     /* 51915 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(52013), // Rule ID 1737 //
     /* 51920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 51923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 51926 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 51929 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 51932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51936 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 51940 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 51944 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 51948 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 51952 */   // MIs[1] Operand 1
     /* 51952 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 51957 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51962 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51967 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51971 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 51975 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 51977 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 51977 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 51980 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 51984 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 51989 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 51993 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 51997 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 51999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52004 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52006 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52009 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52011 */   GIR_RootConstrainSelectedInstOperands,
     /* 52012 */   // GIR_Coverage, 1737,
     /* 52012 */   GIR_EraseRootFromParent_Done,
     /* 52013 */ // Label 1327: @52013
     /* 52013 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(52111), // Rule ID 1738 //
     /* 52018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52021 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52024 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52027 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52034 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52038 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52042 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 52046 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 52050 */   // MIs[1] Operand 1
     /* 52050 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 52055 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52060 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52065 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52069 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52073 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52075 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52075 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52078 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 52082 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52087 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52091 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52095 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52100 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52102 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52104 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52107 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52109 */   GIR_RootConstrainSelectedInstOperands,
     /* 52110 */   // GIR_Coverage, 1738,
     /* 52110 */   GIR_EraseRootFromParent_Done,
     /* 52111 */ // Label 1328: @52111
     /* 52111 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(52209), // Rule ID 1741 //
     /* 52116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52122 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52125 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52132 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52136 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52140 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 52144 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 52148 */   // MIs[1] Operand 1
     /* 52148 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 52153 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52158 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52163 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52167 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52171 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52173 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 52173 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52176 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 52180 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52185 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52189 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52193 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52200 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52202 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52205 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52207 */   GIR_RootConstrainSelectedInstOperands,
     /* 52208 */   // GIR_Coverage, 1741,
     /* 52208 */   GIR_EraseRootFromParent_Done,
     /* 52209 */ // Label 1329: @52209
     /* 52209 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(52307), // Rule ID 1742 //
     /* 52214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52217 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52220 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52223 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52230 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52234 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52238 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 52242 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 52246 */   // MIs[1] Operand 1
     /* 52246 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 52251 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52256 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52261 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52265 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52269 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52271 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 52271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 52278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52283 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52287 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52291 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52298 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52300 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52303 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52305 */   GIR_RootConstrainSelectedInstOperands,
     /* 52306 */   // GIR_Coverage, 1742,
     /* 52306 */   GIR_EraseRootFromParent_Done,
     /* 52307 */ // Label 1330: @52307
     /* 52307 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(52405), // Rule ID 1745 //
     /* 52312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52318 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52321 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52328 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52332 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52336 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 52340 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 52344 */   // MIs[1] Operand 1
     /* 52344 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 52349 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52354 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52359 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52363 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52367 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52369 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52369 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52372 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 52376 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52381 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52385 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52389 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52396 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52398 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52401 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52403 */   GIR_RootConstrainSelectedInstOperands,
     /* 52404 */   // GIR_Coverage, 1745,
     /* 52404 */   GIR_EraseRootFromParent_Done,
     /* 52405 */ // Label 1331: @52405
     /* 52405 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(52503), // Rule ID 1748 //
     /* 52410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52413 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52416 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52419 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52426 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52430 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52434 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 52438 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 52442 */   // MIs[1] Operand 1
     /* 52442 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 52447 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52452 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52457 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52461 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52465 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52467 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52467 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52470 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 52474 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52479 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52483 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52487 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
     /* 52492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52494 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52496 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52499 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52501 */   GIR_RootConstrainSelectedInstOperands,
     /* 52502 */   // GIR_Coverage, 1748,
     /* 52502 */   GIR_EraseRootFromParent_Done,
     /* 52503 */ // Label 1332: @52503
     /* 52503 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(52601), // Rule ID 1759 //
     /* 52508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52511 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52514 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52517 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52524 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52528 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52532 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 52536 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 52540 */   // MIs[1] Operand 1
     /* 52540 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 52545 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52550 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52555 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52559 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52563 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52565 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52565 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52568 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 52572 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52577 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52581 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52592 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52594 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52597 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52599 */   GIR_RootConstrainSelectedInstOperands,
     /* 52600 */   // GIR_Coverage, 1759,
     /* 52600 */   GIR_EraseRootFromParent_Done,
     /* 52601 */ // Label 1333: @52601
     /* 52601 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(52699), // Rule ID 1760 //
     /* 52606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52609 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52612 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52615 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52622 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52626 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52630 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 52634 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 52638 */   // MIs[1] Operand 1
     /* 52638 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 52643 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52648 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52653 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52657 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52661 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52663 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52663 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52666 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 52670 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52675 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52679 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52683 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52690 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52692 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52695 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52697 */   GIR_RootConstrainSelectedInstOperands,
     /* 52698 */   // GIR_Coverage, 1760,
     /* 52698 */   GIR_EraseRootFromParent_Done,
     /* 52699 */ // Label 1334: @52699
     /* 52699 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(52797), // Rule ID 1763 //
     /* 52704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52710 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52713 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52720 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52724 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52728 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 52732 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 52736 */   // MIs[1] Operand 1
     /* 52736 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 52741 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52746 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52751 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52755 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52759 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52761 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 52761 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52764 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 52768 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52773 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52777 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52781 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52786 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52788 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52790 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52793 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52795 */   GIR_RootConstrainSelectedInstOperands,
     /* 52796 */   // GIR_Coverage, 1763,
     /* 52796 */   GIR_EraseRootFromParent_Done,
     /* 52797 */ // Label 1335: @52797
     /* 52797 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(52895), // Rule ID 1764 //
     /* 52802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52805 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52808 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52811 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52818 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52822 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52826 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 52830 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 52834 */   // MIs[1] Operand 1
     /* 52834 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 52839 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52844 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52849 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52853 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52857 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52859 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 52859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 52862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 52866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52871 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52875 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52879 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I),
     /* 52884 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52886 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52888 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52891 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52893 */   GIR_RootConstrainSelectedInstOperands,
     /* 52894 */   // GIR_Coverage, 1764,
     /* 52894 */   GIR_EraseRootFromParent_Done,
     /* 52895 */ // Label 1336: @52895
     /* 52895 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(52993), // Rule ID 1777 //
     /* 52900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 52903 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 52906 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 52909 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 52912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52916 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 52920 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 52924 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 52928 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 52932 */   // MIs[1] Operand 1
     /* 52932 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 52937 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52942 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 52947 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52951 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 52955 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 52957 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 52957 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 52960 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 52964 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 52969 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 52973 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 52977 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 52979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I),
     /* 52982 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 52984 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 52986 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 52989 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 52991 */   GIR_RootConstrainSelectedInstOperands,
     /* 52992 */   // GIR_Coverage, 1777,
     /* 52992 */   GIR_EraseRootFromParent_Done,
     /* 52993 */ // Label 1337: @52993
     /* 52993 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(53091), // Rule ID 1787 //
     /* 52998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53001 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53004 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53007 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53014 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53018 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53022 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 53026 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 53030 */   // MIs[1] Operand 1
     /* 53030 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 53035 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53040 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53045 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53049 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53053 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53055 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 53055 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 53058 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 53062 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53067 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53071 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53075 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53077 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
     /* 53080 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 53082 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53084 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53087 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53089 */   GIR_RootConstrainSelectedInstOperands,
     /* 53090 */   // GIR_Coverage, 1787,
     /* 53090 */   GIR_EraseRootFromParent_Done,
     /* 53091 */ // Label 1338: @53091
     /* 53091 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(53189), // Rule ID 1793 //
     /* 53096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53099 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53102 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53105 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53112 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53116 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53120 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53124 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53128 */   // MIs[1] Operand 1
     /* 53128 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 53133 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53138 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53143 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53147 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53151 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53153 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53153 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53156 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 53160 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53165 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53169 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53173 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53178 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53180 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53182 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53185 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53187 */   GIR_RootConstrainSelectedInstOperands,
     /* 53188 */   // GIR_Coverage, 1793,
     /* 53188 */   GIR_EraseRootFromParent_Done,
     /* 53189 */ // Label 1339: @53189
     /* 53189 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(53287), // Rule ID 1794 //
     /* 53194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53197 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53200 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53203 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53210 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53214 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53218 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53222 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53226 */   // MIs[1] Operand 1
     /* 53226 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 53231 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53236 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53241 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53245 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53249 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53251 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53251 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53254 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 53258 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53263 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53267 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53271 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53276 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53278 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53280 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53283 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53285 */   GIR_RootConstrainSelectedInstOperands,
     /* 53286 */   // GIR_Coverage, 1794,
     /* 53286 */   GIR_EraseRootFromParent_Done,
     /* 53287 */ // Label 1340: @53287
     /* 53287 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(53385), // Rule ID 1797 //
     /* 53292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53298 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53301 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53316 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53320 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53324 */   // MIs[1] Operand 1
     /* 53324 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 53329 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53334 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53339 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53343 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53347 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53349 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 53349 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53352 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 53356 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53361 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53365 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53369 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53376 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53378 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53381 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53383 */   GIR_RootConstrainSelectedInstOperands,
     /* 53384 */   // GIR_Coverage, 1797,
     /* 53384 */   GIR_EraseRootFromParent_Done,
     /* 53385 */ // Label 1341: @53385
     /* 53385 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(53483), // Rule ID 1798 //
     /* 53390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53396 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53399 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53406 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53410 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53414 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53418 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53422 */   // MIs[1] Operand 1
     /* 53422 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 53427 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53432 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53437 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53441 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53445 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53447 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 53447 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53450 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 53454 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53459 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53463 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53467 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53474 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53476 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53479 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53481 */   GIR_RootConstrainSelectedInstOperands,
     /* 53482 */   // GIR_Coverage, 1798,
     /* 53482 */   GIR_EraseRootFromParent_Done,
     /* 53483 */ // Label 1342: @53483
     /* 53483 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(53581), // Rule ID 1801 //
     /* 53488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53491 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53494 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53497 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53504 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53508 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53512 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53516 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53520 */   // MIs[1] Operand 1
     /* 53520 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 53525 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53530 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53535 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53539 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53543 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53545 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53545 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53548 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 53552 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53557 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53561 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53565 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53572 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53574 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53577 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53579 */   GIR_RootConstrainSelectedInstOperands,
     /* 53580 */   // GIR_Coverage, 1801,
     /* 53580 */   GIR_EraseRootFromParent_Done,
     /* 53581 */ // Label 1343: @53581
     /* 53581 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(53679), // Rule ID 1803 //
     /* 53586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53589 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53592 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53595 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53602 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53606 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53610 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 53614 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 53618 */   // MIs[1] Operand 1
     /* 53618 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 53623 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53628 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 53633 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53637 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53641 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53643 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53643 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53646 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 53650 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53655 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53659 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53663 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
     /* 53668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53670 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53672 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53675 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53677 */   GIR_RootConstrainSelectedInstOperands,
     /* 53678 */   // GIR_Coverage, 1803,
     /* 53678 */   GIR_EraseRootFromParent_Done,
     /* 53679 */ // Label 1344: @53679
     /* 53679 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(53777), // Rule ID 1806 //
     /* 53684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53687 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53690 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53693 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53700 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53704 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53708 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 53712 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 53716 */   // MIs[1] Operand 1
     /* 53716 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 53721 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53726 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53731 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53735 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53739 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53741 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53741 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53744 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 53748 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53753 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53757 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53761 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53763 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53766 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53768 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53770 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53773 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53775 */   GIR_RootConstrainSelectedInstOperands,
     /* 53776 */   // GIR_Coverage, 1806,
     /* 53776 */   GIR_EraseRootFromParent_Done,
     /* 53777 */ // Label 1345: @53777
     /* 53777 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(53875), // Rule ID 1807 //
     /* 53782 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53785 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53788 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53791 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53794 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53798 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53802 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53806 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 53810 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 53814 */   // MIs[1] Operand 1
     /* 53814 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 53819 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53824 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53829 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53833 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53837 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53839 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 53839 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53842 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 53846 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53851 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53855 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53859 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53861 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53864 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53866 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53868 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53871 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53873 */   GIR_RootConstrainSelectedInstOperands,
     /* 53874 */   // GIR_Coverage, 1807,
     /* 53874 */   GIR_EraseRootFromParent_Done,
     /* 53875 */ // Label 1346: @53875
     /* 53875 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(53973), // Rule ID 1810 //
     /* 53880 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53883 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53886 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53889 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53892 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53896 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53900 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 53904 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 53908 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 53912 */   // MIs[1] Operand 1
     /* 53912 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 53917 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53922 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 53927 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53931 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53935 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 53937 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 53937 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 53940 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 53944 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 53949 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 53953 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 53957 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 53959 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 53962 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 53964 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 53966 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 53969 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 53971 */   GIR_RootConstrainSelectedInstOperands,
     /* 53972 */   // GIR_Coverage, 1810,
     /* 53972 */   GIR_EraseRootFromParent_Done,
     /* 53973 */ // Label 1347: @53973
     /* 53973 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(54071), // Rule ID 1811 //
     /* 53978 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 53981 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 53984 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 53987 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 53990 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 53994 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 53998 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54002 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 54006 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 54010 */   // MIs[1] Operand 1
     /* 54010 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 54015 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54020 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54025 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54029 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54033 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54035 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 54035 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 54038 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 54042 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 54047 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 54051 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 54055 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 54057 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S),
     /* 54060 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 54062 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 54064 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 54067 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 54069 */   GIR_RootConstrainSelectedInstOperands,
     /* 54070 */   // GIR_Coverage, 1811,
     /* 54070 */   GIR_EraseRootFromParent_Done,
     /* 54071 */ // Label 1348: @54071
     /* 54071 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(54169), // Rule ID 1814 //
     /* 54076 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 54079 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54082 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54085 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54092 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54096 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54100 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 54104 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 54108 */   // MIs[1] Operand 1
     /* 54108 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 54113 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54118 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54123 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54127 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54131 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54133 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 54133 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 54136 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 54140 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 54145 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 54149 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 54153 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 54155 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_S),
     /* 54158 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 54160 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 54162 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 54165 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 54167 */   GIR_RootConstrainSelectedInstOperands,
     /* 54168 */   // GIR_Coverage, 1814,
     /* 54168 */   GIR_EraseRootFromParent_Done,
     /* 54169 */ // Label 1349: @54169
     /* 54169 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(54267), // Rule ID 1816 //
     /* 54174 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 54177 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54180 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54183 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54186 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54190 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54194 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54198 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 54202 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 54206 */   // MIs[1] Operand 1
     /* 54206 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 54211 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54216 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 54221 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54225 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 54229 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54231 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 54231 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 54234 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 54238 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 54243 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 54247 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 54251 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 54253 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
     /* 54256 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 54258 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 54260 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 54263 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 54265 */   GIR_RootConstrainSelectedInstOperands,
     /* 54266 */   // GIR_Coverage, 1816,
     /* 54266 */   GIR_EraseRootFromParent_Done,
     /* 54267 */ // Label 1350: @54267
     /* 54267 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(54348), // Rule ID 1999 //
     /* 54272 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54275 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54278 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54281 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54284 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54288 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54292 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54296 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54300 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54304 */   // MIs[1] Operand 1
     /* 54304 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 54309 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54314 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54319 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54323 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54327 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54329 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
     /* 54329 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
     /* 54332 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54334 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54336 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54338 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54342 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54346 */   GIR_RootConstrainSelectedInstOperands,
     /* 54347 */   // GIR_Coverage, 1999,
     /* 54347 */   GIR_EraseRootFromParent_Done,
     /* 54348 */ // Label 1351: @54348
     /* 54348 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(54429), // Rule ID 2000 //
     /* 54353 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54356 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54359 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54362 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54369 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54373 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54377 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54381 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54385 */   // MIs[1] Operand 1
     /* 54385 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
     /* 54390 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54395 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54400 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54404 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54408 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54410 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSlt),
     /* 54413 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54415 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54417 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54419 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54423 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54427 */   GIR_RootConstrainSelectedInstOperands,
     /* 54428 */   // GIR_Coverage, 2000,
     /* 54428 */   GIR_EraseRootFromParent_Done,
     /* 54429 */ // Label 1352: @54429
     /* 54429 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(54510), // Rule ID 2001 //
     /* 54434 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54437 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54440 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54443 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54446 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54450 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54454 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54458 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54462 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54466 */   // MIs[1] Operand 1
     /* 54466 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 54471 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54476 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54481 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54485 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54489 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54491 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b)
     /* 54491 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
     /* 54494 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54496 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54498 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54500 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54504 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54508 */   GIR_RootConstrainSelectedInstOperands,
     /* 54509 */   // GIR_Coverage, 2001,
     /* 54509 */   GIR_EraseRootFromParent_Done,
     /* 54510 */ // Label 1353: @54510
     /* 54510 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(54591), // Rule ID 2002 //
     /* 54515 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54518 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54521 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54524 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54527 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54531 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54535 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54539 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54543 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54547 */   // MIs[1] Operand 1
     /* 54547 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
     /* 54552 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54557 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54562 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54566 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54570 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54572 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETUGT:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54572 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZSltu),
     /* 54575 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54577 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54579 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54581 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54585 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54589 */   GIR_RootConstrainSelectedInstOperands,
     /* 54590 */   // GIR_Coverage, 2002,
     /* 54590 */   GIR_EraseRootFromParent_Done,
     /* 54591 */ // Label 1354: @54591
     /* 54591 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(54672), // Rule ID 2004 //
     /* 54596 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54599 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54602 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54605 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54608 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54612 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54616 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54620 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54624 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54628 */   // MIs[1] Operand 1
     /* 54628 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 54633 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54638 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54643 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54647 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54651 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54653 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETLE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSlt:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54653 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSlt),
     /* 54656 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54658 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54660 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54662 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54666 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54670 */   GIR_RootConstrainSelectedInstOperands,
     /* 54671 */   // GIR_Coverage, 2004,
     /* 54671 */   GIR_EraseRootFromParent_Done,
     /* 54672 */ // Label 1355: @54672
     /* 54672 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(54753), // Rule ID 2005 //
     /* 54677 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54680 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54683 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54686 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54689 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54693 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54697 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54701 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54705 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54709 */   // MIs[1] Operand 1
     /* 54709 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 54714 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54719 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54724 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54728 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54732 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54734 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETULE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZSltu:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54734 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZSltu),
     /* 54737 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54739 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54741 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54743 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54747 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54751 */   GIR_RootConstrainSelectedInstOperands,
     /* 54752 */   // GIR_Coverage, 2005,
     /* 54752 */   GIR_EraseRootFromParent_Done,
     /* 54753 */ // Label 1356: @54753
     /* 54753 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(54834), // Rule ID 2006 //
     /* 54758 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54764 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54767 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54770 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54774 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54778 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54782 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54786 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54790 */   // MIs[1] Operand 1
     /* 54790 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 54795 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54800 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54805 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54809 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54813 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54815 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETEQ:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBteqZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54815 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBteqZCmp),
     /* 54818 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54820 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54822 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54824 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54828 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54832 */   GIR_RootConstrainSelectedInstOperands,
     /* 54833 */   // GIR_Coverage, 2006,
     /* 54833 */   GIR_EraseRootFromParent_Done,
     /* 54834 */ // Label 1357: @54834
     /* 54834 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(54915), // Rule ID 2009 //
     /* 54839 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 54842 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54845 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54848 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54851 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54855 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54859 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54863 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54867 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54871 */   // MIs[1] Operand 1
     /* 54871 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 54876 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54881 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54886 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54890 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 54894 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54896 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$b, SETNE:{ *:[Other] }), CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelTBtneZCmp:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$b, CPU16Regs:{ *:[i32] }:$a)
     /* 54896 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelTBtneZCmp),
     /* 54899 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 54901 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 54903 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 54905 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // b
     /* 54909 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // a
     /* 54913 */   GIR_RootConstrainSelectedInstOperands,
     /* 54914 */   // GIR_Coverage, 2009,
     /* 54914 */   GIR_EraseRootFromParent_Done,
     /* 54915 */ // Label 1358: @54915
     /* 54915 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(55013), // Rule ID 2347 //
     /* 54920 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 54923 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 54926 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 54929 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 54932 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 54936 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 54940 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 54944 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 54948 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 54952 */   // MIs[1] Operand 1
     /* 54952 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 54957 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 54962 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 54967 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 54971 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 54975 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 54977 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 54977 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 54980 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 54984 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 54989 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 54993 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 54997 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 54999 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55002 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55004 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55006 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55009 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55011 */   GIR_RootConstrainSelectedInstOperands,
     /* 55012 */   // GIR_Coverage, 2347,
     /* 55012 */   GIR_EraseRootFromParent_Done,
     /* 55013 */ // Label 1359: @55013
     /* 55013 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(55111), // Rule ID 2348 //
     /* 55018 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55021 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55024 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55027 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55030 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55034 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55038 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55042 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55046 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55050 */   // MIs[1] Operand 1
     /* 55050 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 55055 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55060 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55065 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55069 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55073 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55075 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55075 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55078 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 55082 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55087 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55091 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55095 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55097 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55100 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55102 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55104 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55107 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55109 */   GIR_RootConstrainSelectedInstOperands,
     /* 55110 */   // GIR_Coverage, 2348,
     /* 55110 */   GIR_EraseRootFromParent_Done,
     /* 55111 */ // Label 1360: @55111
     /* 55111 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(55209), // Rule ID 2351 //
     /* 55116 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55119 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55122 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55125 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55128 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55132 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55136 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55140 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55144 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55148 */   // MIs[1] Operand 1
     /* 55148 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 55153 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55158 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55163 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55167 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55171 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55173 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 55173 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55176 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 55180 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55185 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55189 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55193 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55195 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55198 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55200 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55202 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55205 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55207 */   GIR_RootConstrainSelectedInstOperands,
     /* 55208 */   // GIR_Coverage, 2351,
     /* 55208 */   GIR_EraseRootFromParent_Done,
     /* 55209 */ // Label 1361: @55209
     /* 55209 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(55307), // Rule ID 2352 //
     /* 55214 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55217 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55220 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55223 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55226 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55230 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55234 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55238 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55242 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55246 */   // MIs[1] Operand 1
     /* 55246 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 55251 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55256 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55261 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55265 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55269 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55271 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 55271 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55274 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 55278 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55283 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55287 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55291 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55293 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55296 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55298 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55300 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55303 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55305 */   GIR_RootConstrainSelectedInstOperands,
     /* 55306 */   // GIR_Coverage, 2352,
     /* 55306 */   GIR_EraseRootFromParent_Done,
     /* 55307 */ // Label 1362: @55307
     /* 55307 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(55405), // Rule ID 2355 //
     /* 55312 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55315 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55318 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55321 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55324 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55328 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55332 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55336 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55340 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55344 */   // MIs[1] Operand 1
     /* 55344 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 55349 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55354 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55359 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55363 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55367 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55369 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55369 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55372 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 55376 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55381 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55385 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55389 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55391 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55394 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55396 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55398 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55401 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55403 */   GIR_RootConstrainSelectedInstOperands,
     /* 55404 */   // GIR_Coverage, 2355,
     /* 55404 */   GIR_EraseRootFromParent_Done,
     /* 55405 */ // Label 1363: @55405
     /* 55405 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(55503), // Rule ID 2358 //
     /* 55410 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
     /* 55413 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55416 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55419 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55422 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55426 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55430 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55434 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55438 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55442 */   // MIs[1] Operand 1
     /* 55442 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 55447 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55452 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55457 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55461 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55465 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55467 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55467 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55470 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 55474 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55479 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55483 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55487 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55489 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 55492 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55494 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55496 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55499 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55501 */   GIR_RootConstrainSelectedInstOperands,
     /* 55502 */   // GIR_Coverage, 2358,
     /* 55502 */   GIR_EraseRootFromParent_Done,
     /* 55503 */ // Label 1364: @55503
     /* 55503 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(55601), // Rule ID 2361 //
     /* 55508 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55511 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55514 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55517 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55520 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55524 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55528 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55532 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55536 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55540 */   // MIs[1] Operand 1
     /* 55540 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 55545 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55550 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55555 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55559 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55563 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55565 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55565 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55568 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 55572 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55577 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55581 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55585 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55587 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55590 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55592 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55594 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55597 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55599 */   GIR_RootConstrainSelectedInstOperands,
     /* 55600 */   // GIR_Coverage, 2361,
     /* 55600 */   GIR_EraseRootFromParent_Done,
     /* 55601 */ // Label 1365: @55601
     /* 55601 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(55699), // Rule ID 2362 //
     /* 55606 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55609 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55612 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55615 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55618 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55622 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55626 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55630 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55634 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55638 */   // MIs[1] Operand 1
     /* 55638 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 55643 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55648 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55653 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55657 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55661 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55663 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55663 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55666 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 55670 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55675 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55679 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55683 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55685 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55688 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55690 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55692 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55695 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55697 */   GIR_RootConstrainSelectedInstOperands,
     /* 55698 */   // GIR_Coverage, 2362,
     /* 55698 */   GIR_EraseRootFromParent_Done,
     /* 55699 */ // Label 1366: @55699
     /* 55699 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(55797), // Rule ID 2365 //
     /* 55704 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55707 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55710 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55713 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55716 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55720 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55724 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55728 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55732 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55736 */   // MIs[1] Operand 1
     /* 55736 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 55741 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55746 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55751 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55755 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55759 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55761 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 55761 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55764 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 55768 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55773 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55777 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55781 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55783 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55786 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55788 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55790 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55793 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55795 */   GIR_RootConstrainSelectedInstOperands,
     /* 55796 */   // GIR_Coverage, 2365,
     /* 55796 */   GIR_EraseRootFromParent_Done,
     /* 55797 */ // Label 1367: @55797
     /* 55797 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(55895), // Rule ID 2366 //
     /* 55802 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55805 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55808 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55811 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55814 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55818 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55822 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55826 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55830 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55834 */   // MIs[1] Operand 1
     /* 55834 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 55839 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55844 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55849 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55853 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55857 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55859 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR32:{ *:[i32] }:$F)
     /* 55859 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55862 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 55866 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55871 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55875 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55879 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55881 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55884 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55886 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55888 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55891 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55893 */   GIR_RootConstrainSelectedInstOperands,
     /* 55894 */   // GIR_Coverage, 2366,
     /* 55894 */   GIR_EraseRootFromParent_Done,
     /* 55895 */ // Label 1368: @55895
     /* 55895 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(55993), // Rule ID 2369 //
     /* 55900 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 55903 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 55906 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 55909 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 55912 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55916 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 55920 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 55924 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 55928 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 55932 */   // MIs[1] Operand 1
     /* 55932 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 55937 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55942 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55947 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55951 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 55955 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 55957 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVZ_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 55957 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 55960 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 55964 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 55969 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 55973 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 55977 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 55979 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_MM),
     /* 55982 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 55984 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 55986 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 55989 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 55991 */   GIR_RootConstrainSelectedInstOperands,
     /* 55992 */   // GIR_Coverage, 2369,
     /* 55992 */   GIR_EraseRootFromParent_Done,
     /* 55993 */ // Label 1369: @55993
     /* 55993 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(56091), // Rule ID 2372 //
     /* 55998 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56001 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56004 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56007 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56010 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56014 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56018 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56022 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56026 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56030 */   // MIs[1] Operand 1
     /* 56030 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 56035 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56040 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56045 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56049 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56053 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56055 */   // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR32:{ *:[i32] }:$F)
     /* 56055 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56058 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 56062 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56067 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56071 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56075 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56077 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 56080 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 56082 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56084 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56087 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56089 */   GIR_RootConstrainSelectedInstOperands,
     /* 56090 */   // GIR_Coverage, 2372,
     /* 56090 */   GIR_EraseRootFromParent_Done,
     /* 56091 */ // Label 1370: @56091
     /* 56091 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(56189), // Rule ID 2407 //
     /* 56096 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56099 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56102 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56105 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56108 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56112 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56116 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56120 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56124 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56128 */   // MIs[1] Operand 1
     /* 56128 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 56133 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56138 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56143 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56147 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56151 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56153 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 56153 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56156 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 56160 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56165 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56169 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56173 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56175 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 56178 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56180 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56182 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56185 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56187 */   GIR_RootConstrainSelectedInstOperands,
     /* 56188 */   // GIR_Coverage, 2407,
     /* 56188 */   GIR_EraseRootFromParent_Done,
     /* 56189 */ // Label 1371: @56189
     /* 56189 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(56287), // Rule ID 2408 //
     /* 56194 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56197 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56200 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56203 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56210 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56214 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56218 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56222 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56226 */   // MIs[1] Operand 1
     /* 56226 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 56231 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56236 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56241 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56245 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56249 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56251 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 56251 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56254 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 56258 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56263 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56267 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56271 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 56276 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56278 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56280 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56283 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56285 */   GIR_RootConstrainSelectedInstOperands,
     /* 56286 */   // GIR_Coverage, 2408,
     /* 56286 */   GIR_EraseRootFromParent_Done,
     /* 56287 */ // Label 1372: @56287
     /* 56287 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(56385), // Rule ID 2411 //
     /* 56292 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56295 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56298 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56301 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56304 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56308 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56312 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56316 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56320 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56324 */   // MIs[1] Operand 1
     /* 56324 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 56329 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56334 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56339 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56343 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56347 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56349 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 56349 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56352 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 56356 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56361 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56365 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56369 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56371 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 56374 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56376 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56378 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56381 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56383 */   GIR_RootConstrainSelectedInstOperands,
     /* 56384 */   // GIR_Coverage, 2411,
     /* 56384 */   GIR_EraseRootFromParent_Done,
     /* 56385 */ // Label 1373: @56385
     /* 56385 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(56483), // Rule ID 2412 //
     /* 56390 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56393 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56396 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56399 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56406 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56410 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56414 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56418 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56422 */   // MIs[1] Operand 1
     /* 56422 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 56427 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56432 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56437 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56441 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56445 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56447 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR32:{ *:[f32] }:$F)
     /* 56447 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56450 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 56454 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56459 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56463 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56467 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56469 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 56472 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56474 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56476 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56479 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56481 */   GIR_RootConstrainSelectedInstOperands,
     /* 56482 */   // GIR_Coverage, 2412,
     /* 56482 */   GIR_EraseRootFromParent_Done,
     /* 56483 */ // Label 1374: @56483
     /* 56483 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(56581), // Rule ID 2415 //
     /* 56488 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56491 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56494 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56497 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56504 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56508 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56512 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56516 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56520 */   // MIs[1] Operand 1
     /* 56520 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 56525 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56530 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56535 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56539 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56543 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56545 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVZ_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 56545 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56548 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 56552 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56557 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56561 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56565 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56567 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_S_MM),
     /* 56570 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56572 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56574 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56577 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56579 */   GIR_RootConstrainSelectedInstOperands,
     /* 56580 */   // GIR_Coverage, 2415,
     /* 56580 */   GIR_EraseRootFromParent_Done,
     /* 56581 */ // Label 1375: @56581
     /* 56581 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(56679), // Rule ID 2417 //
     /* 56586 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 56589 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56592 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56595 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56598 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56602 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 56606 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 56610 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 56614 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 56618 */   // MIs[1] Operand 1
     /* 56618 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 56623 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56628 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56633 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56637 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56641 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 56643 */   // (select:{ *:[f32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR32:{ *:[f32] }:$F)
     /* 56643 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 56646 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 56650 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 56655 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 56659 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 56663 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 56665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
     /* 56668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56670 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56672 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 56675 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56677 */   GIR_RootConstrainSelectedInstOperands,
     /* 56678 */   // GIR_Coverage, 2417,
     /* 56678 */   GIR_EraseRootFromParent_Done,
     /* 56679 */ // Label 1376: @56679
     /* 56679 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(56719), // Rule ID 370 //
     /* 56684 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
     /* 56687 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56690 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56693 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56696 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56700 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56704 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56708 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56712 */   // (select:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)  =>  (PseudoSELECT_I:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$cond, GPR32Opnd:{ *:[i32] }:$T, GPR32Opnd:{ *:[i32] }:$F)
     /* 56712 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I),
     /* 56717 */   GIR_RootConstrainSelectedInstOperands,
     /* 56718 */   // GIR_Coverage, 370,
     /* 56718 */   GIR_Done,
     /* 56719 */ // Label 1377: @56719
     /* 56719 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(56759), // Rule ID 372 //
     /* 56724 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
     /* 56727 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56730 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56733 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56736 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56740 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56744 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56748 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56752 */   // (select:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)  =>  (PseudoSELECT_S:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$cond, FGR32Opnd:{ *:[f32] }:$T, FGR32Opnd:{ *:[f32] }:$F)
     /* 56752 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_S),
     /* 56757 */   GIR_RootConstrainSelectedInstOperands,
     /* 56758 */   // GIR_Coverage, 372,
     /* 56758 */   GIR_Done,
     /* 56759 */ // Label 1378: @56759
     /* 56759 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(56805), // Rule ID 409 //
     /* 56764 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 56767 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56770 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56773 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56776 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56780 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
     /* 56784 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56788 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56792 */   // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 56792 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S),
     /* 56795 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56797 */   GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
     /* 56799 */   GIR_RootToRootCopy, /*OpIdx*/3, // fs
     /* 56801 */   GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 56803 */   GIR_RootConstrainSelectedInstOperands,
     /* 56804 */   // GIR_Coverage, 409,
     /* 56804 */   GIR_EraseRootFromParent_Done,
     /* 56805 */ // Label 1379: @56805
     /* 56805 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(56851), // Rule ID 1288 //
     /* 56810 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 56813 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56816 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56819 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56822 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56826 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32CCRegClassID),
     /* 56830 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56834 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56838 */   // (select:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)  =>  (SEL_S_MMR6:{ *:[f32] } FGR32CCOpnd:{ *:[i32] }:$fd_in, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 56838 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_S_MMR6),
     /* 56841 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56843 */   GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
     /* 56845 */   GIR_RootToRootCopy, /*OpIdx*/3, // fs
     /* 56847 */   GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 56849 */   GIR_RootConstrainSelectedInstOperands,
     /* 56850 */   // GIR_Coverage, 1288,
     /* 56850 */   GIR_EraseRootFromParent_Done,
     /* 56851 */ // Label 1380: @56851
     /* 56851 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(56897), // Rule ID 1749 //
     /* 56856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 56859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56862 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56865 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56868 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56872 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56876 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56880 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56884 */   // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
     /* 56884 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I),
     /* 56887 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 56889 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56891 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 56893 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56895 */   GIR_RootConstrainSelectedInstOperands,
     /* 56896 */   // GIR_Coverage, 1749,
     /* 56896 */   GIR_EraseRootFromParent_Done,
     /* 56897 */ // Label 1381: @56897
     /* 56897 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(56943), // Rule ID 1788 //
     /* 56902 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 56905 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 56908 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56911 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56914 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56918 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 56922 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56926 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56930 */   // (select:{ *:[i32] } GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I64_I:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR64:{ *:[i64] }:$cond, GPR32:{ *:[i32] }:$F)
     /* 56930 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I),
     /* 56933 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 56935 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56937 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 56939 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56941 */   GIR_RootConstrainSelectedInstOperands,
     /* 56942 */   // GIR_Coverage, 1788,
     /* 56942 */   GIR_EraseRootFromParent_Done,
     /* 56943 */ // Label 1382: @56943
     /* 56943 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(56989), // Rule ID 1804 //
     /* 56948 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 56951 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 56954 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 56957 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 56960 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56964 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 56968 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56972 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 56976 */   // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
     /* 56976 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S),
     /* 56979 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 56981 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 56983 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 56985 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 56987 */   GIR_RootConstrainSelectedInstOperands,
     /* 56988 */   // GIR_Coverage, 1804,
     /* 56988 */   GIR_EraseRootFromParent_Done,
     /* 56989 */ // Label 1383: @56989
     /* 56989 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(57035), // Rule ID 1817 //
     /* 56994 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 56997 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 57000 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57003 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57006 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57010 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57014 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57018 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57022 */   // (select:{ *:[f32] } GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I64_S:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR64:{ *:[i64] }:$cond, FGR32:{ *:[f32] }:$F)
     /* 57022 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_S),
     /* 57025 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57027 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57029 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 57031 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57033 */   GIR_RootConstrainSelectedInstOperands,
     /* 57034 */   // GIR_Coverage, 1817,
     /* 57034 */   GIR_EraseRootFromParent_Done,
     /* 57035 */ // Label 1384: @57035
     /* 57035 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(57081), // Rule ID 2011 //
     /* 57040 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 57043 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57046 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57049 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57052 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 57056 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 57060 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 57064 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::CPU16RegsRegClassID),
     /* 57068 */   // (select:{ *:[i32] } CPU16Regs:{ *:[i32] }:$a, CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y)  =>  (SelBneZ:{ *:[i32] } CPU16Regs:{ *:[i32] }:$x, CPU16Regs:{ *:[i32] }:$y, CPU16Regs:{ *:[i32] }:$a)
     /* 57068 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SelBneZ),
     /* 57071 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd_]
     /* 57073 */   GIR_RootToRootCopy, /*OpIdx*/2, // x
     /* 57075 */   GIR_RootToRootCopy, /*OpIdx*/3, // y
     /* 57077 */   GIR_RootToRootCopy, /*OpIdx*/1, // a
     /* 57079 */   GIR_RootConstrainSelectedInstOperands,
     /* 57080 */   // GIR_Coverage, 2011,
     /* 57080 */   GIR_EraseRootFromParent_Done,
     /* 57081 */ // Label 1385: @57081
     /* 57081 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(57127), // Rule ID 2359 //
     /* 57086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6),
     /* 57089 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57092 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57095 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57098 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57102 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57106 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57110 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57114 */   // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
     /* 57114 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 57117 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57119 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57121 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 57123 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57125 */   GIR_RootConstrainSelectedInstOperands,
     /* 57126 */   // GIR_Coverage, 2359,
     /* 57126 */   GIR_EraseRootFromParent_Done,
     /* 57127 */ // Label 1386: @57127
     /* 57127 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(57173), // Rule ID 2373 //
     /* 57132 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 57135 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57138 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57141 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57144 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57148 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57152 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57156 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57160 */   // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$F)  =>  (MOVN_I_MM:{ *:[i32] } GPR32:{ *:[i32] }:$T, GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$F)
     /* 57160 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_MM),
     /* 57163 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57165 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57167 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 57169 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57171 */   GIR_RootConstrainSelectedInstOperands,
     /* 57172 */   // GIR_Coverage, 2373,
     /* 57172 */   GIR_EraseRootFromParent_Done,
     /* 57173 */ // Label 1387: @57173
     /* 57173 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(57219), // Rule ID 2418 //
     /* 57178 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6),
     /* 57181 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57184 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57187 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57190 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57194 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57198 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57202 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 57206 */   // (select:{ *:[f32] } GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$T, FGR32:{ *:[f32] }:$F)  =>  (MOVN_I_S_MM:{ *:[f32] } FGR32:{ *:[f32] }:$T, GPR32:{ *:[i32] }:$cond, FGR32:{ *:[f32] }:$F)
     /* 57206 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_S_MM),
     /* 57209 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57211 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57213 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 57215 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57217 */   GIR_RootConstrainSelectedInstOperands,
     /* 57218 */   // GIR_Coverage, 2418,
     /* 57218 */   GIR_EraseRootFromParent_Done,
     /* 57219 */ // Label 1388: @57219
     /* 57219 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(57297), // Rule ID 1878 //
     /* 57224 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 57227 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57230 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57233 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57236 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57240 */   // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR:{ *:[i32] } (SELNEZ:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
     /* 57240 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 57243 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ),
     /* 57247 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 57252 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
     /* 57256 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 57260 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 57262 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 57265 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ),
     /* 57269 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 57274 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
     /* 57278 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 57282 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 57284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR),
     /* 57287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57289 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 57292 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 57295 */   GIR_RootConstrainSelectedInstOperands,
     /* 57296 */   // GIR_Coverage, 1878,
     /* 57296 */   GIR_EraseRootFromParent_Done,
     /* 57297 */ // Label 1389: @57297
     /* 57297 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(57375), // Rule ID 2435 //
     /* 57302 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 57305 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57308 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 57311 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 57314 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57318 */   // (select:{ *:[i32] } i32:{ *:[i32] }:$cond, i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$f)  =>  (OR_MM:{ *:[i32] } (SELNEZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$t, i32:{ *:[i32] }:$cond), (SELEQZ_MMR6:{ *:[i32] } i32:{ *:[i32] }:$f, i32:{ *:[i32] }:$cond))
     /* 57318 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
     /* 57321 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ_MMR6),
     /* 57325 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 57330 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
     /* 57334 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 57338 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 57340 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 57343 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ_MMR6),
     /* 57347 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 57352 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
     /* 57356 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 57360 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 57362 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR_MM),
     /* 57365 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57367 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 57370 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 57373 */   GIR_RootConstrainSelectedInstOperands,
     /* 57374 */   // GIR_Coverage, 2435,
     /* 57374 */   GIR_EraseRootFromParent_Done,
     /* 57375 */ // Label 1390: @57375
     /* 57375 */ GIM_Reject,
     /* 57376 */ // Label 1305: @57376
     /* 57376 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(57452), // Rule ID 1776 //
     /* 57381 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57384 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57387 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57390 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57393 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57397 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57401 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57405 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 57409 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 57413 */   // MIs[1] Operand 1
     /* 57413 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 57418 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57423 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57427 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57431 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57435 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57437 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
     /* 57437 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 57440 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57442 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57444 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57448 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57450 */   GIR_RootConstrainSelectedInstOperands,
     /* 57451 */   // GIR_Coverage, 1776,
     /* 57451 */   GIR_EraseRootFromParent_Done,
     /* 57452 */ // Label 1391: @57452
     /* 57452 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(57528), // Rule ID 1780 //
     /* 57457 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57460 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57463 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57466 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57469 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57473 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57477 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57481 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 57485 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 57489 */   // MIs[1] Operand 1
     /* 57489 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 57494 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57499 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57503 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57507 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57511 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57513 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
     /* 57513 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
     /* 57516 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57518 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57520 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57524 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57526 */   GIR_RootConstrainSelectedInstOperands,
     /* 57527 */   // GIR_Coverage, 1780,
     /* 57527 */   GIR_EraseRootFromParent_Done,
     /* 57528 */ // Label 1392: @57528
     /* 57528 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(57604), // Rule ID 1786 //
     /* 57533 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57536 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57539 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57542 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57545 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57549 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57553 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57557 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 57561 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 57565 */   // MIs[1] Operand 1
     /* 57565 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 57570 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57575 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57579 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57583 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57587 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57589 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$lhs, GPR64:{ *:[i64] }:$F)
     /* 57589 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
     /* 57592 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57594 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57596 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57600 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57602 */   GIR_RootConstrainSelectedInstOperands,
     /* 57603 */   // GIR_Coverage, 1786,
     /* 57603 */   GIR_EraseRootFromParent_Done,
     /* 57604 */ // Label 1393: @57604
     /* 57604 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(57680), // Rule ID 1792 //
     /* 57609 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57612 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57615 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57618 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57621 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57625 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57629 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57633 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 57637 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 57641 */   // MIs[1] Operand 1
     /* 57641 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 57646 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57651 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57655 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57659 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57663 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57665 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$F)
     /* 57665 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
     /* 57668 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 57670 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57672 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57676 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57678 */   GIR_RootConstrainSelectedInstOperands,
     /* 57679 */   // GIR_Coverage, 1792,
     /* 57679 */   GIR_EraseRootFromParent_Done,
     /* 57680 */ // Label 1394: @57680
     /* 57680 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(57756), // Rule ID 1828 //
     /* 57685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57688 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57691 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57694 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57701 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57705 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57709 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 57713 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 57717 */   // MIs[1] Operand 1
     /* 57717 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 57722 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57727 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57731 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57735 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57739 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57741 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
     /* 57741 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 57744 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57746 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57748 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57752 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57754 */   GIR_RootConstrainSelectedInstOperands,
     /* 57755 */   // GIR_Coverage, 1828,
     /* 57755 */   GIR_EraseRootFromParent_Done,
     /* 57756 */ // Label 1395: @57756
     /* 57756 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(57832), // Rule ID 1831 //
     /* 57761 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57764 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57767 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57770 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57773 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57777 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57781 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57785 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 57789 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 57793 */   // MIs[1] Operand 1
     /* 57793 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 57798 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57803 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57807 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57811 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 57815 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57817 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
     /* 57817 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
     /* 57820 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57822 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57824 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57828 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57830 */   GIR_RootConstrainSelectedInstOperands,
     /* 57831 */   // GIR_Coverage, 1831,
     /* 57831 */   GIR_EraseRootFromParent_Done,
     /* 57832 */ // Label 1396: @57832
     /* 57832 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(57908), // Rule ID 1849 //
     /* 57837 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57840 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57843 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57846 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57849 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57853 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57857 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57861 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 57865 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 57869 */   // MIs[1] Operand 1
     /* 57869 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 57874 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 57879 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57883 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57887 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57891 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57893 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
     /* 57893 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 57896 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57898 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57900 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57904 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57906 */   GIR_RootConstrainSelectedInstOperands,
     /* 57907 */   // GIR_Coverage, 1849,
     /* 57907 */   GIR_EraseRootFromParent_Done,
     /* 57908 */ // Label 1397: @57908
     /* 57908 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(57984), // Rule ID 1851 //
     /* 57913 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57916 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57919 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57922 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 57925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57929 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 57933 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 57937 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 57941 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 57945 */   // MIs[1] Operand 1
     /* 57945 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 57950 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 57955 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 57959 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57963 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 57967 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 57969 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
     /* 57969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
     /* 57972 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 57974 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 57976 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 57980 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 57982 */   GIR_RootConstrainSelectedInstOperands,
     /* 57983 */   // GIR_Coverage, 1851,
     /* 57983 */   GIR_EraseRootFromParent_Done,
     /* 57984 */ // Label 1398: @57984
     /* 57984 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(58060), // Rule ID 1854 //
     /* 57989 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 57992 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 57995 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 57998 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58005 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58009 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58013 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58017 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58021 */   // MIs[1] Operand 1
     /* 58021 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 58026 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58031 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 58035 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58039 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58043 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58045 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, FGR64:{ *:[f64] }:$F)
     /* 58045 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
     /* 58048 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 58050 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58052 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58056 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58058 */   GIR_RootConstrainSelectedInstOperands,
     /* 58059 */   // GIR_Coverage, 1854,
     /* 58059 */   GIR_EraseRootFromParent_Done,
     /* 58060 */ // Label 1399: @58060
     /* 58060 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(58136), // Rule ID 1857 //
     /* 58065 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58068 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58071 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58074 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58077 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58081 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58085 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58089 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 58093 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 58097 */   // MIs[1] Operand 1
     /* 58097 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 58102 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58107 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 58111 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58115 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 58119 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58121 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, 0:{ *:[i64] }, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$lhs, FGR64:{ *:[f64] }:$F)
     /* 58121 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
     /* 58124 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 58126 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58128 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58132 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58134 */   GIR_RootConstrainSelectedInstOperands,
     /* 58135 */   // GIR_Coverage, 1857,
     /* 58135 */   GIR_EraseRootFromParent_Done,
     /* 58136 */ // Label 1400: @58136
     /* 58136 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(58212), // Rule ID 2429 //
     /* 58141 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 58144 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58147 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58150 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58153 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58157 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58161 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58165 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58169 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58173 */   // MIs[1] Operand 1
     /* 58173 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 58178 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58183 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 58187 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58191 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58195 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58197 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
     /* 58197 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 58200 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 58202 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58204 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58208 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58210 */   GIR_RootConstrainSelectedInstOperands,
     /* 58211 */   // GIR_Coverage, 2429,
     /* 58211 */   GIR_EraseRootFromParent_Done,
     /* 58212 */ // Label 1401: @58212
     /* 58212 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(58288), // Rule ID 2432 //
     /* 58217 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 58220 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58223 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58226 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58233 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58237 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58241 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58245 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58249 */   // MIs[1] Operand 1
     /* 58249 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 58254 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58259 */   GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0,
     /* 58263 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58267 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 58271 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58273 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, 0:{ *:[i32] }, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$lhs, AFGR64:{ *:[f64] }:$F)
     /* 58273 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
     /* 58276 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 58278 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58280 */   GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58284 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58286 */   GIR_RootConstrainSelectedInstOperands,
     /* 58287 */   // GIR_Coverage, 2432,
     /* 58287 */   GIR_EraseRootFromParent_Done,
     /* 58288 */ // Label 1402: @58288
     /* 58288 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(58386), // Rule ID 1751 //
     /* 58293 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58296 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58299 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58302 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58305 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58309 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58313 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58317 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58321 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58325 */   // MIs[1] Operand 1
     /* 58325 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 58330 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58335 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58340 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58344 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58348 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58350 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 58350 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58353 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 58357 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58362 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58366 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58370 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58372 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58375 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58377 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58379 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58382 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58384 */   GIR_RootConstrainSelectedInstOperands,
     /* 58385 */   // GIR_Coverage, 1751,
     /* 58385 */   GIR_EraseRootFromParent_Done,
     /* 58386 */ // Label 1403: @58386
     /* 58386 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(58484), // Rule ID 1752 //
     /* 58391 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58394 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58397 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58400 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58403 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58407 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58411 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58415 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58419 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58423 */   // MIs[1] Operand 1
     /* 58423 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 58428 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58433 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58438 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58442 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58446 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58448 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 58448 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58451 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 58455 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58460 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58464 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58468 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58470 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58473 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58475 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58477 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58480 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58482 */   GIR_RootConstrainSelectedInstOperands,
     /* 58483 */   // GIR_Coverage, 1752,
     /* 58483 */   GIR_EraseRootFromParent_Done,
     /* 58484 */ // Label 1404: @58484
     /* 58484 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(58582), // Rule ID 1755 //
     /* 58489 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58492 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58495 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58498 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58501 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58505 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58509 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58513 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58517 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58521 */   // MIs[1] Operand 1
     /* 58521 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 58526 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58531 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58536 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58540 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58544 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58546 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
     /* 58546 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58549 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 58553 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58558 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58562 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58566 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58568 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58571 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58573 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58575 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58578 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58580 */   GIR_RootConstrainSelectedInstOperands,
     /* 58581 */   // GIR_Coverage, 1755,
     /* 58581 */   GIR_EraseRootFromParent_Done,
     /* 58582 */ // Label 1405: @58582
     /* 58582 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(58680), // Rule ID 1756 //
     /* 58587 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58593 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58596 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58599 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58603 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58607 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58611 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 58615 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 58619 */   // MIs[1] Operand 1
     /* 58619 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 58624 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58629 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 58634 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58638 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58642 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58644 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), GPR64:{ *:[i64] }:$F)
     /* 58644 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58647 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 58651 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58656 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58660 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58664 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58666 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58669 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58671 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58673 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58676 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58678 */   GIR_RootConstrainSelectedInstOperands,
     /* 58679 */   // GIR_Coverage, 1756,
     /* 58679 */   GIR_EraseRootFromParent_Done,
     /* 58680 */ // Label 1406: @58680
     /* 58680 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(58778), // Rule ID 1767 //
     /* 58685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58688 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58691 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58694 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58697 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58701 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58705 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58709 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 58713 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 58717 */   // MIs[1] Operand 1
     /* 58717 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 58722 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58727 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58732 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58736 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58740 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58742 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 58742 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58745 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 58749 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58754 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58758 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58762 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58764 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58767 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58769 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58771 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58774 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58776 */   GIR_RootConstrainSelectedInstOperands,
     /* 58777 */   // GIR_Coverage, 1767,
     /* 58777 */   GIR_EraseRootFromParent_Done,
     /* 58778 */ // Label 1407: @58778
     /* 58778 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(58876), // Rule ID 1768 //
     /* 58783 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58786 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58789 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58792 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58795 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58799 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58803 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58807 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 58811 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 58815 */   // MIs[1] Operand 1
     /* 58815 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 58820 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58825 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58830 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58834 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58838 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58840 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 58840 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58843 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 58847 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58852 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58856 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58860 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58862 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58865 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58867 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58869 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58872 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58874 */   GIR_RootConstrainSelectedInstOperands,
     /* 58875 */   // GIR_Coverage, 1768,
     /* 58875 */   GIR_EraseRootFromParent_Done,
     /* 58876 */ // Label 1408: @58876
     /* 58876 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(58974), // Rule ID 1771 //
     /* 58881 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58884 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58887 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58890 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58893 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58897 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58901 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 58905 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 58909 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 58913 */   // MIs[1] Operand 1
     /* 58913 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 58918 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58923 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58928 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58932 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58936 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 58938 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
     /* 58938 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 58941 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 58945 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 58950 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 58954 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 58958 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 58960 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 58963 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 58965 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 58967 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 58970 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 58972 */   GIR_RootConstrainSelectedInstOperands,
     /* 58973 */   // GIR_Coverage, 1771,
     /* 58973 */   GIR_EraseRootFromParent_Done,
     /* 58974 */ // Label 1409: @58974
     /* 58974 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(59072), // Rule ID 1772 //
     /* 58979 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 58982 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 58985 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 58988 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 58991 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 58995 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 58999 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59003 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 59007 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 59011 */   // MIs[1] Operand 1
     /* 59011 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 59016 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59021 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59026 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59030 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59034 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59036 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), GPR64:{ *:[i64] }:$F)
     /* 59036 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59039 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 59043 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59048 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59052 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59056 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59058 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 59061 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 59063 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59065 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59068 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59070 */   GIR_RootConstrainSelectedInstOperands,
     /* 59071 */   // GIR_Coverage, 1772,
     /* 59071 */   GIR_EraseRootFromParent_Done,
     /* 59072 */ // Label 1410: @59072
     /* 59072 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(59170), // Rule ID 1775 //
     /* 59077 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59080 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59083 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59086 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59089 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59093 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59097 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59101 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59105 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59109 */   // MIs[1] Operand 1
     /* 59109 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 59114 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59119 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59124 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59128 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59132 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59134 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 59134 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59137 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 59141 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59146 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59150 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59154 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59156 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_I64),
     /* 59159 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 59161 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59163 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59166 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59168 */   GIR_RootConstrainSelectedInstOperands,
     /* 59169 */   // GIR_Coverage, 1775,
     /* 59169 */   GIR_EraseRootFromParent_Done,
     /* 59170 */ // Label 1411: @59170
     /* 59170 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(59268), // Rule ID 1779 //
     /* 59175 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59178 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59181 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59184 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59187 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59191 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59195 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59199 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 59203 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 59207 */   // MIs[1] Operand 1
     /* 59207 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 59212 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59217 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59222 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59226 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59230 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59232 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVZ_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 59232 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 59235 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 59239 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59244 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59248 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59252 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59254 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_I64),
     /* 59257 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 59259 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59261 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59264 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59266 */   GIR_RootConstrainSelectedInstOperands,
     /* 59267 */   // GIR_Coverage, 1779,
     /* 59267 */   GIR_EraseRootFromParent_Done,
     /* 59268 */ // Label 1412: @59268
     /* 59268 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(59366), // Rule ID 1784 //
     /* 59273 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59276 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59279 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59282 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59285 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59289 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59293 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59297 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59301 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59305 */   // MIs[1] Operand 1
     /* 59305 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 59310 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59315 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59320 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59324 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59328 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59330 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 59330 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59333 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 59337 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59342 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59346 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59350 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59352 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
     /* 59355 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 59357 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59359 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59362 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59364 */   GIR_RootConstrainSelectedInstOperands,
     /* 59365 */   // GIR_Coverage, 1784,
     /* 59365 */   GIR_EraseRootFromParent_Done,
     /* 59366 */ // Label 1413: @59366
     /* 59366 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(59464), // Rule ID 1790 //
     /* 59371 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59374 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59377 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59380 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59383 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59387 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59391 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59395 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 59399 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 59403 */   // MIs[1] Operand 1
     /* 59403 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 59408 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59413 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59418 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59422 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 59426 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59428 */   // (select:{ *:[i64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), GPR64:{ *:[i64] }:$F)
     /* 59428 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 59431 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 59435 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59440 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59444 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59448 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59450 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
     /* 59453 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 59455 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59457 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59460 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59462 */   GIR_RootConstrainSelectedInstOperands,
     /* 59463 */   // GIR_Coverage, 1790,
     /* 59463 */   GIR_EraseRootFromParent_Done,
     /* 59464 */ // Label 1414: @59464
     /* 59464 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(59562), // Rule ID 1819 //
     /* 59469 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59472 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59475 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59478 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59481 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59485 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59489 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59493 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59497 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59501 */   // MIs[1] Operand 1
     /* 59501 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 59506 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59511 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59516 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59520 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59524 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59526 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 59526 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59529 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 59533 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59538 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59542 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59546 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59548 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 59551 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 59553 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59555 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59558 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59560 */   GIR_RootConstrainSelectedInstOperands,
     /* 59561 */   // GIR_Coverage, 1819,
     /* 59561 */   GIR_EraseRootFromParent_Done,
     /* 59562 */ // Label 1415: @59562
     /* 59562 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(59660), // Rule ID 1820 //
     /* 59567 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59570 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59573 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59576 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59579 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59583 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59587 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59591 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59595 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59599 */   // MIs[1] Operand 1
     /* 59599 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 59604 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59609 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59614 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59618 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59622 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59624 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 59624 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59627 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 59631 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59636 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59640 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59644 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59646 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 59649 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 59651 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59653 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59656 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59658 */   GIR_RootConstrainSelectedInstOperands,
     /* 59659 */   // GIR_Coverage, 1820,
     /* 59659 */   GIR_EraseRootFromParent_Done,
     /* 59660 */ // Label 1416: @59660
     /* 59660 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(59758), // Rule ID 1823 //
     /* 59665 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59668 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59671 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59674 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59677 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59681 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59685 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59689 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59693 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59697 */   // MIs[1] Operand 1
     /* 59697 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 59702 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59707 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59712 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59716 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59720 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59722 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
     /* 59722 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59725 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 59729 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59734 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59738 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59742 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59744 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 59747 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 59749 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59751 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59754 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59756 */   GIR_RootConstrainSelectedInstOperands,
     /* 59757 */   // GIR_Coverage, 1823,
     /* 59757 */   GIR_EraseRootFromParent_Done,
     /* 59758 */ // Label 1417: @59758
     /* 59758 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(59856), // Rule ID 1824 //
     /* 59763 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59766 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59769 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59772 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59775 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59779 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59783 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59787 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59791 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59795 */   // MIs[1] Operand 1
     /* 59795 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 59800 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59805 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59810 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59814 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59818 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59820 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
     /* 59820 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59823 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 59827 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59832 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59836 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59840 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59842 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 59845 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 59847 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59849 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59852 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59854 */   GIR_RootConstrainSelectedInstOperands,
     /* 59855 */   // GIR_Coverage, 1824,
     /* 59855 */   GIR_EraseRootFromParent_Done,
     /* 59856 */ // Label 1418: @59856
     /* 59856 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(59954), // Rule ID 1827 //
     /* 59861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59867 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59870 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59877 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59881 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59885 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59889 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59893 */   // MIs[1] Operand 1
     /* 59893 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 59898 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59903 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 59908 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59912 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59916 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 59918 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 59918 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 59921 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 59925 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 59930 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 59934 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 59938 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 59940 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32),
     /* 59943 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 59945 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 59947 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 59950 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 59952 */   GIR_RootConstrainSelectedInstOperands,
     /* 59953 */   // GIR_Coverage, 1827,
     /* 59953 */   GIR_EraseRootFromParent_Done,
     /* 59954 */ // Label 1419: @59954
     /* 59954 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(60052), // Rule ID 1829 //
     /* 59959 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 59962 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 59965 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 59968 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 59971 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 59975 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 59979 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 59983 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 59987 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 59991 */   // MIs[1] Operand 1
     /* 59991 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 59996 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60001 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60006 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 60010 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 60014 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60016 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 60016 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60019 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 60023 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60028 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60032 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60036 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60038 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
     /* 60041 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60043 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60045 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60048 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60050 */   GIR_RootConstrainSelectedInstOperands,
     /* 60051 */   // GIR_Coverage, 1829,
     /* 60051 */   GIR_EraseRootFromParent_Done,
     /* 60052 */ // Label 1420: @60052
     /* 60052 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(60150), // Rule ID 1832 //
     /* 60057 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60060 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60063 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60066 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60069 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60073 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60077 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60081 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 60085 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 60089 */   // MIs[1] Operand 1
     /* 60089 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 60094 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60099 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60104 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60108 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60112 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60114 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60114 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60117 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 60121 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60126 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60130 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60134 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60136 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60139 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60141 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60143 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60146 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60148 */   GIR_RootConstrainSelectedInstOperands,
     /* 60149 */   // GIR_Coverage, 1832,
     /* 60149 */   GIR_EraseRootFromParent_Done,
     /* 60150 */ // Label 1421: @60150
     /* 60150 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(60248), // Rule ID 1833 //
     /* 60155 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60158 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60161 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60164 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60167 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60171 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60175 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60179 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 60183 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 60187 */   // MIs[1] Operand 1
     /* 60187 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 60192 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60197 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60202 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60206 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60210 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60212 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60212 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60215 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 60219 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60224 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60228 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60232 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60234 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60237 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60239 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60241 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60244 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60246 */   GIR_RootConstrainSelectedInstOperands,
     /* 60247 */   // GIR_Coverage, 1833,
     /* 60247 */   GIR_EraseRootFromParent_Done,
     /* 60248 */ // Label 1422: @60248
     /* 60248 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(60346), // Rule ID 1836 //
     /* 60253 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60256 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60259 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60262 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60265 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60269 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60273 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60277 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 60281 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 60285 */   // MIs[1] Operand 1
     /* 60285 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 60290 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60295 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60300 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60304 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60308 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60310 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
     /* 60310 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60313 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT),
     /* 60317 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60322 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60326 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60330 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60332 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60335 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60337 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60339 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60342 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60344 */   GIR_RootConstrainSelectedInstOperands,
     /* 60345 */   // GIR_Coverage, 1836,
     /* 60345 */   GIR_EraseRootFromParent_Done,
     /* 60346 */ // Label 1423: @60346
     /* 60346 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(60444), // Rule ID 1837 //
     /* 60351 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60354 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60357 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60360 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60363 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60367 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60371 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60375 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 60379 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 60383 */   // MIs[1] Operand 1
     /* 60383 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 60388 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60393 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60398 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60402 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60406 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60408 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), FGR64:{ *:[f64] }:$F)
     /* 60408 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60411 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu),
     /* 60415 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60420 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60424 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60428 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60430 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60433 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60435 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60437 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60440 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60442 */   GIR_RootConstrainSelectedInstOperands,
     /* 60443 */   // GIR_Coverage, 1837,
     /* 60443 */   GIR_EraseRootFromParent_Done,
     /* 60444 */ // Label 1424: @60444
     /* 60444 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(60542), // Rule ID 1840 //
     /* 60449 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60452 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60455 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60458 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60461 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60465 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60469 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60473 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 60477 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 60481 */   // MIs[1] Operand 1
     /* 60481 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 60486 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60491 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60496 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60500 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60504 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60506 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60506 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60509 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 60513 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60518 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60522 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60526 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60528 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60531 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60533 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60535 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60538 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60540 */   GIR_RootConstrainSelectedInstOperands,
     /* 60541 */   // GIR_Coverage, 1840,
     /* 60541 */   GIR_EraseRootFromParent_Done,
     /* 60542 */ // Label 1425: @60542
     /* 60542 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(60640), // Rule ID 1841 //
     /* 60547 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60550 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60553 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60556 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60559 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60563 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60567 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60571 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 60575 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 60579 */   // MIs[1] Operand 1
     /* 60579 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 60584 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60589 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60594 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60598 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60602 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60604 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETUGE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60604 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60607 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 60611 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60616 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60620 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60624 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60626 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60629 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60631 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60633 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60636 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60638 */   GIR_RootConstrainSelectedInstOperands,
     /* 60639 */   // GIR_Coverage, 1841,
     /* 60639 */   GIR_EraseRootFromParent_Done,
     /* 60640 */ // Label 1426: @60640
     /* 60640 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(60738), // Rule ID 1844 //
     /* 60645 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60648 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60651 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60654 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60657 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60661 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60665 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60669 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 60673 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 60677 */   // MIs[1] Operand 1
     /* 60677 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 60682 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60687 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60692 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60696 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60700 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60702 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETLE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLT64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
     /* 60702 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60705 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT64),
     /* 60709 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60714 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60718 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60722 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60724 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60727 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60729 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60731 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60734 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60736 */   GIR_RootConstrainSelectedInstOperands,
     /* 60737 */   // GIR_Coverage, 1844,
     /* 60737 */   GIR_EraseRootFromParent_Done,
     /* 60738 */ // Label 1427: @60738
     /* 60738 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(60836), // Rule ID 1845 //
     /* 60743 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60746 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60749 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60752 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60755 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60759 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60763 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60767 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 60771 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 60775 */   // MIs[1] Operand 1
     /* 60775 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 60780 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60785 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60790 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60794 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60798 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60800 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETULE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (SLTu64:{ *:[i32] } GPR64:{ *:[i64] }:$rhs, GPR64:{ *:[i64] }:$lhs), FGR64:{ *:[f64] }:$F)
     /* 60800 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60803 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu64),
     /* 60807 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60812 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60816 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60820 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60822 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60825 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60827 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60829 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60832 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60834 */   GIR_RootConstrainSelectedInstOperands,
     /* 60835 */   // GIR_Coverage, 1845,
     /* 60835 */   GIR_EraseRootFromParent_Done,
     /* 60836 */ // Label 1428: @60836
     /* 60836 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(60934), // Rule ID 1848 //
     /* 60841 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60844 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60847 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60850 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60857 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60861 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60865 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 60869 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 60873 */   // MIs[1] Operand 1
     /* 60873 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 60878 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60883 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 60888 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60892 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60896 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60898 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60898 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 60901 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 60905 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 60910 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 60914 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 60918 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 60920 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D64),
     /* 60923 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 60925 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 60927 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 60930 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 60932 */   GIR_RootConstrainSelectedInstOperands,
     /* 60933 */   // GIR_Coverage, 1848,
     /* 60933 */   GIR_EraseRootFromParent_Done,
     /* 60934 */ // Label 1429: @60934
     /* 60934 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(61032), // Rule ID 1850 //
     /* 60939 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 60942 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 60945 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 60948 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 60951 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60955 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 60959 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 60963 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 60967 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 60971 */   // MIs[1] Operand 1
     /* 60971 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 60976 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60981 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 60986 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60990 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 60994 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 60996 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETEQ:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVZ_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 60996 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 60999 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 61003 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61008 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61012 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61016 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61018 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I64_D64),
     /* 61021 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61023 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61025 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61028 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61030 */   GIR_RootConstrainSelectedInstOperands,
     /* 61031 */   // GIR_Coverage, 1850,
     /* 61031 */   GIR_EraseRootFromParent_Done,
     /* 61032 */ // Label 1430: @61032
     /* 61032 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(61130), // Rule ID 1852 //
     /* 61037 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 61040 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61043 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61046 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61049 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61053 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61057 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61061 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61065 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61069 */   // MIs[1] Operand 1
     /* 61069 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 61074 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61079 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61084 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61088 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61092 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61094 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 61094 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61097 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR),
     /* 61101 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61106 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61110 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61114 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61116 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
     /* 61119 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61121 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61123 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61126 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61128 */   GIR_RootConstrainSelectedInstOperands,
     /* 61129 */   // GIR_Coverage, 1852,
     /* 61129 */   GIR_EraseRootFromParent_Done,
     /* 61130 */ // Label 1431: @61130
     /* 61130 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(61228), // Rule ID 1855 //
     /* 61135 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 61138 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61141 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61144 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61147 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61151 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61155 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61159 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 61163 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
     /* 61167 */   // MIs[1] Operand 1
     /* 61167 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 61172 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 61177 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 61182 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61186 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61190 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61192 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs, SETNE:{ *:[Other] }), FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, (XOR64:{ *:[i64] } GPR64:{ *:[i64] }:$lhs, GPR64:{ *:[i64] }:$rhs), FGR64:{ *:[f64] }:$F)
     /* 61192 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 61195 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR64),
     /* 61199 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61204 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61208 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61212 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61214 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
     /* 61217 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61219 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61221 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61224 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61226 */   GIR_RootConstrainSelectedInstOperands,
     /* 61227 */   // GIR_Coverage, 1855,
     /* 61227 */   GIR_EraseRootFromParent_Done,
     /* 61228 */ // Label 1432: @61228
     /* 61228 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(61326), // Rule ID 2420 //
     /* 61233 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61236 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61239 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61242 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61245 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61249 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61253 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61257 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61261 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61265 */   // MIs[1] Operand 1
     /* 61265 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
     /* 61270 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61275 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61280 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61284 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61288 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61290 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 61290 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61293 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 61297 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61302 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61306 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61310 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61312 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 61315 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61317 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61319 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61322 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61324 */   GIR_RootConstrainSelectedInstOperands,
     /* 61325 */   // GIR_Coverage, 2420,
     /* 61325 */   GIR_EraseRootFromParent_Done,
     /* 61326 */ // Label 1433: @61326
     /* 61326 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(61424), // Rule ID 2421 //
     /* 61331 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61334 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61337 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61340 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61343 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61347 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61351 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61355 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61359 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61363 */   // MIs[1] Operand 1
     /* 61363 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
     /* 61368 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61373 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61378 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61382 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61386 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61388 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETUGE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 61388 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61391 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 61395 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61400 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61404 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61408 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61410 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 61413 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61415 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61417 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61420 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61422 */   GIR_RootConstrainSelectedInstOperands,
     /* 61423 */   // GIR_Coverage, 2421,
     /* 61423 */   GIR_EraseRootFromParent_Done,
     /* 61424 */ // Label 1434: @61424
     /* 61424 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(61522), // Rule ID 2424 //
     /* 61429 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61432 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61435 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61438 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61441 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61445 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61449 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61453 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61457 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61461 */   // MIs[1] Operand 1
     /* 61461 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
     /* 61466 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61471 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61476 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61480 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61484 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61486 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETLE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLT_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
     /* 61486 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61489 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLT_MM),
     /* 61493 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61498 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61502 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61506 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61508 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 61511 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61513 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61515 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61518 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61520 */   GIR_RootConstrainSelectedInstOperands,
     /* 61521 */   // GIR_Coverage, 2424,
     /* 61521 */   GIR_EraseRootFromParent_Done,
     /* 61522 */ // Label 1435: @61522
     /* 61522 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(61620), // Rule ID 2425 //
     /* 61527 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61530 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61533 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61536 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61539 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61543 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61547 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61551 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61555 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61559 */   // MIs[1] Operand 1
     /* 61559 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
     /* 61564 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61569 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61574 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61578 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61582 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61584 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETULE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (SLTu_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rhs, GPR32:{ *:[i32] }:$lhs), AFGR64:{ *:[f64] }:$F)
     /* 61584 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61587 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SLTu_MM),
     /* 61591 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61596 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61600 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61604 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61606 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 61609 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61611 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61613 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61616 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61618 */   GIR_RootConstrainSelectedInstOperands,
     /* 61619 */   // GIR_Coverage, 2425,
     /* 61619 */   GIR_EraseRootFromParent_Done,
     /* 61620 */ // Label 1436: @61620
     /* 61620 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(61718), // Rule ID 2428 //
     /* 61625 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61631 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61634 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61641 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61645 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61649 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61653 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61657 */   // MIs[1] Operand 1
     /* 61657 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
     /* 61662 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61667 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61672 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61676 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61680 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61682 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETEQ:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVZ_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 61682 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61685 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 61689 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61694 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61698 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61702 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61704 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVZ_I_D32_MM),
     /* 61707 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61709 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61711 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61714 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61716 */   GIR_RootConstrainSelectedInstOperands,
     /* 61717 */   // GIR_Coverage, 2428,
     /* 61717 */   GIR_EraseRootFromParent_Done,
     /* 61718 */ // Label 1437: @61718
     /* 61718 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(61816), // Rule ID 2430 //
     /* 61723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 61726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61729 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61732 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61739 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 61743 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP),
     /* 61747 */   GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 61751 */   GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
     /* 61755 */   // MIs[1] Operand 1
     /* 61755 */   GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
     /* 61760 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61765 */   GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61770 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61774 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61778 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 61780 */   // (select:{ *:[f64] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs, SETNE:{ *:[Other] }), AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, (XOR_MM:{ *:[i32] } GPR32:{ *:[i32] }:$lhs, GPR32:{ *:[i32] }:$rhs), AFGR64:{ *:[f64] }:$F)
     /* 61780 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 61783 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::XOR_MM),
     /* 61787 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 61792 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // lhs
     /* 61796 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/3, // rhs
     /* 61800 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 61802 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
     /* 61805 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61807 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 61809 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 61812 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 61814 */   GIR_RootConstrainSelectedInstOperands,
     /* 61815 */   // GIR_Coverage, 2430,
     /* 61815 */   GIR_EraseRootFromParent_Done,
     /* 61816 */ // Label 1438: @61816
     /* 61816 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(61856), // Rule ID 371 //
     /* 61821 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotMips4_32),
     /* 61824 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61827 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61830 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61833 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 61837 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61841 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 61845 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 61849 */   // (select:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)  =>  (PseudoSELECT_I64:{ *:[i64] } GPR32Opnd:{ *:[i32] }:$cond, GPR64Opnd:{ *:[i64] }:$T, GPR64Opnd:{ *:[i64] }:$F)
     /* 61849 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_I64),
     /* 61854 */   GIR_RootConstrainSelectedInstOperands,
     /* 61855 */   // GIR_Coverage, 371,
     /* 61855 */   GIR_Done,
     /* 61856 */ // Label 1439: @61856
     /* 61856 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(61896), // Rule ID 373 //
     /* 61861 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotMips4_32),
     /* 61864 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61867 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61870 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61873 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61877 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61881 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61885 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 61889 */   // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D32:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, AFGR64Opnd:{ *:[f64] }:$T, AFGR64Opnd:{ *:[f64] }:$F)
     /* 61889 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D32),
     /* 61894 */   GIR_RootConstrainSelectedInstOperands,
     /* 61895 */   // GIR_Coverage, 373,
     /* 61895 */   GIR_Done,
     /* 61896 */ // Label 1440: @61896
     /* 61896 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(61936), // Rule ID 374 //
     /* 61901 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotMips4_32),
     /* 61904 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61907 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61910 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61913 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61917 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 61921 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61925 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61929 */   // (select:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)  =>  (PseudoSELECT_D64:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$cond, FGR64Opnd:{ *:[f64] }:$T, FGR64Opnd:{ *:[f64] }:$F)
     /* 61929 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoSELECT_D64),
     /* 61934 */   GIR_RootConstrainSelectedInstOperands,
     /* 61935 */   // GIR_Coverage, 374,
     /* 61935 */   GIR_Done,
     /* 61936 */ // Label 1441: @61936
     /* 61936 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(61982), // Rule ID 408 //
     /* 61941 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 61944 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61947 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61950 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61953 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61957 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
     /* 61961 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61965 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 61969 */   // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs)  =>  (SEL_D:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 61969 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D),
     /* 61972 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 61974 */   GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
     /* 61976 */   GIR_RootToRootCopy, /*OpIdx*/3, // fs
     /* 61978 */   GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 61980 */   GIR_RootConstrainSelectedInstOperands,
     /* 61981 */   // GIR_Coverage, 408,
     /* 61981 */   GIR_EraseRootFromParent_Done,
     /* 61982 */ // Label 1442: @61982
     /* 61982 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(62028), // Rule ID 1289 //
     /* 61987 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 61990 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 61993 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 61996 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 61999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62003 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64CCRegClassID),
     /* 62007 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62011 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62015 */   // (select:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$ft, FGR64Opnd:{ *:[f64] }:$fs)  =>  (SEL_D_MMR6:{ *:[f64] } FGR64CCOpnd:{ *:[i32] }:$fd_in, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 62015 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::SEL_D_MMR6),
     /* 62018 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 62020 */   GIR_RootToRootCopy, /*OpIdx*/1, // fd_in
     /* 62022 */   GIR_RootToRootCopy, /*OpIdx*/3, // fs
     /* 62024 */   GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 62026 */   GIR_RootConstrainSelectedInstOperands,
     /* 62027 */   // GIR_Coverage, 1289,
     /* 62027 */   GIR_EraseRootFromParent_Done,
     /* 62028 */ // Label 1443: @62028
     /* 62028 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(62074), // Rule ID 1785 //
     /* 62033 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 62036 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62039 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62042 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62045 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62049 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62053 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62057 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62061 */   // (select:{ *:[i64] } GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR32:{ *:[i32] }:$cond, GPR64:{ *:[i64] }:$F)
     /* 62061 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_I64),
     /* 62064 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 62066 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62068 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62070 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62072 */   GIR_RootConstrainSelectedInstOperands,
     /* 62073 */   // GIR_Coverage, 1785,
     /* 62073 */   GIR_EraseRootFromParent_Done,
     /* 62074 */ // Label 1444: @62074
     /* 62074 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(62120), // Rule ID 1791 //
     /* 62079 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 62082 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 62085 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62088 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62091 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62095 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62099 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62103 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62107 */   // (select:{ *:[i64] } GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$F)  =>  (MOVN_I64_I64:{ *:[i64] } GPR64:{ *:[i64] }:$T, GPR64:{ *:[i64] }:$cond, GPR64:{ *:[i64] }:$F)
     /* 62107 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_I64),
     /* 62110 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 62112 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62114 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62116 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62118 */   GIR_RootConstrainSelectedInstOperands,
     /* 62119 */   // GIR_Coverage, 1791,
     /* 62119 */   GIR_EraseRootFromParent_Done,
     /* 62120 */ // Label 1445: @62120
     /* 62120 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(62166), // Rule ID 1830 //
     /* 62125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 62128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62131 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62134 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62137 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62141 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62145 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62149 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62153 */   // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
     /* 62153 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32),
     /* 62156 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 62158 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62160 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62162 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62164 */   GIR_RootConstrainSelectedInstOperands,
     /* 62165 */   // GIR_Coverage, 1830,
     /* 62165 */   GIR_EraseRootFromParent_Done,
     /* 62166 */ // Label 1446: @62166
     /* 62166 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(62212), // Rule ID 1853 //
     /* 62171 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 62174 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62177 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62180 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62183 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62187 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62191 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62195 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62199 */   // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, FGR64:{ *:[f64] }:$F)
     /* 62199 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D64),
     /* 62202 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 62204 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62206 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62208 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62210 */   GIR_RootConstrainSelectedInstOperands,
     /* 62211 */   // GIR_Coverage, 1853,
     /* 62211 */   GIR_EraseRootFromParent_Done,
     /* 62212 */ // Label 1447: @62212
     /* 62212 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(62258), // Rule ID 1856 //
     /* 62217 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 62220 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 62223 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62226 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62229 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62233 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62237 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62241 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 62245 */   // (select:{ *:[f64] } GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$T, FGR64:{ *:[f64] }:$F)  =>  (MOVN_I64_D64:{ *:[f64] } FGR64:{ *:[f64] }:$T, GPR64:{ *:[i64] }:$cond, FGR64:{ *:[f64] }:$F)
     /* 62245 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I64_D64),
     /* 62248 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 62250 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62252 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62254 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62256 */   GIR_RootConstrainSelectedInstOperands,
     /* 62257 */   // GIR_Coverage, 1856,
     /* 62257 */   GIR_EraseRootFromParent_Done,
     /* 62258 */ // Label 1448: @62258
     /* 62258 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(62304), // Rule ID 2431 //
     /* 62263 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit_NotMips32r6),
     /* 62266 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62269 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62272 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62275 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62279 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62283 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62287 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 62291 */   // (select:{ *:[f64] } GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$T, AFGR64:{ *:[f64] }:$F)  =>  (MOVN_I_D32_MM:{ *:[f64] } AFGR64:{ *:[f64] }:$T, GPR32:{ *:[i32] }:$cond, AFGR64:{ *:[f64] }:$F)
     /* 62291 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MOVN_I_D32_MM),
     /* 62294 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 62296 */   GIR_RootToRootCopy, /*OpIdx*/2, // T
     /* 62298 */   GIR_RootToRootCopy, /*OpIdx*/1, // cond
     /* 62300 */   GIR_RootToRootCopy, /*OpIdx*/3, // F
     /* 62302 */   GIR_RootConstrainSelectedInstOperands,
     /* 62303 */   // GIR_Coverage, 2431,
     /* 62303 */   GIR_EraseRootFromParent_Done,
     /* 62304 */ // Label 1449: @62304
     /* 62304 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(62382), // Rule ID 1909 //
     /* 62309 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 62312 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 62315 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62318 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62321 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62325 */   // (select:{ *:[i64] } i64:{ *:[i64] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$cond), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, i64:{ *:[i64] }:$cond))
     /* 62325 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 62328 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
     /* 62332 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62337 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // f
     /* 62341 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 62345 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 62347 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 62350 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
     /* 62354 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62359 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
     /* 62363 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 62367 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 62369 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
     /* 62372 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 62374 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 62377 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
     /* 62380 */   GIR_RootConstrainSelectedInstOperands,
     /* 62381 */   // GIR_Coverage, 1909,
     /* 62381 */   GIR_EraseRootFromParent_Done,
     /* 62382 */ // Label 1450: @62382
     /* 62382 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(62494), // Rule ID 1920 //
     /* 62387 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc),
     /* 62390 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62393 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62396 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 62399 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62403 */   // (select:{ *:[i64] } i32:{ *:[i32] }:$cond, i64:{ *:[i64] }:$t, i64:{ *:[i64] }:$f)  =>  (OR64:{ *:[i64] } (SELNEZ64:{ *:[i64] } i64:{ *:[i64] }:$t, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)), (SELEQZ64:{ *:[i64] } i64:{ *:[i64] }:$f, (SLL64_32:{ *:[i64] } i32:{ *:[i32] }:$cond)))
     /* 62403 */   GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
     /* 62406 */   GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
     /* 62410 */   GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62415 */   GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 62419 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
     /* 62421 */   GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
     /* 62424 */   GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(Mips::SELEQZ64),
     /* 62428 */   GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62433 */   GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // f
     /* 62437 */   GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
     /* 62440 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
     /* 62442 */   GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
     /* 62445 */   GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(Mips::SLL64_32),
     /* 62449 */   GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62454 */   GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // cond
     /* 62458 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
     /* 62460 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 62463 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::SELNEZ64),
     /* 62467 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 62472 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // t
     /* 62476 */   GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
     /* 62479 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 62481 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::OR64),
     /* 62484 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 62486 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 62489 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
     /* 62492 */   GIR_RootConstrainSelectedInstOperands,
     /* 62493 */   // GIR_Coverage, 1920,
     /* 62493 */   GIR_EraseRootFromParent_Done,
     /* 62494 */ // Label 1451: @62494
     /* 62494 */ GIM_Reject,
     /* 62495 */ // Label 1306: @62495
     /* 62495 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(62568),
     /* 62500 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 62503 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 62506 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 62509 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 62513 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 62517 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 62521 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 62525 */   GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(62546), // Rule ID 658 //
     /* 62530 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62533 */     // (vselect:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$wt, MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (BSEL_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 62533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_D_PSEUDO),
     /* 62536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62538 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62540 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62542 */     GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62544 */     GIR_RootConstrainSelectedInstOperands,
     /* 62545 */     // GIR_Coverage, 658,
     /* 62545 */     GIR_EraseRootFromParent_Done,
     /* 62546 */   // Label 1453: @62546
     /* 62546 */   GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(62567), // Rule ID 660 //
     /* 62551 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62554 */     // (vselect:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$wt, MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (BSEL_FD_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 62554 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FD_PSEUDO),
     /* 62557 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62559 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62561 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62563 */     GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62565 */     GIR_RootConstrainSelectedInstOperands,
     /* 62566 */     // GIR_Coverage, 660,
     /* 62566 */     GIR_EraseRootFromParent_Done,
     /* 62567 */   // Label 1454: @62567
     /* 62567 */   GIM_Reject,
     /* 62568 */ // Label 1452: @62568
     /* 62568 */ GIM_Reject,
     /* 62569 */ // Label 1307: @62569
     /* 62569 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(62642),
     /* 62574 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 62577 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 62580 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 62583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 62587 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 62591 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 62595 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 62599 */   GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(62620), // Rule ID 657 //
     /* 62604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62607 */     // (vselect:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$wt, MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (BSEL_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 62607 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_W_PSEUDO),
     /* 62610 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62612 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62614 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62616 */     GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62618 */     GIR_RootConstrainSelectedInstOperands,
     /* 62619 */     // GIR_Coverage, 657,
     /* 62619 */     GIR_EraseRootFromParent_Done,
     /* 62620 */   // Label 1456: @62620
     /* 62620 */   GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(62641), // Rule ID 659 //
     /* 62625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62628 */     // (vselect:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$wt, MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (BSEL_FW_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 62628 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_FW_PSEUDO),
     /* 62631 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62633 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62635 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62637 */     GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62639 */     GIR_RootConstrainSelectedInstOperands,
     /* 62640 */     // GIR_Coverage, 659,
     /* 62640 */     GIR_EraseRootFromParent_Done,
     /* 62641 */   // Label 1457: @62641
     /* 62641 */   GIM_Reject,
     /* 62642 */ // Label 1455: @62642
     /* 62642 */ GIM_Reject,
     /* 62643 */ // Label 1308: @62643
     /* 62643 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(62689), // Rule ID 656 //
     /* 62648 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62651 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 62654 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 62657 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
     /* 62660 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 62664 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 62668 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 62672 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 62676 */   // (vselect:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$wt, MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (BSEL_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 62676 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_H_PSEUDO),
     /* 62679 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62681 */   GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62683 */   GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62685 */   GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62687 */   GIR_RootConstrainSelectedInstOperands,
     /* 62688 */   // GIR_Coverage, 656,
     /* 62688 */   GIR_EraseRootFromParent_Done,
     /* 62689 */ // Label 1458: @62689
     /* 62689 */ GIM_Reject,
     /* 62690 */ // Label 1309: @62690
     /* 62690 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(62784),
     /* 62695 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 62698 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 62701 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
     /* 62704 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 62708 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 62712 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 62716 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 62720 */   GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(62741), // Rule ID 643 //
     /* 62725 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62728 */     // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wd_in)  =>  (BMNZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 62728 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMNZ_V),
     /* 62731 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62733 */     GIR_RootToRootCopy, /*OpIdx*/3, // wd_in
     /* 62735 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 62737 */     GIR_RootToRootCopy, /*OpIdx*/1, // wt
     /* 62739 */     GIR_RootConstrainSelectedInstOperands,
     /* 62740 */     // GIR_Coverage, 643,
     /* 62740 */     GIR_EraseRootFromParent_Done,
     /* 62741 */   // Label 1460: @62741
     /* 62741 */   GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(62762), // Rule ID 645 //
     /* 62746 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62749 */     // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (BMZ_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 62749 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BMZ_V),
     /* 62752 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62754 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd_in
     /* 62756 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62758 */     GIR_RootToRootCopy, /*OpIdx*/1, // wt
     /* 62760 */     GIR_RootConstrainSelectedInstOperands,
     /* 62761 */     // GIR_Coverage, 645,
     /* 62761 */     GIR_EraseRootFromParent_Done,
     /* 62762 */   // Label 1461: @62762
     /* 62762 */   GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(62783), // Rule ID 655 //
     /* 62767 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 62770 */     // (vselect:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$wt, MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (BSEL_V:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 62770 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::BSEL_V),
     /* 62773 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 62775 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 62777 */     GIR_RootToRootCopy, /*OpIdx*/3, // ws
     /* 62779 */     GIR_RootToRootCopy, /*OpIdx*/2, // wt
     /* 62781 */     GIR_RootConstrainSelectedInstOperands,
     /* 62782 */     // GIR_Coverage, 655,
     /* 62782 */     GIR_EraseRootFromParent_Done,
     /* 62783 */   // Label 1462: @62783
     /* 62783 */   GIM_Reject,
     /* 62784 */ // Label 1459: @62784
     /* 62784 */ GIM_Reject,
     /* 62785 */ // Label 1310: @62785
     /* 62785 */ GIM_Reject,
     /* 62786 */ // Label 44: @62786
     /* 62786 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1465*/ GIMT_Encode4(62894),
     /* 62797 */ /*GILLT_s32*//*Label 1463*/ GIMT_Encode4(62805),
     /* 62801 */ /*GILLT_s64*//*Label 1464*/ GIMT_Encode4(62860),
     /* 62805 */ // Label 1463: @62805
     /* 62805 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(62859),
     /* 62810 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62813 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 62816 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62820 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62824 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62828 */   GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(62843), // Rule ID 406 //
     /* 62833 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 62836 */     // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 62836 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU),
     /* 62841 */     GIR_RootConstrainSelectedInstOperands,
     /* 62842 */     // GIR_Coverage, 406,
     /* 62842 */     GIR_Done,
     /* 62843 */   // Label 1467: @62843
     /* 62843 */   GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(62858), // Rule ID 1256 //
     /* 62848 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 62851 */     // (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUHU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 62851 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUHU_MMR6),
     /* 62856 */     GIR_RootConstrainSelectedInstOperands,
     /* 62857 */     // GIR_Coverage, 1256,
     /* 62857 */     GIR_Done,
     /* 62858 */   // Label 1468: @62858
     /* 62858 */   GIM_Reject,
     /* 62859 */ // Label 1466: @62859
     /* 62859 */ GIM_Reject,
     /* 62860 */ // Label 1464: @62860
     /* 62860 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(62893), // Rule ID 421 //
     /* 62865 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /* 62868 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 62871 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62874 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62878 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62882 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62886 */   // (mulhu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUHU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 62886 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUHU),
     /* 62891 */   GIR_RootConstrainSelectedInstOperands,
     /* 62892 */   // GIR_Coverage, 421,
     /* 62892 */   GIR_Done,
     /* 62893 */ // Label 1469: @62893
     /* 62893 */ GIM_Reject,
     /* 62894 */ // Label 1465: @62894
     /* 62894 */ GIM_Reject,
     /* 62895 */ // Label 45: @62895
     /* 62895 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1472*/ GIMT_Encode4(63003),
     /* 62906 */ /*GILLT_s32*//*Label 1470*/ GIMT_Encode4(62914),
     /* 62910 */ /*GILLT_s64*//*Label 1471*/ GIMT_Encode4(62969),
     /* 62914 */ // Label 1470: @62914
     /* 62914 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(62968),
     /* 62919 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 62922 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 62925 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62929 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62933 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 62937 */   GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(62952), // Rule ID 405 //
     /* 62942 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 62945 */     // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 62945 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH),
     /* 62950 */     GIR_RootConstrainSelectedInstOperands,
     /* 62951 */     // GIR_Coverage, 405,
     /* 62951 */     GIR_Done,
     /* 62952 */   // Label 1474: @62952
     /* 62952 */   GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(62967), // Rule ID 1255 //
     /* 62957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 62960 */     // (mulhs:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)  =>  (MUH_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
     /* 62960 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MUH_MMR6),
     /* 62965 */     GIR_RootConstrainSelectedInstOperands,
     /* 62966 */     // GIR_Coverage, 1255,
     /* 62966 */     GIR_Done,
     /* 62967 */   // Label 1475: @62967
     /* 62967 */   GIM_Reject,
     /* 62968 */ // Label 1473: @62968
     /* 62968 */ GIM_Reject,
     /* 62969 */ // Label 1471: @62969
     /* 62969 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(63002), // Rule ID 420 //
     /* 62974 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /* 62977 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 62980 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 62983 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62987 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62991 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 62995 */   // (mulhs:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)  =>  (DMUH:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
     /* 62995 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DMUH),
     /* 63000 */   GIR_RootConstrainSelectedInstOperands,
     /* 63001 */   // GIR_Coverage, 420,
     /* 63001 */   GIR_Done,
     /* 63002 */ // Label 1476: @63002
     /* 63002 */ GIM_Reject,
     /* 63003 */ // Label 1472: @63003
     /* 63003 */ GIM_Reject,
     /* 63004 */ // Label 46: @63004
     /* 63004 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1481*/ GIMT_Encode4(64298),
     /* 63015 */ /*GILLT_s32*//*Label 1477*/ GIMT_Encode4(63039),
     /* 63019 */ /*GILLT_s64*//*Label 1478*/ GIMT_Encode4(63365), GIMT_Encode4(0),
     /* 63027 */ /*GILLT_v2s64*//*Label 1479*/ GIMT_Encode4(63990), GIMT_Encode4(0),
     /* 63035 */ /*GILLT_v4s32*//*Label 1480*/ GIMT_Encode4(64144),
     /* 63039 */ // Label 1477: @63039
     /* 63039 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(63364),
     /* 63044 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 63047 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 63050 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63054 */   GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(63111), // Rule ID 181 //
     /* 63059 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63062 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63066 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63070 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 63074 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 63078 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63083 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63088 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63092 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63094 */     // (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63094 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 63097 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63099 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63101 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63105 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63109 */     GIR_RootConstrainSelectedInstOperands,
     /* 63110 */     // GIR_Coverage, 181,
     /* 63110 */     GIR_EraseRootFromParent_Done,
     /* 63111 */   // Label 1483: @63111
     /* 63111 */   GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(63168), // Rule ID 180 //
     /* 63116 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63119 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63123 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63127 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 63131 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 63135 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63140 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63145 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63149 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63151 */     // (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63151 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 63154 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63156 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63166 */     GIR_RootConstrainSelectedInstOperands,
     /* 63167 */     // GIR_Coverage, 180,
     /* 63167 */     GIR_EraseRootFromParent_Done,
     /* 63168 */   // Label 1484: @63168
     /* 63168 */   GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(63225), // Rule ID 2490 //
     /* 63173 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63176 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63180 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63184 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63188 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 63192 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 63196 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63201 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63206 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63208 */     // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63208 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 63211 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63213 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63223 */     GIR_RootConstrainSelectedInstOperands,
     /* 63224 */     // GIR_Coverage, 2490,
     /* 63224 */     GIR_EraseRootFromParent_Done,
     /* 63225 */   // Label 1485: @63225
     /* 63225 */   GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(63282), // Rule ID 2489 //
     /* 63230 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63233 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 63249 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 63253 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63258 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63263 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63265 */     // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63265 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 63268 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63270 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63272 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63276 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63280 */     GIR_RootConstrainSelectedInstOperands,
     /* 63281 */     // GIR_Coverage, 2489,
     /* 63281 */     GIR_EraseRootFromParent_Done,
     /* 63282 */   // Label 1486: @63282
     /* 63282 */   GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(63309), // Rule ID 155 //
     /* 63287 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 63290 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63294 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63298 */     // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63298 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
     /* 63303 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63307 */     GIR_RootConstrainSelectedInstOperands,
     /* 63308 */     // GIR_Coverage, 155,
     /* 63308 */     GIR_Done,
     /* 63309 */   // Label 1487: @63309
     /* 63309 */   GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(63336), // Rule ID 1205 //
     /* 63314 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 63317 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63321 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63325 */     // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 63325 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MM),
     /* 63330 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63334 */     GIR_RootConstrainSelectedInstOperands,
     /* 63335 */     // GIR_Coverage, 1205,
     /* 63335 */     GIR_Done,
     /* 63336 */   // Label 1488: @63336
     /* 63336 */   GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(63363), // Rule ID 1263 //
     /* 63341 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 63344 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63348 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 63352 */     // (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
     /* 63352 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FADD_S_MMR6),
     /* 63355 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63357 */     GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 63359 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /* 63361 */     GIR_RootConstrainSelectedInstOperands,
     /* 63362 */     // GIR_Coverage, 1263,
     /* 63362 */     GIR_EraseRootFromParent_Done,
     /* 63363 */   // Label 1489: @63363
     /* 63363 */   GIM_Reject,
     /* 63364 */ // Label 1482: @63364
     /* 63364 */ GIM_Reject,
     /* 63365 */ // Label 1478: @63365
     /* 63365 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(63989),
     /* 63370 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 63373 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 63376 */   GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(63437), // Rule ID 189 //
     /* 63381 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63384 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63388 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63392 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63396 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63400 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63404 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63409 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63414 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63418 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63420 */     // (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63420 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 63423 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63425 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63427 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63431 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63435 */     GIR_RootConstrainSelectedInstOperands,
     /* 63436 */     // GIR_Coverage, 189,
     /* 63436 */     GIR_EraseRootFromParent_Done,
     /* 63437 */   // Label 1491: @63437
     /* 63437 */   GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(63498), // Rule ID 197 //
     /* 63442 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63445 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63449 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63453 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63457 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63461 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63465 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63470 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63479 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63481 */     // (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63481 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 63484 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63486 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63488 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63492 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63496 */     GIR_RootConstrainSelectedInstOperands,
     /* 63497 */     // GIR_Coverage, 197,
     /* 63497 */     GIR_EraseRootFromParent_Done,
     /* 63498 */   // Label 1492: @63498
     /* 63498 */   GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(63559), // Rule ID 188 //
     /* 63503 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63506 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63510 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63514 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63518 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63522 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63526 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63531 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63540 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63542 */     // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 63545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63547 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63549 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63553 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63557 */     GIR_RootConstrainSelectedInstOperands,
     /* 63558 */     // GIR_Coverage, 188,
     /* 63558 */     GIR_EraseRootFromParent_Done,
     /* 63559 */   // Label 1493: @63559
     /* 63559 */   GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(63620), // Rule ID 196 //
     /* 63564 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63567 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63571 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 63575 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63579 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63583 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63587 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63592 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63597 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63601 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63603 */     // (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63603 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 63606 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63608 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 63610 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63614 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63618 */     GIR_RootConstrainSelectedInstOperands,
     /* 63619 */     // GIR_Coverage, 196,
     /* 63619 */     GIR_EraseRootFromParent_Done,
     /* 63620 */   // Label 1494: @63620
     /* 63620 */   GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(63681), // Rule ID 2494 //
     /* 63625 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63628 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63632 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63636 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63640 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63644 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63648 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63652 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63657 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63662 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63664 */     // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63664 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 63667 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63669 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63679 */     GIR_RootConstrainSelectedInstOperands,
     /* 63680 */     // GIR_Coverage, 2494,
     /* 63680 */     GIR_EraseRootFromParent_Done,
     /* 63681 */   // Label 1495: @63681
     /* 63681 */   GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(63742), // Rule ID 2498 //
     /* 63686 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63689 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63693 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63697 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63701 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 63705 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63709 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63713 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63718 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63723 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63725 */     // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63725 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 63728 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63730 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63732 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63736 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63740 */     GIR_RootConstrainSelectedInstOperands,
     /* 63741 */     // GIR_Coverage, 2498,
     /* 63741 */     GIR_EraseRootFromParent_Done,
     /* 63742 */   // Label 1496: @63742
     /* 63742 */   GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(63803), // Rule ID 2493 //
     /* 63747 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63750 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63754 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63758 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63762 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63766 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63770 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63774 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63779 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63784 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63786 */     // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63786 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 63789 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63791 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63793 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63797 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63801 */     GIR_RootConstrainSelectedInstOperands,
     /* 63802 */     // GIR_Coverage, 2493,
     /* 63802 */     GIR_EraseRootFromParent_Done,
     /* 63803 */   // Label 1497: @63803
     /* 63803 */   GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(63864), // Rule ID 2497 //
     /* 63808 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 63811 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63815 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63819 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 63823 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 63827 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 63831 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 63835 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63840 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63845 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 63847 */     // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63847 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 63850 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 63852 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 63854 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 63858 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 63862 */     GIR_RootConstrainSelectedInstOperands,
     /* 63863 */     // GIR_Coverage, 2497,
     /* 63863 */     GIR_EraseRootFromParent_Done,
     /* 63864 */   // Label 1498: @63864
     /* 63864 */   GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(63895), // Rule ID 157 //
     /* 63869 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 63872 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63876 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63880 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63884 */     // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63884 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
     /* 63889 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63893 */     GIR_RootConstrainSelectedInstOperands,
     /* 63894 */     // GIR_Coverage, 157,
     /* 63894 */     GIR_Done,
     /* 63895 */   // Label 1499: @63895
     /* 63895 */   GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(63926), // Rule ID 159 //
     /* 63900 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 63903 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63907 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63911 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63915 */     // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63915 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
     /* 63920 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63924 */     GIR_RootConstrainSelectedInstOperands,
     /* 63925 */     // GIR_Coverage, 159,
     /* 63925 */     GIR_Done,
     /* 63926 */   // Label 1500: @63926
     /* 63926 */   GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(63957), // Rule ID 1209 //
     /* 63931 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 63934 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63938 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63942 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 63946 */     // (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 63946 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32_MM),
     /* 63951 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63955 */     GIR_RootConstrainSelectedInstOperands,
     /* 63956 */     // GIR_Coverage, 1209,
     /* 63956 */     GIR_Done,
     /* 63957 */   // Label 1501: @63957
     /* 63957 */   GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(63988), // Rule ID 1210 //
     /* 63962 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 63965 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63969 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63973 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 63977 */     // (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 63977 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64_MM),
     /* 63982 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 63986 */     GIR_RootConstrainSelectedInstOperands,
     /* 63987 */     // GIR_Coverage, 1210,
     /* 63987 */     GIR_Done,
     /* 63988 */   // Label 1502: @63988
     /* 63988 */   GIM_Reject,
     /* 63989 */ // Label 1490: @63989
     /* 63989 */ GIM_Reject,
     /* 63990 */ // Label 1479: @63990
     /* 63990 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(64143),
     /* 63995 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 63998 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 64001 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64005 */   GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(64062), // Rule ID 2633 //
     /* 64010 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 64013 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64017 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64021 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 64025 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 64029 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64034 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64039 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64043 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64045 */     // (fadd:{ *:[v2f64] } (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$wd)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 64045 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
     /* 64048 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 64050 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd
     /* 64052 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 64056 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 64060 */     GIR_RootConstrainSelectedInstOperands,
     /* 64061 */     // GIR_Coverage, 2633,
     /* 64061 */     GIR_EraseRootFromParent_Done,
     /* 64062 */   // Label 1504: @64062
     /* 64062 */   GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(64119), // Rule ID 2120 //
     /* 64067 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 64070 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64074 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 64078 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64082 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 64086 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 64090 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64095 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64100 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64102 */     // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 64102 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
     /* 64105 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 64107 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd
     /* 64109 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 64113 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 64117 */     GIR_RootConstrainSelectedInstOperands,
     /* 64118 */     // GIR_Coverage, 2120,
     /* 64118 */     GIR_EraseRootFromParent_Done,
     /* 64119 */   // Label 1505: @64119
     /* 64119 */   GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(64142), // Rule ID 746 //
     /* 64124 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 64127 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64131 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64135 */     // (fadd:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 64135 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D),
     /* 64140 */     GIR_RootConstrainSelectedInstOperands,
     /* 64141 */     // GIR_Coverage, 746,
     /* 64141 */     GIR_Done,
     /* 64142 */   // Label 1506: @64142
     /* 64142 */   GIM_Reject,
     /* 64143 */ // Label 1503: @64143
     /* 64143 */ GIM_Reject,
     /* 64144 */ // Label 1480: @64144
     /* 64144 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(64297),
     /* 64149 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 64152 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 64155 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64159 */   GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(64216), // Rule ID 2632 //
     /* 64164 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 64167 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64171 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64175 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 64179 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 64183 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64188 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64193 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64197 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64199 */     // (fadd:{ *:[v4f32] } (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$wd)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 64199 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
     /* 64202 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 64204 */     GIR_RootToRootCopy, /*OpIdx*/2, // wd
     /* 64206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 64210 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 64214 */     GIR_RootConstrainSelectedInstOperands,
     /* 64215 */     // GIR_Coverage, 2632,
     /* 64215 */     GIR_EraseRootFromParent_Done,
     /* 64216 */   // Label 1508: @64216
     /* 64216 */   GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(64273), // Rule ID 2119 //
     /* 64221 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 64224 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64228 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 64232 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64236 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 64240 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 64244 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64249 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64254 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64256 */     // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 64256 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
     /* 64259 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 64261 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd
     /* 64263 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 64267 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 64271 */     GIR_RootConstrainSelectedInstOperands,
     /* 64272 */     // GIR_Coverage, 2119,
     /* 64272 */     GIR_EraseRootFromParent_Done,
     /* 64273 */   // Label 1509: @64273
     /* 64273 */   GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(64296), // Rule ID 745 //
     /* 64278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 64281 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64285 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 64289 */     // (fadd:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 64289 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_W),
     /* 64294 */     GIR_RootConstrainSelectedInstOperands,
     /* 64295 */     // GIR_Coverage, 745,
     /* 64295 */     GIR_Done,
     /* 64296 */   // Label 1510: @64296
     /* 64296 */   GIM_Reject,
     /* 64297 */ // Label 1507: @64297
     /* 64297 */ GIM_Reject,
     /* 64298 */ // Label 1481: @64298
     /* 64298 */ GIM_Reject,
     /* 64299 */ // Label 47: @64299
     /* 64299 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1515*/ GIMT_Encode4(65113),
     /* 64310 */ /*GILLT_s32*//*Label 1511*/ GIMT_Encode4(64334),
     /* 64314 */ /*GILLT_s64*//*Label 1512*/ GIMT_Encode4(64546), GIMT_Encode4(0),
     /* 64322 */ /*GILLT_v2s64*//*Label 1513*/ GIMT_Encode4(64927), GIMT_Encode4(0),
     /* 64330 */ /*GILLT_v4s32*//*Label 1514*/ GIMT_Encode4(65020),
     /* 64334 */ // Label 1511: @64334
     /* 64334 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(64545),
     /* 64339 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 64342 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 64345 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64349 */   GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(64406), // Rule ID 185 //
     /* 64354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64357 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64361 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64365 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 64369 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 64373 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64378 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64383 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64387 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64389 */     // (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 64389 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
     /* 64392 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64394 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64396 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64400 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64404 */     GIR_RootConstrainSelectedInstOperands,
     /* 64405 */     // GIR_Coverage, 185,
     /* 64405 */     GIR_EraseRootFromParent_Done,
     /* 64406 */   // Label 1517: @64406
     /* 64406 */   GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(64463), // Rule ID 184 //
     /* 64411 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64414 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64418 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 64422 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 64426 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 64430 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64435 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64440 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64444 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64446 */     // (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 64446 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
     /* 64449 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64451 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64453 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64457 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64461 */     GIR_RootConstrainSelectedInstOperands,
     /* 64462 */     // GIR_Coverage, 184,
     /* 64462 */     GIR_EraseRootFromParent_Done,
     /* 64463 */   // Label 1518: @64463
     /* 64463 */   GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(64490), // Rule ID 173 //
     /* 64468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 64471 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64475 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64479 */     // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 64479 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
     /* 64484 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64488 */     GIR_RootConstrainSelectedInstOperands,
     /* 64489 */     // GIR_Coverage, 173,
     /* 64489 */     GIR_Done,
     /* 64490 */   // Label 1519: @64490
     /* 64490 */   GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(64517), // Rule ID 1208 //
     /* 64495 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 64498 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64502 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64506 */     // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 64506 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MM),
     /* 64511 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64515 */     GIR_RootConstrainSelectedInstOperands,
     /* 64516 */     // GIR_Coverage, 1208,
     /* 64516 */     GIR_Done,
     /* 64517 */   // Label 1520: @64517
     /* 64517 */   GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(64544), // Rule ID 1264 //
     /* 64522 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 64525 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64529 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 64533 */     // (fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
     /* 64533 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FSUB_S_MMR6),
     /* 64536 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64538 */     GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 64540 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /* 64542 */     GIR_RootConstrainSelectedInstOperands,
     /* 64543 */     // GIR_Coverage, 1264,
     /* 64543 */     GIR_EraseRootFromParent_Done,
     /* 64544 */   // Label 1521: @64544
     /* 64544 */   GIM_Reject,
     /* 64545 */ // Label 1516: @64545
     /* 64545 */ GIM_Reject,
     /* 64546 */ // Label 1512: @64546
     /* 64546 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(64926),
     /* 64551 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 64554 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 64557 */   GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(64618), // Rule ID 193 //
     /* 64562 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64565 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64569 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64573 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64577 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 64581 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 64585 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64590 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64595 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64599 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64601 */     // (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 64601 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
     /* 64604 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64606 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64608 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64612 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64616 */     GIR_RootConstrainSelectedInstOperands,
     /* 64617 */     // GIR_Coverage, 193,
     /* 64617 */     GIR_EraseRootFromParent_Done,
     /* 64618 */   // Label 1523: @64618
     /* 64618 */   GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(64679), // Rule ID 201 //
     /* 64623 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64626 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64630 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64634 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64638 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 64642 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 64646 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64651 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64656 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64660 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64662 */     // (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 64662 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
     /* 64665 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64667 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64669 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64673 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64677 */     GIR_RootConstrainSelectedInstOperands,
     /* 64678 */     // GIR_Coverage, 201,
     /* 64678 */     GIR_EraseRootFromParent_Done,
     /* 64679 */   // Label 1524: @64679
     /* 64679 */   GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(64740), // Rule ID 192 //
     /* 64684 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64691 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64695 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 64699 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 64703 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 64707 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64712 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64717 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64721 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64723 */     // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 64723 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
     /* 64726 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64728 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64730 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64734 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64738 */     GIR_RootConstrainSelectedInstOperands,
     /* 64739 */     // GIR_Coverage, 192,
     /* 64739 */     GIR_EraseRootFromParent_Done,
     /* 64740 */   // Label 1525: @64740
     /* 64740 */   GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(64801), // Rule ID 200 //
     /* 64745 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 64748 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64752 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 64756 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 64760 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 64764 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 64768 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64773 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64778 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64782 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64784 */     // (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 64784 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
     /* 64787 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 64789 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 64791 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 64795 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 64799 */     GIR_RootConstrainSelectedInstOperands,
     /* 64800 */     // GIR_Coverage, 200,
     /* 64800 */     GIR_EraseRootFromParent_Done,
     /* 64801 */   // Label 1526: @64801
     /* 64801 */   GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(64832), // Rule ID 175 //
     /* 64806 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 64809 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64813 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64817 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64821 */     // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 64821 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
     /* 64826 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64830 */     GIR_RootConstrainSelectedInstOperands,
     /* 64831 */     // GIR_Coverage, 175,
     /* 64831 */     GIR_Done,
     /* 64832 */   // Label 1527: @64832
     /* 64832 */   GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(64863), // Rule ID 177 //
     /* 64837 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 64840 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64844 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64848 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64852 */     // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 64852 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
     /* 64857 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64861 */     GIR_RootConstrainSelectedInstOperands,
     /* 64862 */     // GIR_Coverage, 177,
     /* 64862 */     GIR_Done,
     /* 64863 */   // Label 1528: @64863
     /* 64863 */   GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(64894), // Rule ID 1215 //
     /* 64868 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 64871 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64875 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64879 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 64883 */     // (fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 64883 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32_MM),
     /* 64888 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64892 */     GIR_RootConstrainSelectedInstOperands,
     /* 64893 */     // GIR_Coverage, 1215,
     /* 64893 */     GIR_Done,
     /* 64894 */   // Label 1529: @64894
     /* 64894 */   GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(64925), // Rule ID 1216 //
     /* 64899 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 64902 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64906 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64910 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 64914 */     // (fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 64914 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64_MM),
     /* 64919 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 64923 */     GIR_RootConstrainSelectedInstOperands,
     /* 64924 */     // GIR_Coverage, 1216,
     /* 64924 */     GIR_Done,
     /* 64925 */   // Label 1530: @64925
     /* 64925 */   GIM_Reject,
     /* 64926 */ // Label 1522: @64926
     /* 64926 */ GIM_Reject,
     /* 64927 */ // Label 1513: @64927
     /* 64927 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(65019),
     /* 64932 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 64935 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 64938 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64942 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64946 */   GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(64999), // Rule ID 2118 //
     /* 64951 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 64954 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 64958 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 64962 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 64966 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 64970 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64975 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 64980 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 64982 */     // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FMSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 64982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_D),
     /* 64985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 64987 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd
     /* 64989 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 64993 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 64997 */     GIR_RootConstrainSelectedInstOperands,
     /* 64998 */     // GIR_Coverage, 2118,
     /* 64998 */     GIR_EraseRootFromParent_Done,
     /* 64999 */   // Label 1532: @64999
     /* 64999 */   GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(65018), // Rule ID 834 //
     /* 65004 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65007 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65011 */     // (fsub:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FSUB_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 65011 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D),
     /* 65016 */     GIR_RootConstrainSelectedInstOperands,
     /* 65017 */     // GIR_Coverage, 834,
     /* 65017 */     GIR_Done,
     /* 65018 */   // Label 1533: @65018
     /* 65018 */   GIM_Reject,
     /* 65019 */ // Label 1531: @65019
     /* 65019 */ GIM_Reject,
     /* 65020 */ // Label 1514: @65020
     /* 65020 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(65112),
     /* 65025 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65028 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 65031 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65035 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65039 */   GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(65092), // Rule ID 2117 //
     /* 65044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc),
     /* 65047 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 65051 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 65055 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65059 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 65063 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65068 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65073 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 65075 */     // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FMSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65075 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMSUB_W),
     /* 65078 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 65080 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd
     /* 65082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
     /* 65086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
     /* 65090 */     GIR_RootConstrainSelectedInstOperands,
     /* 65091 */     // GIR_Coverage, 2117,
     /* 65091 */     GIR_EraseRootFromParent_Done,
     /* 65092 */   // Label 1535: @65092
     /* 65092 */   GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(65111), // Rule ID 833 //
     /* 65097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65100 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65104 */     // (fsub:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FSUB_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65104 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_W),
     /* 65109 */     GIR_RootConstrainSelectedInstOperands,
     /* 65110 */     // GIR_Coverage, 833,
     /* 65110 */     GIR_Done,
     /* 65111 */   // Label 1536: @65111
     /* 65111 */   GIM_Reject,
     /* 65112 */ // Label 1534: @65112
     /* 65112 */ GIM_Reject,
     /* 65113 */ // Label 1515: @65113
     /* 65113 */ GIM_Reject,
     /* 65114 */ // Label 48: @65114
     /* 65114 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1541*/ GIMT_Encode4(65624),
     /* 65125 */ /*GILLT_s32*//*Label 1537*/ GIMT_Encode4(65149),
     /* 65129 */ /*GILLT_s64*//*Label 1538*/ GIMT_Encode4(65231), GIMT_Encode4(0),
     /* 65137 */ /*GILLT_v2s64*//*Label 1539*/ GIMT_Encode4(65368), GIMT_Encode4(0),
     /* 65145 */ /*GILLT_v4s32*//*Label 1540*/ GIMT_Encode4(65496),
     /* 65149 */ // Label 1537: @65149
     /* 65149 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(65230),
     /* 65154 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 65157 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 65160 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65164 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65168 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65172 */   GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(65191), // Rule ID 167 //
     /* 65177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 65180 */     // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 65180 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
     /* 65185 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65189 */     GIR_RootConstrainSelectedInstOperands,
     /* 65190 */     // GIR_Coverage, 167,
     /* 65190 */     GIR_Done,
     /* 65191 */   // Label 1543: @65191
     /* 65191 */   GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(65210), // Rule ID 1207 //
     /* 65196 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 65199 */     // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 65199 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MM),
     /* 65204 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65208 */     GIR_RootConstrainSelectedInstOperands,
     /* 65209 */     // GIR_Coverage, 1207,
     /* 65209 */     GIR_Done,
     /* 65210 */   // Label 1544: @65210
     /* 65210 */   GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(65229), // Rule ID 1265 //
     /* 65215 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 65218 */     // (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
     /* 65218 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FMUL_S_MMR6),
     /* 65221 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 65223 */     GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 65225 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /* 65227 */     GIR_RootConstrainSelectedInstOperands,
     /* 65228 */     // GIR_Coverage, 1265,
     /* 65228 */     GIR_EraseRootFromParent_Done,
     /* 65229 */   // Label 1545: @65229
     /* 65229 */   GIM_Reject,
     /* 65230 */ // Label 1542: @65230
     /* 65230 */ GIM_Reject,
     /* 65231 */ // Label 1538: @65231
     /* 65231 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(65367),
     /* 65236 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 65239 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 65242 */   GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(65273), // Rule ID 169 //
     /* 65247 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 65250 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65254 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65258 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65262 */     // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 65262 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
     /* 65267 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65271 */     GIR_RootConstrainSelectedInstOperands,
     /* 65272 */     // GIR_Coverage, 169,
     /* 65272 */     GIR_Done,
     /* 65273 */   // Label 1547: @65273
     /* 65273 */   GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(65304), // Rule ID 171 //
     /* 65278 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 65281 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65285 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65289 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65293 */     // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 65293 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
     /* 65298 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65302 */     GIR_RootConstrainSelectedInstOperands,
     /* 65303 */     // GIR_Coverage, 171,
     /* 65303 */     GIR_Done,
     /* 65304 */   // Label 1548: @65304
     /* 65304 */   GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(65335), // Rule ID 1213 //
     /* 65309 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 65312 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65316 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65320 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65324 */     // (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 65324 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32_MM),
     /* 65329 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65333 */     GIR_RootConstrainSelectedInstOperands,
     /* 65334 */     // GIR_Coverage, 1213,
     /* 65334 */     GIR_Done,
     /* 65335 */   // Label 1549: @65335
     /* 65335 */   GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(65366), // Rule ID 1214 //
     /* 65340 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 65343 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65347 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65351 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65355 */     // (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 65355 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64_MM),
     /* 65360 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65364 */     GIR_RootConstrainSelectedInstOperands,
     /* 65365 */     // GIR_Coverage, 1214,
     /* 65365 */     GIR_Done,
     /* 65366 */   // Label 1550: @65366
     /* 65366 */   GIM_Reject,
     /* 65367 */ // Label 1546: @65367
     /* 65367 */ GIM_Reject,
     /* 65368 */ // Label 1539: @65368
     /* 65368 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(65495),
     /* 65373 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 65376 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 65379 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65383 */   GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(65427), // Rule ID 2560 //
     /* 65388 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 65395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
     /* 65399 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 65403 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65408 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65412 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 65414 */     // (fmul:{ *:[v2f64] } (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt), MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 65414 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
     /* 65417 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 65419 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 65421 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 65425 */     GIR_RootConstrainSelectedInstOperands,
     /* 65426 */     // GIR_Coverage, 2560,
     /* 65426 */     GIR_EraseRootFromParent_Done,
     /* 65427 */   // Label 1552: @65427
     /* 65427 */   GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(65471), // Rule ID 776 //
     /* 65432 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65435 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65439 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 65443 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
     /* 65447 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 65451 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65456 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 65458 */     // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, (fexp2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wt))  =>  (FEXP2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 65458 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D),
     /* 65461 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 65463 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 65465 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 65469 */     GIR_RootConstrainSelectedInstOperands,
     /* 65470 */     // GIR_Coverage, 776,
     /* 65470 */     GIR_EraseRootFromParent_Done,
     /* 65471 */   // Label 1553: @65471
     /* 65471 */   GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(65494), // Rule ID 812 //
     /* 65476 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65479 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65483 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65487 */     // (fmul:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMUL_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 65487 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D),
     /* 65492 */     GIR_RootConstrainSelectedInstOperands,
     /* 65493 */     // GIR_Coverage, 812,
     /* 65493 */     GIR_Done,
     /* 65494 */   // Label 1554: @65494
     /* 65494 */   GIM_Reject,
     /* 65495 */ // Label 1551: @65495
     /* 65495 */ GIM_Reject,
     /* 65496 */ // Label 1540: @65496
     /* 65496 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(65623),
     /* 65501 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65504 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 65507 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65511 */   GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(65555), // Rule ID 2559 //
     /* 65516 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65519 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 65523 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
     /* 65527 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65531 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65536 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65540 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 65542 */     // (fmul:{ *:[v4f32] } (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt), MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65542 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
     /* 65545 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 65547 */     GIR_RootToRootCopy, /*OpIdx*/2, // ws
     /* 65549 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 65553 */     GIR_RootConstrainSelectedInstOperands,
     /* 65554 */     // GIR_Coverage, 2559,
     /* 65554 */     GIR_EraseRootFromParent_Done,
     /* 65555 */   // Label 1556: @65555
     /* 65555 */   GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(65599), // Rule ID 775 //
     /* 65560 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65563 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65567 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 65571 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FEXP2),
     /* 65575 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65579 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65584 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 65586 */     // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, (fexp2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wt))  =>  (FEXP2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65586 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W),
     /* 65589 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 65591 */     GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 65593 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // wt
     /* 65597 */     GIR_RootConstrainSelectedInstOperands,
     /* 65598 */     // GIR_Coverage, 775,
     /* 65598 */     GIR_EraseRootFromParent_Done,
     /* 65599 */   // Label 1557: @65599
     /* 65599 */   GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(65622), // Rule ID 811 //
     /* 65604 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65607 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65611 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65615 */     // (fmul:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMUL_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65615 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_W),
     /* 65620 */     GIR_RootConstrainSelectedInstOperands,
     /* 65621 */     // GIR_Coverage, 811,
     /* 65621 */     GIR_Done,
     /* 65622 */   // Label 1558: @65622
     /* 65622 */   GIM_Reject,
     /* 65623 */ // Label 1555: @65623
     /* 65623 */ GIM_Reject,
     /* 65624 */ // Label 1541: @65624
     /* 65624 */ GIM_Reject,
     /* 65625 */ // Label 49: @65625
     /* 65625 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1561*/ GIMT_Encode4(65730),
     /* 65636 */ /*GILLT_v2s64*//*Label 1559*/ GIMT_Encode4(65648), GIMT_Encode4(0),
     /* 65644 */ /*GILLT_v4s32*//*Label 1560*/ GIMT_Encode4(65689),
     /* 65648 */ // Label 1559: @65648
     /* 65648 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(65688), // Rule ID 800 //
     /* 65653 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65656 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 65659 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 65662 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
     /* 65665 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65669 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65673 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65677 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 65681 */   // (fma:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FMADD_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 65681 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_D),
     /* 65686 */   GIR_RootConstrainSelectedInstOperands,
     /* 65687 */   // GIR_Coverage, 800,
     /* 65687 */   GIR_Done,
     /* 65688 */ // Label 1562: @65688
     /* 65688 */ GIM_Reject,
     /* 65689 */ // Label 1560: @65689
     /* 65689 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(65729), // Rule ID 799 //
     /* 65694 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65697 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 65700 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 65703 */   GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
     /* 65706 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65710 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65714 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65718 */   GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 65722 */   // (fma:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FMADD_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 65722 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMADD_W),
     /* 65727 */   GIR_RootConstrainSelectedInstOperands,
     /* 65728 */   // GIR_Coverage, 799,
     /* 65728 */   GIR_Done,
     /* 65729 */ // Label 1563: @65729
     /* 65729 */ GIM_Reject,
     /* 65730 */ // Label 1561: @65730
     /* 65730 */ GIM_Reject,
     /* 65731 */ // Label 50: @65731
     /* 65731 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1568*/ GIMT_Encode4(66053),
     /* 65742 */ /*GILLT_s32*//*Label 1564*/ GIMT_Encode4(65766),
     /* 65746 */ /*GILLT_s64*//*Label 1565*/ GIMT_Encode4(65848), GIMT_Encode4(0),
     /* 65754 */ /*GILLT_v2s64*//*Label 1566*/ GIMT_Encode4(65985), GIMT_Encode4(0),
     /* 65762 */ /*GILLT_v4s32*//*Label 1567*/ GIMT_Encode4(66019),
     /* 65766 */ // Label 1564: @65766
     /* 65766 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(65847),
     /* 65771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 65774 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 65777 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65781 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65785 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 65789 */   GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(65808), // Rule ID 161 //
     /* 65794 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 65797 */     // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 65797 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
     /* 65802 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65806 */     GIR_RootConstrainSelectedInstOperands,
     /* 65807 */     // GIR_Coverage, 161,
     /* 65807 */     GIR_Done,
     /* 65808 */   // Label 1570: @65808
     /* 65808 */   GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(65827), // Rule ID 1206 //
     /* 65813 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 65816 */     // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 65816 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MM),
     /* 65821 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65825 */     GIR_RootConstrainSelectedInstOperands,
     /* 65826 */     // GIR_Coverage, 1206,
     /* 65826 */     GIR_Done,
     /* 65827 */   // Label 1571: @65827
     /* 65827 */   GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(65846), // Rule ID 1266 //
     /* 65832 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 65835 */     // (fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$ft, FGR32Opnd:{ *:[f32] }:$fs)
     /* 65835 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::FDIV_S_MMR6),
     /* 65838 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 65840 */     GIR_RootToRootCopy, /*OpIdx*/2, // ft
     /* 65842 */     GIR_RootToRootCopy, /*OpIdx*/1, // fs
     /* 65844 */     GIR_RootConstrainSelectedInstOperands,
     /* 65845 */     // GIR_Coverage, 1266,
     /* 65845 */     GIR_EraseRootFromParent_Done,
     /* 65846 */   // Label 1572: @65846
     /* 65846 */   GIM_Reject,
     /* 65847 */ // Label 1569: @65847
     /* 65847 */ GIM_Reject,
     /* 65848 */ // Label 1565: @65848
     /* 65848 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(65984),
     /* 65853 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 65856 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 65859 */   GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(65890), // Rule ID 163 //
     /* 65864 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 65867 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65871 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65875 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65879 */     // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 65879 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
     /* 65884 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65888 */     GIR_RootConstrainSelectedInstOperands,
     /* 65889 */     // GIR_Coverage, 163,
     /* 65889 */     GIR_Done,
     /* 65890 */   // Label 1574: @65890
     /* 65890 */   GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(65921), // Rule ID 165 //
     /* 65895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 65898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65902 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65906 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65910 */     // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 65910 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
     /* 65915 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65919 */     GIR_RootConstrainSelectedInstOperands,
     /* 65920 */     // GIR_Coverage, 165,
     /* 65920 */     GIR_Done,
     /* 65921 */   // Label 1575: @65921
     /* 65921 */   GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(65952), // Rule ID 1211 //
     /* 65926 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 65929 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65933 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65937 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 65941 */     // (fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 65941 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32_MM),
     /* 65946 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65950 */     GIR_RootConstrainSelectedInstOperands,
     /* 65951 */     // GIR_Coverage, 1211,
     /* 65951 */     GIR_Done,
     /* 65952 */   // Label 1576: @65952
     /* 65952 */   GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(65983), // Rule ID 1212 //
     /* 65957 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 65960 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65964 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65968 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 65972 */     // (fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 65972 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64_MM),
     /* 65977 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 65981 */     GIR_RootConstrainSelectedInstOperands,
     /* 65982 */     // GIR_Coverage, 1212,
     /* 65982 */     GIR_Done,
     /* 65983 */   // Label 1577: @65983
     /* 65983 */   GIM_Reject,
     /* 65984 */ // Label 1573: @65984
     /* 65984 */ GIM_Reject,
     /* 65985 */ // Label 1566: @65985
     /* 65985 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(66018), // Rule ID 772 //
     /* 65990 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 65993 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 65996 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 65999 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66003 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66007 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66011 */   // (fdiv:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)  =>  (FDIV_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws, MSA128DOpnd:{ *:[v2f64] }:$wt)
     /* 66011 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D),
     /* 66016 */   GIR_RootConstrainSelectedInstOperands,
     /* 66017 */   // GIR_Coverage, 772,
     /* 66017 */   GIR_Done,
     /* 66018 */ // Label 1578: @66018
     /* 66018 */ GIM_Reject,
     /* 66019 */ // Label 1567: @66019
     /* 66019 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(66052), // Rule ID 771 //
     /* 66024 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 66027 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 66030 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 66033 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66037 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66041 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66045 */   // (fdiv:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)  =>  (FDIV_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws, MSA128WOpnd:{ *:[v4f32] }:$wt)
     /* 66045 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_W),
     /* 66050 */   GIR_RootConstrainSelectedInstOperands,
     /* 66051 */   // GIR_Coverage, 771,
     /* 66051 */   GIR_Done,
     /* 66052 */ // Label 1579: @66052
     /* 66052 */ GIM_Reject,
     /* 66053 */ // Label 1568: @66053
     /* 66053 */ GIM_Reject,
     /* 66054 */ // Label 51: @66054
     /* 66054 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(66131),
     /* 66065 */ /*GILLT_v2s64*//*Label 1580*/ GIMT_Encode4(66077), GIMT_Encode4(0),
     /* 66073 */ /*GILLT_v4s32*//*Label 1581*/ GIMT_Encode4(66104),
     /* 66077 */ // Label 1580: @66077
     /* 66077 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(66103), // Rule ID 778 //
     /* 66082 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 66085 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 66088 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66092 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66096 */   // (fexp2:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)  =>  (FEXP2_D_1_PSEUDO:{ *:[v2f64] } MSA128D:{ *:[v2f64] }:$ws)
     /* 66096 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_D_1_PSEUDO),
     /* 66101 */   GIR_RootConstrainSelectedInstOperands,
     /* 66102 */   // GIR_Coverage, 778,
     /* 66102 */   GIR_Done,
     /* 66103 */ // Label 1583: @66103
     /* 66103 */ GIM_Reject,
     /* 66104 */ // Label 1581: @66104
     /* 66104 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(66130), // Rule ID 777 //
     /* 66109 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 66112 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 66115 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66119 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66123 */   // (fexp2:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)  =>  (FEXP2_W_1_PSEUDO:{ *:[v4f32] } MSA128W:{ *:[v4f32] }:$ws)
     /* 66123 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FEXP2_W_1_PSEUDO),
     /* 66128 */   GIR_RootConstrainSelectedInstOperands,
     /* 66129 */   // GIR_Coverage, 777,
     /* 66129 */   GIR_Done,
     /* 66130 */ // Label 1584: @66130
     /* 66130 */ GIM_Reject,
     /* 66131 */ // Label 1582: @66131
     /* 66131 */ GIM_Reject,
     /* 66132 */ // Label 52: @66132
     /* 66132 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1587*/ GIMT_Encode4(66209),
     /* 66143 */ /*GILLT_v2s64*//*Label 1585*/ GIMT_Encode4(66155), GIMT_Encode4(0),
     /* 66151 */ /*GILLT_v4s32*//*Label 1586*/ GIMT_Encode4(66182),
     /* 66155 */ // Label 1585: @66155
     /* 66155 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(66181), // Rule ID 798 //
     /* 66160 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 66163 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 66166 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66170 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 66174 */   // (flog2:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FLOG2_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 66174 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_D),
     /* 66179 */   GIR_RootConstrainSelectedInstOperands,
     /* 66180 */   // GIR_Coverage, 798,
     /* 66180 */   GIR_Done,
     /* 66181 */ // Label 1588: @66181
     /* 66181 */ GIM_Reject,
     /* 66182 */ // Label 1586: @66182
     /* 66182 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(66208), // Rule ID 797 //
     /* 66187 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 66190 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 66193 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66197 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 66201 */   // (flog2:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FLOG2_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 66201 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FLOG2_W),
     /* 66206 */   GIR_RootConstrainSelectedInstOperands,
     /* 66207 */   // GIR_Coverage, 797,
     /* 66207 */   GIR_Done,
     /* 66208 */ // Label 1589: @66208
     /* 66208 */ GIM_Reject,
     /* 66209 */ // Label 1587: @66209
     /* 66209 */ GIM_Reject,
     /* 66210 */ // Label 53: @66210
     /* 66210 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1592*/ GIMT_Encode4(71114),
     /* 66221 */ /*GILLT_s32*//*Label 1590*/ GIMT_Encode4(66229),
     /* 66225 */ /*GILLT_s64*//*Label 1591*/ GIMT_Encode4(68124),
     /* 66229 */ // Label 1590: @66229
     /* 66229 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(68123),
     /* 66234 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 66237 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66241 */   GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(66317), // Rule ID 1547 //
     /* 66246 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 66249 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66253 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66257 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66261 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66265 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66269 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66273 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66277 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66281 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66286 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66291 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66296 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66298 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66298 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 66301 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66303 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66307 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66311 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66315 */     GIR_RootConstrainSelectedInstOperands,
     /* 66316 */     // GIR_Coverage, 1547,
     /* 66316 */     GIR_EraseRootFromParent_Done,
     /* 66317 */   // Label 1594: @66317
     /* 66317 */   GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(66393), // Rule ID 2378 //
     /* 66322 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 66325 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66329 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66333 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66337 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66341 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66345 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66349 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66353 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66357 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66362 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66367 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66372 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66374 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66374 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 66377 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66379 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66383 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66387 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66391 */     GIR_RootConstrainSelectedInstOperands,
     /* 66392 */     // GIR_Coverage, 2378,
     /* 66392 */     GIR_EraseRootFromParent_Done,
     /* 66393 */   // Label 1595: @66393
     /* 66393 */   GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(66469), // Rule ID 1546 //
     /* 66398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 66401 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66405 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66409 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66413 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66417 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66421 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 66425 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66429 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66433 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66438 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66443 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66448 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66450 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 66453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66455 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66459 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66463 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66467 */     GIR_RootConstrainSelectedInstOperands,
     /* 66468 */     // GIR_Coverage, 1546,
     /* 66468 */     GIR_EraseRootFromParent_Done,
     /* 66469 */   // Label 1596: @66469
     /* 66469 */   GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(66545), // Rule ID 2377 //
     /* 66474 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 66477 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66481 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66485 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66489 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66493 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66497 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 66501 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66505 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66509 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66514 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66519 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66524 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66526 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66526 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 66529 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66531 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66535 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66539 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66543 */     GIR_RootConstrainSelectedInstOperands,
     /* 66544 */     // GIR_Coverage, 2377,
     /* 66544 */     GIR_EraseRootFromParent_Done,
     /* 66545 */   // Label 1597: @66545
     /* 66545 */   GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(66621), // Rule ID 2598 //
     /* 66550 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 66553 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66557 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66561 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66565 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66569 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66574 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 66578 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66582 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66586 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66590 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66595 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66600 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66602 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66602 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 66605 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66607 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 66611 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66615 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66619 */     GIR_RootConstrainSelectedInstOperands,
     /* 66620 */     // GIR_Coverage, 2598,
     /* 66620 */     GIR_EraseRootFromParent_Done,
     /* 66621 */   // Label 1598: @66621
     /* 66621 */   GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(66697), // Rule ID 2693 //
     /* 66626 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 66629 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66633 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66637 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66641 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66645 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66650 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 66654 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66658 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66662 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66666 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66671 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66676 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66678 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66678 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 66681 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66683 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 66687 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66691 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66695 */     GIR_RootConstrainSelectedInstOperands,
     /* 66696 */     // GIR_Coverage, 2693,
     /* 66696 */     GIR_EraseRootFromParent_Done,
     /* 66697 */   // Label 1599: @66697
     /* 66697 */   GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(66773), // Rule ID 2597 //
     /* 66702 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 66705 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66709 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66713 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66717 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66721 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66726 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 66730 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 66734 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66738 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66742 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66747 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66752 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66754 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66754 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 66757 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66759 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 66763 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66767 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66771 */     GIR_RootConstrainSelectedInstOperands,
     /* 66772 */     // GIR_Coverage, 2597,
     /* 66772 */     GIR_EraseRootFromParent_Done,
     /* 66773 */   // Label 1600: @66773
     /* 66773 */   GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(66849), // Rule ID 2692 //
     /* 66778 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 66781 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66785 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 66789 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66793 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66802 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 66806 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 66810 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66814 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66818 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66823 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66828 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66830 */     // (fneg:{ *:[f32] } (fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66830 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 66833 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66835 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 66839 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66843 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66847 */     GIR_RootConstrainSelectedInstOperands,
     /* 66848 */     // GIR_Coverage, 2692,
     /* 66848 */     GIR_EraseRootFromParent_Done,
     /* 66849 */   // Label 1601: @66849
     /* 66849 */   GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(66925), // Rule ID 1551 //
     /* 66854 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 66857 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66861 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 66865 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66869 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66873 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66877 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66881 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66885 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66889 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66894 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66899 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66904 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66906 */     // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66906 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
     /* 66909 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66911 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66915 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66919 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66923 */     GIR_RootConstrainSelectedInstOperands,
     /* 66924 */     // GIR_Coverage, 1551,
     /* 66924 */     GIR_EraseRootFromParent_Done,
     /* 66925 */   // Label 1602: @66925
     /* 66925 */   GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(67001), // Rule ID 2382 //
     /* 66930 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 66933 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 66937 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 66941 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 66945 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 66949 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 66953 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 66957 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 66961 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 66965 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66970 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66975 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 66980 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 66982 */     // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 66982 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
     /* 66985 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 66987 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 66991 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 66995 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 66999 */     GIR_RootConstrainSelectedInstOperands,
     /* 67000 */     // GIR_Coverage, 2382,
     /* 67000 */     GIR_EraseRootFromParent_Done,
     /* 67001 */   // Label 1603: @67001
     /* 67001 */   GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(67077), // Rule ID 1550 //
     /* 67006 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67009 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67013 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 67017 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67021 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67025 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67029 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67033 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67037 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67041 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67046 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67051 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67056 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67058 */     // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67058 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
     /* 67061 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67063 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67067 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67071 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67075 */     GIR_RootConstrainSelectedInstOperands,
     /* 67076 */     // GIR_Coverage, 1550,
     /* 67076 */     GIR_EraseRootFromParent_Done,
     /* 67077 */   // Label 1604: @67077
     /* 67077 */   GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(67153), // Rule ID 2381 //
     /* 67082 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67085 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67089 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 67093 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67097 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67101 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67105 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67109 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67113 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67117 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67122 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67132 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67134 */     // (fneg:{ *:[f32] } (fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67134 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
     /* 67137 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67139 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67143 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67147 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67151 */     GIR_RootConstrainSelectedInstOperands,
     /* 67152 */     // GIR_Coverage, 2381,
     /* 67152 */     GIR_EraseRootFromParent_Done,
     /* 67153 */   // Label 1605: @67153
     /* 67153 */   GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(67229), // Rule ID 1545 //
     /* 67158 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67161 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67165 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67169 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67173 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67177 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67181 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67185 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67189 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67193 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67198 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67203 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67208 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67210 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67210 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 67213 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67215 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67219 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67223 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67227 */     GIR_RootConstrainSelectedInstOperands,
     /* 67228 */     // GIR_Coverage, 1545,
     /* 67228 */     GIR_EraseRootFromParent_Done,
     /* 67229 */   // Label 1606: @67229
     /* 67229 */   GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(67305), // Rule ID 2376 //
     /* 67234 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67237 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67241 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67245 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67249 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67253 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67257 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67261 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67265 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67269 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67274 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67279 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67284 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67286 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67286 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 67289 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67291 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67303 */     GIR_RootConstrainSelectedInstOperands,
     /* 67304 */     // GIR_Coverage, 2376,
     /* 67304 */     GIR_EraseRootFromParent_Done,
     /* 67305 */   // Label 1607: @67305
     /* 67305 */   GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(67381), // Rule ID 1544 //
     /* 67310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67329 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67333 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67337 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67341 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67345 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67350 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67355 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67360 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67362 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 67365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67367 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67371 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67375 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67379 */     GIR_RootConstrainSelectedInstOperands,
     /* 67380 */     // GIR_Coverage, 1544,
     /* 67380 */     GIR_EraseRootFromParent_Done,
     /* 67381 */   // Label 1608: @67381
     /* 67381 */   GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(67457), // Rule ID 2375 //
     /* 67386 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67389 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67393 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67397 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67401 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67405 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67409 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67413 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67417 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67421 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67426 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67431 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67436 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67438 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67438 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 67441 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67443 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67447 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67451 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67455 */     GIR_RootConstrainSelectedInstOperands,
     /* 67456 */     // GIR_Coverage, 2375,
     /* 67456 */     GIR_EraseRootFromParent_Done,
     /* 67457 */   // Label 1609: @67457
     /* 67457 */   GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(67533), // Rule ID 2596 //
     /* 67462 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67465 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67469 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67473 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67477 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67481 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67486 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 67490 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67494 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67498 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67502 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67507 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67512 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67514 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67514 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 67517 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67519 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 67523 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67527 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67531 */     GIR_RootConstrainSelectedInstOperands,
     /* 67532 */     // GIR_Coverage, 2596,
     /* 67532 */     GIR_EraseRootFromParent_Done,
     /* 67533 */   // Label 1610: @67533
     /* 67533 */   GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(67609), // Rule ID 2691 //
     /* 67538 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67541 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67545 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67549 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67553 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67557 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67562 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 67566 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67570 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67574 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67578 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67583 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67588 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67590 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67590 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 67593 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67595 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 67599 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67603 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67607 */     GIR_RootConstrainSelectedInstOperands,
     /* 67608 */     // GIR_Coverage, 2691,
     /* 67608 */     GIR_EraseRootFromParent_Done,
     /* 67609 */   // Label 1611: @67609
     /* 67609 */   GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(67685), // Rule ID 2595 //
     /* 67614 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67617 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67621 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67625 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67629 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67633 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67638 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 67642 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67646 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67650 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67654 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67659 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67664 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67666 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67666 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S),
     /* 67669 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67671 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 67675 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67679 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67683 */     GIR_RootConstrainSelectedInstOperands,
     /* 67684 */     // GIR_Coverage, 2595,
     /* 67684 */     GIR_EraseRootFromParent_Done,
     /* 67685 */   // Label 1612: @67685
     /* 67685 */   GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(67761), // Rule ID 2690 //
     /* 67690 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67693 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67697 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 67701 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67705 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67709 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67714 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 67718 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67722 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67726 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67730 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67735 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67740 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67742 */     // (fneg:{ *:[f32] } (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)))  =>  (NMADD_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67742 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_S_MM),
     /* 67745 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67747 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 67751 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67755 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67759 */     GIR_RootConstrainSelectedInstOperands,
     /* 67760 */     // GIR_Coverage, 2690,
     /* 67760 */     GIR_EraseRootFromParent_Done,
     /* 67761 */   // Label 1613: @67761
     /* 67761 */   GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(67837), // Rule ID 1549 //
     /* 67766 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67769 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67773 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 67777 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67781 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67785 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67789 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67793 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67797 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67801 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67806 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67811 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67816 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67818 */     // (fneg:{ *:[f32] } (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67818 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
     /* 67821 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67823 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67827 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67831 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67835 */     GIR_RootConstrainSelectedInstOperands,
     /* 67836 */     // GIR_Coverage, 1549,
     /* 67836 */     GIR_EraseRootFromParent_Done,
     /* 67837 */   // Label 1614: @67837
     /* 67837 */   GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(67913), // Rule ID 2380 //
     /* 67842 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67845 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67849 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 67853 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67857 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67861 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67865 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 67869 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67873 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67877 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67882 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67887 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67892 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67894 */     // (fneg:{ *:[f32] } (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67894 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
     /* 67897 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67899 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67903 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67907 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67911 */     GIR_RootConstrainSelectedInstOperands,
     /* 67912 */     // GIR_Coverage, 2380,
     /* 67912 */     GIR_EraseRootFromParent_Done,
     /* 67913 */   // Label 1615: @67913
     /* 67913 */   GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(67989), // Rule ID 1548 //
     /* 67918 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 67921 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 67925 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 67929 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 67933 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 67937 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 67941 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 67945 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 67949 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 67953 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67958 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67963 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 67968 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 67970 */     // (fneg:{ *:[f32] } (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 67970 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S),
     /* 67973 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 67975 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 67979 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 67983 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 67987 */     GIR_RootConstrainSelectedInstOperands,
     /* 67988 */     // GIR_Coverage, 1548,
     /* 67988 */     GIR_EraseRootFromParent_Done,
     /* 67989 */   // Label 1616: @67989
     /* 67989 */   GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(68065), // Rule ID 2379 //
     /* 67994 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotMips32r6),
     /* 67997 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68001 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 68005 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 68009 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 68013 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68017 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68021 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
     /* 68025 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
     /* 68029 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68034 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68039 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68044 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68046 */     // (fneg:{ *:[f32] } (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr))  =>  (NMSUB_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 68046 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_S_MM),
     /* 68049 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68051 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68055 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68059 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68063 */     GIR_RootConstrainSelectedInstOperands,
     /* 68064 */     // GIR_Coverage, 2379,
     /* 68064 */     GIR_EraseRootFromParent_Done,
     /* 68065 */   // Label 1617: @68065
     /* 68065 */   GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(68084), // Rule ID 129 //
     /* 68070 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat),
     /* 68073 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68077 */     // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 68077 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S),
     /* 68082 */     GIR_RootConstrainSelectedInstOperands,
     /* 68083 */     // GIR_Coverage, 129,
     /* 68083 */     GIR_Done,
     /* 68084 */   // Label 1618: @68084
     /* 68084 */   GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(68103), // Rule ID 1228 //
     /* 68089 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 68092 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68096 */     // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 68096 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MM),
     /* 68101 */     GIR_RootConstrainSelectedInstOperands,
     /* 68102 */     // GIR_Coverage, 1228,
     /* 68102 */     GIR_Done,
     /* 68103 */   // Label 1619: @68103
     /* 68103 */   GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(68122), // Rule ID 1267 //
     /* 68108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat),
     /* 68111 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 68115 */     // (fneg:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FNEG_S_MMR6:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 68115 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_S_MMR6),
     /* 68120 */     GIR_RootConstrainSelectedInstOperands,
     /* 68121 */     // GIR_Coverage, 1267,
     /* 68121 */     GIR_Done,
     /* 68122 */   // Label 1620: @68122
     /* 68122 */   GIM_Reject,
     /* 68123 */ // Label 1593: @68123
     /* 68123 */ GIM_Reject,
     /* 68124 */ // Label 1591: @68124
     /* 68124 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(71113),
     /* 68129 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 68132 */   GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(68212), // Rule ID 1555 //
     /* 68137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68156 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68160 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68164 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68168 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68172 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68176 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68181 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68186 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68191 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68193 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 68196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68210 */     GIR_RootConstrainSelectedInstOperands,
     /* 68211 */     // GIR_Coverage, 1555,
     /* 68211 */     GIR_EraseRootFromParent_Done,
     /* 68212 */   // Label 1622: @68212
     /* 68212 */   GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(68292), // Rule ID 1563 //
     /* 68217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68240 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68244 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68248 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68252 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68256 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68261 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68266 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68271 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68273 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 68273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 68276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68290 */     GIR_RootConstrainSelectedInstOperands,
     /* 68291 */     // GIR_Coverage, 1563,
     /* 68291 */     GIR_EraseRootFromParent_Done,
     /* 68292 */   // Label 1623: @68292
     /* 68292 */   GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(68372), // Rule ID 2386 //
     /* 68297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 68300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68316 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68320 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68324 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68328 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68332 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68336 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68341 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68346 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68353 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 68356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68370 */     GIR_RootConstrainSelectedInstOperands,
     /* 68371 */     // GIR_Coverage, 2386,
     /* 68371 */     GIR_EraseRootFromParent_Done,
     /* 68372 */   // Label 1624: @68372
     /* 68372 */   GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(68452), // Rule ID 1554 //
     /* 68377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68396 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68400 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68404 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68408 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68412 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68416 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68421 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68426 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68431 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68433 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 68436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68450 */     GIR_RootConstrainSelectedInstOperands,
     /* 68451 */     // GIR_Coverage, 1554,
     /* 68451 */     GIR_EraseRootFromParent_Done,
     /* 68452 */   // Label 1625: @68452
     /* 68452 */   GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(68532), // Rule ID 1562 //
     /* 68457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68476 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68480 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68484 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68488 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68492 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68496 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68501 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68506 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68511 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68513 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 68513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 68516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68530 */     GIR_RootConstrainSelectedInstOperands,
     /* 68531 */     // GIR_Coverage, 1562,
     /* 68531 */     GIR_EraseRootFromParent_Done,
     /* 68532 */   // Label 1626: @68532
     /* 68532 */   GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(68612), // Rule ID 2385 //
     /* 68537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 68540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68548 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68552 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68556 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68560 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 68564 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68568 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68572 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68576 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68581 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68586 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68591 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68593 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 68596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68598 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 68602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68610 */     GIR_RootConstrainSelectedInstOperands,
     /* 68611 */     // GIR_Coverage, 2385,
     /* 68611 */     GIR_EraseRootFromParent_Done,
     /* 68612 */   // Label 1627: @68612
     /* 68612 */   GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(68692), // Rule ID 2602 //
     /* 68617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68636 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68640 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68645 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 68649 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68653 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68657 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68661 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68666 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68671 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68673 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 68676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 68682 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68690 */     GIR_RootConstrainSelectedInstOperands,
     /* 68691 */     // GIR_Coverage, 2602,
     /* 68691 */     GIR_EraseRootFromParent_Done,
     /* 68692 */   // Label 1628: @68692
     /* 68692 */   GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(68772), // Rule ID 2606 //
     /* 68697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68716 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68720 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68725 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 68729 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68733 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68737 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68741 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68746 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68751 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68753 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 68753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 68756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 68762 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68770 */     GIR_RootConstrainSelectedInstOperands,
     /* 68771 */     // GIR_Coverage, 2606,
     /* 68771 */     GIR_EraseRootFromParent_Done,
     /* 68772 */   // Label 1629: @68772
     /* 68772 */   GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(68852), // Rule ID 2697 //
     /* 68777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 68780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68796 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68800 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68805 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 68809 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 68813 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68817 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68821 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68826 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68831 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68833 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 68836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68838 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 68842 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68846 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68850 */     GIR_RootConstrainSelectedInstOperands,
     /* 68851 */     // GIR_Coverage, 2697,
     /* 68851 */     GIR_EraseRootFromParent_Done,
     /* 68852 */   // Label 1630: @68852
     /* 68852 */   GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(68932), // Rule ID 2601 //
     /* 68857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68872 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68876 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68880 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68885 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 68889 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68893 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68897 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68901 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68906 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 68911 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68913 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 68913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 68916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 68922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 68926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 68930 */     GIR_RootConstrainSelectedInstOperands,
     /* 68931 */     // GIR_Coverage, 2601,
     /* 68931 */     GIR_EraseRootFromParent_Done,
     /* 68932 */   // Label 1631: @68932
     /* 68932 */   GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(69012), // Rule ID 2605 //
     /* 68937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 68940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 68948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 68952 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 68956 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 68960 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68965 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 68969 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 68973 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 68977 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 68981 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68986 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 68991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 68993 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 68993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 68996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 68998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 69002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69010 */     GIR_RootConstrainSelectedInstOperands,
     /* 69011 */     // GIR_Coverage, 2605,
     /* 69011 */     GIR_EraseRootFromParent_Done,
     /* 69012 */   // Label 1632: @69012
     /* 69012 */   GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(69092), // Rule ID 2696 //
     /* 69017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 69020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69024 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69028 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FADD),
     /* 69032 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69036 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69040 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69045 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 69049 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69053 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69057 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69061 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69066 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69071 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69073 */     // (fneg:{ *:[f64] } (fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69073 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 69076 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69078 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 69082 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69086 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69090 */     GIR_RootConstrainSelectedInstOperands,
     /* 69091 */     // GIR_Coverage, 2696,
     /* 69091 */     GIR_EraseRootFromParent_Done,
     /* 69092 */   // Label 1633: @69092
     /* 69092 */   GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(69172), // Rule ID 1559 //
     /* 69097 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69100 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69104 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69108 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69112 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69116 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69120 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69124 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69128 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69132 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69136 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69141 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69146 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69151 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69153 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69153 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
     /* 69156 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69158 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69162 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69166 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69170 */     GIR_RootConstrainSelectedInstOperands,
     /* 69171 */     // GIR_Coverage, 1559,
     /* 69171 */     GIR_EraseRootFromParent_Done,
     /* 69172 */   // Label 1634: @69172
     /* 69172 */   GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(69252), // Rule ID 1567 //
     /* 69177 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69180 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69184 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69188 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69192 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69196 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69200 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69204 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69208 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69212 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69216 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69221 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69226 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69231 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69233 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 69233 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
     /* 69236 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69238 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69242 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69246 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69250 */     GIR_RootConstrainSelectedInstOperands,
     /* 69251 */     // GIR_Coverage, 1567,
     /* 69251 */     GIR_EraseRootFromParent_Done,
     /* 69252 */   // Label 1635: @69252
     /* 69252 */   GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(69332), // Rule ID 2390 //
     /* 69257 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 69260 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69264 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69268 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69272 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69276 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69280 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69284 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69288 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69292 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69296 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69301 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69306 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69311 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69313 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69313 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
     /* 69316 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69318 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69322 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69326 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69330 */     GIR_RootConstrainSelectedInstOperands,
     /* 69331 */     // GIR_Coverage, 2390,
     /* 69331 */     GIR_EraseRootFromParent_Done,
     /* 69332 */   // Label 1636: @69332
     /* 69332 */   GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(69412), // Rule ID 1558 //
     /* 69337 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69340 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69344 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69348 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69352 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69356 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69360 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69364 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69368 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69372 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69376 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69381 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69386 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69391 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69393 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69393 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
     /* 69396 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69398 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69402 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69406 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69410 */     GIR_RootConstrainSelectedInstOperands,
     /* 69411 */     // GIR_Coverage, 1558,
     /* 69411 */     GIR_EraseRootFromParent_Done,
     /* 69412 */   // Label 1637: @69412
     /* 69412 */   GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(69492), // Rule ID 1566 //
     /* 69417 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69420 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69424 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69428 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69432 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69436 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69440 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69444 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69448 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69452 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69456 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69461 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69466 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69471 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69473 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 69473 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
     /* 69476 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69478 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69482 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69486 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69490 */     GIR_RootConstrainSelectedInstOperands,
     /* 69491 */     // GIR_Coverage, 1566,
     /* 69491 */     GIR_EraseRootFromParent_Done,
     /* 69492 */   // Label 1638: @69492
     /* 69492 */   GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(69572), // Rule ID 2389 //
     /* 69497 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 69500 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69504 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69508 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
     /* 69512 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69516 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69520 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69524 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69528 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69532 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69536 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69541 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69546 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69551 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69553 */     // (fneg:{ *:[f64] } (fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69553 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
     /* 69556 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69558 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69562 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69566 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69570 */     GIR_RootConstrainSelectedInstOperands,
     /* 69571 */     // GIR_Coverage, 2389,
     /* 69571 */     GIR_EraseRootFromParent_Done,
     /* 69572 */   // Label 1639: @69572
     /* 69572 */   GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(69652), // Rule ID 1553 //
     /* 69577 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69580 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69584 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69588 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69592 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69596 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69600 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69604 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69608 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69612 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69616 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69621 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69626 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69631 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69633 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69633 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 69636 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69638 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69642 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69646 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69650 */     GIR_RootConstrainSelectedInstOperands,
     /* 69651 */     // GIR_Coverage, 1553,
     /* 69651 */     GIR_EraseRootFromParent_Done,
     /* 69652 */   // Label 1640: @69652
     /* 69652 */   GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(69732), // Rule ID 1561 //
     /* 69657 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69660 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69664 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69668 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69672 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69676 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69680 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69684 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69688 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69692 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69696 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69701 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69706 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69711 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69713 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 69713 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 69716 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69718 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69722 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69726 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69730 */     GIR_RootConstrainSelectedInstOperands,
     /* 69731 */     // GIR_Coverage, 1561,
     /* 69731 */     GIR_EraseRootFromParent_Done,
     /* 69732 */   // Label 1641: @69732
     /* 69732 */   GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(69812), // Rule ID 2384 //
     /* 69737 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 69740 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69744 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69748 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69752 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69756 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69760 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69764 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 69768 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69772 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69776 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69781 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69786 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69791 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69793 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69793 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 69796 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69798 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69802 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69806 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69810 */     GIR_RootConstrainSelectedInstOperands,
     /* 69811 */     // GIR_Coverage, 2384,
     /* 69811 */     GIR_EraseRootFromParent_Done,
     /* 69812 */   // Label 1642: @69812
     /* 69812 */   GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(69892), // Rule ID 1552 //
     /* 69817 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69824 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69828 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69832 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69836 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69840 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69844 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69848 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69852 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69856 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69861 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69866 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69871 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69873 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 69873 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 69876 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69878 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69882 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69886 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69890 */     GIR_RootConstrainSelectedInstOperands,
     /* 69891 */     // GIR_Coverage, 1552,
     /* 69891 */     GIR_EraseRootFromParent_Done,
     /* 69892 */   // Label 1643: @69892
     /* 69892 */   GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(69972), // Rule ID 1560 //
     /* 69897 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 69900 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69904 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69908 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69912 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69916 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 69920 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 69924 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 69928 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 69932 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 69936 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69941 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69946 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 69951 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 69953 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 69953 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 69956 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 69958 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 69962 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 69966 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 69970 */     GIR_RootConstrainSelectedInstOperands,
     /* 69971 */     // GIR_Coverage, 1560,
     /* 69971 */     GIR_EraseRootFromParent_Done,
     /* 69972 */   // Label 1644: @69972
     /* 69972 */   GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(70052), // Rule ID 2383 //
     /* 69977 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 69980 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 69984 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 69988 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 69992 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 69996 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70000 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70004 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70008 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70012 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70016 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70021 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70026 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70031 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70033 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70033 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 70036 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70038 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70042 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70046 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70050 */     GIR_RootConstrainSelectedInstOperands,
     /* 70051 */     // GIR_Coverage, 2383,
     /* 70051 */     GIR_EraseRootFromParent_Done,
     /* 70052 */   // Label 1645: @70052
     /* 70052 */   GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(70132), // Rule ID 2600 //
     /* 70057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70064 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70068 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70072 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70076 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70080 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70085 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70089 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70093 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70097 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70101 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70106 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70111 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70113 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70113 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 70116 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70118 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70122 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70126 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70130 */     GIR_RootConstrainSelectedInstOperands,
     /* 70131 */     // GIR_Coverage, 2600,
     /* 70131 */     GIR_EraseRootFromParent_Done,
     /* 70132 */   // Label 1646: @70132
     /* 70132 */   GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(70212), // Rule ID 2604 //
     /* 70137 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70140 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70144 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70148 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70152 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70156 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70160 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70165 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70169 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70173 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70177 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70181 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70186 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70191 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70193 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 70193 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 70196 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70198 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70202 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70206 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70210 */     GIR_RootConstrainSelectedInstOperands,
     /* 70211 */     // GIR_Coverage, 2604,
     /* 70211 */     GIR_EraseRootFromParent_Done,
     /* 70212 */   // Label 1647: @70212
     /* 70212 */   GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(70292), // Rule ID 2695 //
     /* 70217 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 70220 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70224 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70228 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70232 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70236 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70240 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70245 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70249 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70253 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70257 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70261 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70266 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70271 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70273 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70273 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 70276 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70278 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70282 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70286 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70290 */     GIR_RootConstrainSelectedInstOperands,
     /* 70291 */     // GIR_Coverage, 2695,
     /* 70291 */     GIR_EraseRootFromParent_Done,
     /* 70292 */   // Label 1648: @70292
     /* 70292 */   GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(70372), // Rule ID 2599 //
     /* 70297 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70300 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70304 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70308 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70312 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70316 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70320 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70325 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70329 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70333 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70337 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70341 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70346 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70351 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70353 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70353 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32),
     /* 70356 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70358 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70362 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70366 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70370 */     GIR_RootConstrainSelectedInstOperands,
     /* 70371 */     // GIR_Coverage, 2599,
     /* 70371 */     GIR_EraseRootFromParent_Done,
     /* 70372 */   // Label 1649: @70372
     /* 70372 */   GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(70452), // Rule ID 2603 //
     /* 70377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70380 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70384 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70388 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70392 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70396 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70400 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70405 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70409 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70413 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70417 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70421 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70426 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70431 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70433 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 70433 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D64),
     /* 70436 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70438 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70442 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70446 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70450 */     GIR_RootConstrainSelectedInstOperands,
     /* 70451 */     // GIR_Coverage, 2603,
     /* 70451 */     GIR_EraseRootFromParent_Done,
     /* 70452 */   // Label 1650: @70452
     /* 70452 */   GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(70532), // Rule ID 2694 //
     /* 70457 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 70460 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70464 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70468 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FADD),
     /* 70472 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70476 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70480 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70485 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
     /* 70489 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70493 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70497 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70501 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70506 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70511 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70513 */     // (fneg:{ *:[f64] } (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)))  =>  (NMADD_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70513 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMADD_D32_MM),
     /* 70516 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70518 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fr
     /* 70522 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70526 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70530 */     GIR_RootConstrainSelectedInstOperands,
     /* 70531 */     // GIR_Coverage, 2694,
     /* 70531 */     GIR_EraseRootFromParent_Done,
     /* 70532 */   // Label 1651: @70532
     /* 70532 */   GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(70612), // Rule ID 1557 //
     /* 70537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70544 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70548 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70552 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70556 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70560 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70564 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70568 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70572 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70576 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70581 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70586 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70591 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70593 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70593 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
     /* 70596 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70598 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70602 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70606 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70610 */     GIR_RootConstrainSelectedInstOperands,
     /* 70611 */     // GIR_Coverage, 1557,
     /* 70611 */     GIR_EraseRootFromParent_Done,
     /* 70612 */   // Label 1652: @70612
     /* 70612 */   GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(70692), // Rule ID 1565 //
     /* 70617 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70620 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70624 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70628 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70632 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70636 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70640 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70644 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70648 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70652 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70656 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70661 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70666 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70671 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70673 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 70673 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
     /* 70676 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70678 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70682 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70686 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70690 */     GIR_RootConstrainSelectedInstOperands,
     /* 70691 */     // GIR_Coverage, 1565,
     /* 70691 */     GIR_EraseRootFromParent_Done,
     /* 70692 */   // Label 1653: @70692
     /* 70692 */   GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(70772), // Rule ID 2388 //
     /* 70697 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 70700 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70704 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70708 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70712 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70716 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70720 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70724 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 70728 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70732 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70736 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70741 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70746 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70751 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70753 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70753 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
     /* 70756 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70758 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70762 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70766 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70770 */     GIR_RootConstrainSelectedInstOperands,
     /* 70771 */     // GIR_Coverage, 2388,
     /* 70771 */     GIR_EraseRootFromParent_Done,
     /* 70772 */   // Label 1654: @70772
     /* 70772 */   GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(70852), // Rule ID 1556 //
     /* 70777 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70784 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70788 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70792 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70796 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70800 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70804 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70808 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70812 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70816 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70821 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70826 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70831 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70833 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70833 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32),
     /* 70836 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70838 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70842 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70846 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70850 */     GIR_RootConstrainSelectedInstOperands,
     /* 70851 */     // GIR_Coverage, 1556,
     /* 70851 */     GIR_EraseRootFromParent_Done,
     /* 70852 */   // Label 1655: @70852
     /* 70852 */   GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(70932), // Rule ID 1564 //
     /* 70857 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 70860 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70864 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70868 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70872 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70876 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70880 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70884 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70888 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70892 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70896 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70901 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70906 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 70911 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70913 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 70913 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D64),
     /* 70916 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70918 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 70922 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 70926 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 70930 */     GIR_RootConstrainSelectedInstOperands,
     /* 70931 */     // GIR_Coverage, 1564,
     /* 70931 */     GIR_EraseRootFromParent_Done,
     /* 70932 */   // Label 1656: @70932
     /* 70932 */   GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(71012), // Rule ID 2387 //
     /* 70937 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6),
     /* 70940 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70944 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 70948 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FSUB),
     /* 70952 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 70956 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 70960 */     GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
     /* 70964 */     GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 70968 */     GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
     /* 70972 */     GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
     /* 70976 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70981 */     GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70986 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 70991 */     GIM_CheckIsSafeToFold, /*NumInsns*/2,
     /* 70993 */     // (fneg:{ *:[f64] } (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr))  =>  (NMSUB_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 70993 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::NMSUB_D32_MM),
     /* 70996 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 70998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // fr
     /* 71002 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // fs
     /* 71006 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // ft
     /* 71010 */     GIR_RootConstrainSelectedInstOperands,
     /* 71011 */     // GIR_Coverage, 2387,
     /* 71011 */     GIR_EraseRootFromParent_Done,
     /* 71012 */   // Label 1657: @71012
     /* 71012 */   GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(71039), // Rule ID 130 //
     /* 71017 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 71020 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71024 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71028 */     // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 71028 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32),
     /* 71033 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71037 */     GIR_RootConstrainSelectedInstOperands,
     /* 71038 */     // GIR_Coverage, 130,
     /* 71038 */     GIR_Done,
     /* 71039 */   // Label 1658: @71039
     /* 71039 */   GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(71066), // Rule ID 131 //
     /* 71044 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 71047 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71051 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71055 */     // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 71055 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64),
     /* 71060 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71064 */     GIR_RootConstrainSelectedInstOperands,
     /* 71065 */     // GIR_Coverage, 131,
     /* 71065 */     GIR_Done,
     /* 71066 */   // Label 1659: @71066
     /* 71066 */   GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(71089), // Rule ID 1229 //
     /* 71071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 71074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71078 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71082 */     // (fneg:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 71082 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D32_MM),
     /* 71087 */     GIR_RootConstrainSelectedInstOperands,
     /* 71088 */     // GIR_Coverage, 1229,
     /* 71088 */     GIR_Done,
     /* 71089 */   // Label 1660: @71089
     /* 71089 */   GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(71112), // Rule ID 1230 //
     /* 71094 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 71097 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71101 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71105 */     // (fneg:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FNEG_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 71105 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FNEG_D64_MM),
     /* 71110 */     GIR_RootConstrainSelectedInstOperands,
     /* 71111 */     // GIR_Coverage, 1230,
     /* 71111 */     GIR_Done,
     /* 71112 */   // Label 1661: @71112
     /* 71112 */   GIM_Reject,
     /* 71113 */ // Label 1621: @71113
     /* 71113 */ GIM_Reject,
     /* 71114 */ // Label 1592: @71114
     /* 71114 */ GIM_Reject,
     /* 71115 */ // Label 54: @71115
     /* 71115 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1664*/ GIMT_Encode4(71308),
     /* 71126 */ /*GILLT_s32*//*Label 1662*/ GIMT_Encode4(71134),
     /* 71130 */ /*GILLT_s64*//*Label 1663*/ GIMT_Encode4(71161),
     /* 71134 */ // Label 1662: @71134
     /* 71134 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(71160), // Rule ID 1131 //
     /* 71139 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 71142 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 71145 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71149 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
     /* 71153 */   // (fpextend:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_W_PSEUDO:{ *:[f32] } MSA128F16:{ *:[f16] }:$ws)
     /* 71153 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_W_PSEUDO),
     /* 71158 */   GIR_RootConstrainSelectedInstOperands,
     /* 71159 */   // GIR_Coverage, 1131,
     /* 71159 */   GIR_Done,
     /* 71160 */ // Label 1665: @71160
     /* 71160 */ GIM_Reject,
     /* 71161 */ // Label 1663: @71161
     /* 71161 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(71187), // Rule ID 1133 //
     /* 71166 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 71169 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
     /* 71172 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71176 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
     /* 71180 */   // (fpextend:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)  =>  (MSA_FP_EXTEND_D_PSEUDO:{ *:[f64] } MSA128F16:{ *:[f16] }:$ws)
     /* 71180 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_EXTEND_D_PSEUDO),
     /* 71185 */   GIR_RootConstrainSelectedInstOperands,
     /* 71186 */   // GIR_Coverage, 1133,
     /* 71186 */   GIR_Done,
     /* 71187 */ // Label 1666: @71187
     /* 71187 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(71217), // Rule ID 1528 //
     /* 71192 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
     /* 71195 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71198 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71202 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71206 */   // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
     /* 71206 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S),
     /* 71211 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71215 */   GIR_RootConstrainSelectedInstOperands,
     /* 71216 */   // GIR_Coverage, 1528,
     /* 71216 */   GIR_Done,
     /* 71217 */ // Label 1667: @71217
     /* 71217 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(71247), // Rule ID 1543 //
     /* 71222 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
     /* 71225 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71228 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71232 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71236 */   // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
     /* 71236 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S),
     /* 71241 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71245 */   GIR_RootConstrainSelectedInstOperands,
     /* 71246 */   // GIR_Coverage, 1543,
     /* 71246 */   GIR_Done,
     /* 71247 */ // Label 1668: @71247
     /* 71247 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(71277), // Rule ID 2401 //
     /* 71252 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
     /* 71255 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71258 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71262 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71266 */   // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D64_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
     /* 71266 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D64_S_MM),
     /* 71271 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71275 */   GIR_RootConstrainSelectedInstOperands,
     /* 71276 */   // GIR_Coverage, 2401,
     /* 71276 */   GIR_Done,
     /* 71277 */ // Label 1669: @71277
     /* 71277 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(71307), // Rule ID 2403 //
     /* 71282 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
     /* 71285 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71288 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71292 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71296 */   // (fpextend:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)  =>  (CVT_D32_S_MM:{ *:[f64] } FGR32Opnd:{ *:[f32] }:$src)
     /* 71296 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_D32_S_MM),
     /* 71301 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71305 */   GIR_RootConstrainSelectedInstOperands,
     /* 71306 */   // GIR_Coverage, 2403,
     /* 71306 */   GIR_Done,
     /* 71307 */ // Label 1670: @71307
     /* 71307 */ GIM_Reject,
     /* 71308 */ // Label 1664: @71308
     /* 71308 */ GIM_Reject,
     /* 71309 */ // Label 55: @71309
     /* 71309 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1673*/ GIMT_Encode4(71487),
     /* 71320 */ /*GILLT_s16*//*Label 1671*/ GIMT_Encode4(71328),
     /* 71324 */ /*GILLT_s32*//*Label 1672*/ GIMT_Encode4(71381),
     /* 71328 */ // Label 1671: @71328
     /* 71328 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(71354), // Rule ID 1132 //
     /* 71333 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 71336 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71339 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
     /* 71343 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71347 */   // (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 71347 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_W_PSEUDO),
     /* 71352 */   GIR_RootConstrainSelectedInstOperands,
     /* 71353 */   // GIR_Coverage, 1132,
     /* 71353 */   GIR_Done,
     /* 71354 */ // Label 1674: @71354
     /* 71354 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(71380), // Rule ID 1134 //
     /* 71359 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 71362 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 71365 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128F16RegClassID),
     /* 71369 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71373 */   // (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 71373 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MSA_FP_ROUND_D_PSEUDO),
     /* 71378 */   GIR_RootConstrainSelectedInstOperands,
     /* 71379 */   // GIR_Coverage, 1134,
     /* 71379 */   GIR_Done,
     /* 71380 */ // Label 1675: @71380
     /* 71380 */ GIM_Reject,
     /* 71381 */ // Label 1672: @71381
     /* 71381 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(71486),
     /* 71386 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 71389 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71393 */   GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(71416), // Rule ID 1526 //
     /* 71398 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips),
     /* 71401 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71405 */     // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
     /* 71405 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32),
     /* 71410 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71414 */     GIR_RootConstrainSelectedInstOperands,
     /* 71415 */     // GIR_Coverage, 1526,
     /* 71415 */     GIR_Done,
     /* 71416 */   // Label 1677: @71416
     /* 71416 */   GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(71439), // Rule ID 1541 //
     /* 71421 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips),
     /* 71424 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71428 */     // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
     /* 71428 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64),
     /* 71433 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71437 */     GIR_RootConstrainSelectedInstOperands,
     /* 71438 */     // GIR_Coverage, 1541,
     /* 71438 */     GIR_Done,
     /* 71439 */   // Label 1678: @71439
     /* 71439 */   GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(71462), // Rule ID 2400 //
     /* 71444 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit),
     /* 71447 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71451 */     // (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src)
     /* 71451 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D64_MM),
     /* 71456 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71460 */     GIR_RootConstrainSelectedInstOperands,
     /* 71461 */     // GIR_Coverage, 2400,
     /* 71461 */     GIR_Done,
     /* 71462 */   // Label 1679: @71462
     /* 71462 */   GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(71485), // Rule ID 2402 //
     /* 71467 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotFP64bit),
     /* 71470 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71474 */     // (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)  =>  (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src)
     /* 71474 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CVT_S_D32_MM),
     /* 71479 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 71483 */     GIR_RootConstrainSelectedInstOperands,
     /* 71484 */     // GIR_Coverage, 2402,
     /* 71484 */     GIR_Done,
     /* 71485 */   // Label 1680: @71485
     /* 71485 */   GIM_Reject,
     /* 71486 */ // Label 1676: @71486
     /* 71486 */ GIM_Reject,
     /* 71487 */ // Label 1673: @71487
     /* 71487 */ GIM_Reject,
     /* 71488 */ // Label 56: @71488
     /* 71488 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1683*/ GIMT_Encode4(71565),
     /* 71499 */ /*GILLT_v2s64*//*Label 1681*/ GIMT_Encode4(71511), GIMT_Encode4(0),
     /* 71507 */ /*GILLT_v4s32*//*Label 1682*/ GIMT_Encode4(71538),
     /* 71511 */ // Label 1681: @71511
     /* 71511 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(71537), // Rule ID 852 //
     /* 71516 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71519 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 71522 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71526 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71530 */   // (fp_to_sint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 71530 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_D),
     /* 71535 */   GIR_RootConstrainSelectedInstOperands,
     /* 71536 */   // GIR_Coverage, 852,
     /* 71536 */   GIR_Done,
     /* 71537 */ // Label 1684: @71537
     /* 71537 */ GIM_Reject,
     /* 71538 */ // Label 1682: @71538
     /* 71538 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(71564), // Rule ID 851 //
     /* 71543 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71546 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 71549 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71553 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71557 */   // (fp_to_sint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 71557 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_S_W),
     /* 71562 */   GIR_RootConstrainSelectedInstOperands,
     /* 71563 */   // GIR_Coverage, 851,
     /* 71563 */   GIR_Done,
     /* 71564 */ // Label 1685: @71564
     /* 71564 */ GIM_Reject,
     /* 71565 */ // Label 1683: @71565
     /* 71565 */ GIM_Reject,
     /* 71566 */ // Label 57: @71566
     /* 71566 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1688*/ GIMT_Encode4(71643),
     /* 71577 */ /*GILLT_v2s64*//*Label 1686*/ GIMT_Encode4(71589), GIMT_Encode4(0),
     /* 71585 */ /*GILLT_v4s32*//*Label 1687*/ GIMT_Encode4(71616),
     /* 71589 */ // Label 1686: @71589
     /* 71589 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(71615), // Rule ID 854 //
     /* 71594 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71597 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 71600 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71604 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71608 */   // (fp_to_uint:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FTRUNC_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 71608 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_D),
     /* 71613 */   GIR_RootConstrainSelectedInstOperands,
     /* 71614 */   // GIR_Coverage, 854,
     /* 71614 */   GIR_Done,
     /* 71615 */ // Label 1689: @71615
     /* 71615 */ GIM_Reject,
     /* 71616 */ // Label 1687: @71616
     /* 71616 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(71642), // Rule ID 853 //
     /* 71621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 71627 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71631 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71635 */   // (fp_to_uint:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FTRUNC_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 71635 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FTRUNC_U_W),
     /* 71640 */   GIR_RootConstrainSelectedInstOperands,
     /* 71641 */   // GIR_Coverage, 853,
     /* 71641 */   GIR_Done,
     /* 71642 */ // Label 1690: @71642
     /* 71642 */ GIM_Reject,
     /* 71643 */ // Label 1688: @71643
     /* 71643 */ GIM_Reject,
     /* 71644 */ // Label 58: @71644
     /* 71644 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1695*/ GIMT_Encode4(71896),
     /* 71655 */ /*GILLT_s32*//*Label 1691*/ GIMT_Encode4(71679),
     /* 71659 */ /*GILLT_s64*//*Label 1692*/ GIMT_Encode4(71763), GIMT_Encode4(0),
     /* 71667 */ /*GILLT_v2s64*//*Label 1693*/ GIMT_Encode4(71842), GIMT_Encode4(0),
     /* 71675 */ /*GILLT_v4s32*//*Label 1694*/ GIMT_Encode4(71869),
     /* 71679 */ // Label 1691: @71679
     /* 71679 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(71702), // Rule ID 1519 //
     /* 71684 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71687 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71691 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 71695 */   // (sint_to_fp:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_S_W:{ *:[f32] } GPR32Opnd:{ *:[i32] }:$src)
     /* 71695 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_W),
     /* 71700 */   GIR_RootConstrainSelectedInstOperands,
     /* 71701 */   // GIR_Coverage, 1519,
     /* 71701 */   GIR_Done,
     /* 71702 */ // Label 1696: @71702
     /* 71702 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(71762), // Rule ID 1534 //
     /* 71707 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
     /* 71710 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 71713 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71717 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 71721 */   // (sint_to_fp:{ *:[f32] } GPR64Opnd:{ *:[i64] }:$src)  =>  (EXTRACT_SUBREG:{ *:[f32] } (PseudoCVT_S_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src), sub_lo:{ *:[i32] })
     /* 71721 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 71724 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_S_L),
     /* 71728 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 71733 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
     /* 71737 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 71739 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
     /* 71742 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
     /* 71744 */   GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(Mips::sub_lo),
     /* 71751 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Mips::FGR32RegClassID),
     /* 71756 */   GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71761 */   // GIR_Coverage, 1534,
     /* 71761 */   GIR_EraseRootFromParent_Done,
     /* 71762 */ // Label 1697: @71762
     /* 71762 */ GIM_Reject,
     /* 71763 */ // Label 1692: @71763
     /* 71763 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(71789), // Rule ID 1523 //
     /* 71768 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotFP64bit),
     /* 71771 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71774 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 71778 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 71782 */   // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D32_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
     /* 71782 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D32_W),
     /* 71787 */   GIR_RootConstrainSelectedInstOperands,
     /* 71788 */   // GIR_Coverage, 1523,
     /* 71788 */   GIR_Done,
     /* 71789 */ // Label 1698: @71789
     /* 71789 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(71815), // Rule ID 1532 //
     /* 71794 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
     /* 71797 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 71800 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71804 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 71808 */   // (sint_to_fp:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)  =>  (PseudoCVT_D64_W:{ *:[f64] } GPR32Opnd:{ *:[i32] }:$src)
     /* 71808 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_W),
     /* 71813 */   GIR_RootConstrainSelectedInstOperands,
     /* 71814 */   // GIR_Coverage, 1532,
     /* 71814 */   GIR_Done,
     /* 71815 */ // Label 1699: @71815
     /* 71815 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(71841), // Rule ID 1536 //
     /* 71820 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsFP64bit),
     /* 71823 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 71826 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 71830 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 71834 */   // (sint_to_fp:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)  =>  (PseudoCVT_D64_L:{ *:[f64] } GPR64Opnd:{ *:[i64] }:$src)
     /* 71834 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PseudoCVT_D64_L),
     /* 71839 */   GIR_RootConstrainSelectedInstOperands,
     /* 71840 */   // GIR_Coverage, 1536,
     /* 71840 */   GIR_Done,
     /* 71841 */ // Label 1700: @71841
     /* 71841 */ GIM_Reject,
     /* 71842 */ // Label 1693: @71842
     /* 71842 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(71868), // Rule ID 784 //
     /* 71847 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71850 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 71853 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71857 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71861 */   // (sint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_S_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
     /* 71861 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_D),
     /* 71866 */   GIR_RootConstrainSelectedInstOperands,
     /* 71867 */   // GIR_Coverage, 784,
     /* 71867 */   GIR_Done,
     /* 71868 */ // Label 1701: @71868
     /* 71868 */ GIM_Reject,
     /* 71869 */ // Label 1694: @71869
     /* 71869 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(71895), // Rule ID 783 //
     /* 71874 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71877 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 71880 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71884 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71888 */   // (sint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_S_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 71888 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_S_W),
     /* 71893 */   GIR_RootConstrainSelectedInstOperands,
     /* 71894 */   // GIR_Coverage, 783,
     /* 71894 */   GIR_Done,
     /* 71895 */ // Label 1702: @71895
     /* 71895 */ GIM_Reject,
     /* 71896 */ // Label 1695: @71896
     /* 71896 */ GIM_Reject,
     /* 71897 */ // Label 59: @71897
     /* 71897 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1705*/ GIMT_Encode4(71974),
     /* 71908 */ /*GILLT_v2s64*//*Label 1703*/ GIMT_Encode4(71920), GIMT_Encode4(0),
     /* 71916 */ /*GILLT_v4s32*//*Label 1704*/ GIMT_Encode4(71947),
     /* 71920 */ // Label 1703: @71920
     /* 71920 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(71946), // Rule ID 786 //
     /* 71925 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71928 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 71931 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71935 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 71939 */   // (uint_to_fp:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (FFINT_U_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
     /* 71939 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_D),
     /* 71944 */   GIR_RootConstrainSelectedInstOperands,
     /* 71945 */   // GIR_Coverage, 786,
     /* 71945 */   GIR_Done,
     /* 71946 */ // Label 1706: @71946
     /* 71946 */ GIM_Reject,
     /* 71947 */ // Label 1704: @71947
     /* 71947 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(71973), // Rule ID 785 //
     /* 71952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 71955 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 71958 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71962 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 71966 */   // (uint_to_fp:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (FFINT_U_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 71966 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FFINT_U_W),
     /* 71971 */   GIR_RootConstrainSelectedInstOperands,
     /* 71972 */   // GIR_Coverage, 785,
     /* 71972 */   GIR_Done,
     /* 71973 */ // Label 1707: @71973
     /* 71973 */ GIM_Reject,
     /* 71974 */ // Label 1705: @71974
     /* 71974 */ GIM_Reject,
     /* 71975 */ // Label 60: @71975
     /* 71975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1712*/ GIMT_Encode4(72222),
     /* 71986 */ /*GILLT_s32*//*Label 1708*/ GIMT_Encode4(72010),
     /* 71990 */ /*GILLT_s64*//*Label 1709*/ GIMT_Encode4(72058), GIMT_Encode4(0),
     /* 71998 */ /*GILLT_v2s64*//*Label 1710*/ GIMT_Encode4(72168), GIMT_Encode4(0),
     /* 72006 */ /*GILLT_v4s32*//*Label 1711*/ GIMT_Encode4(72195),
     /* 72010 */ // Label 1708: @72010
     /* 72010 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(72057),
     /* 72015 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72018 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72022 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72026 */   GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(72041), // Rule ID 126 //
     /* 72031 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs),
     /* 72034 */     // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 72034 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S),
     /* 72039 */     GIR_RootConstrainSelectedInstOperands,
     /* 72040 */     // GIR_Coverage, 126,
     /* 72040 */     GIR_Done,
     /* 72041 */   // Label 1714: @72041
     /* 72041 */   GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(72056), // Rule ID 1227 //
     /* 72046 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_UseAbs),
     /* 72049 */     // (fabs:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FABS_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 72049 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_S_MM),
     /* 72054 */     GIR_RootConstrainSelectedInstOperands,
     /* 72055 */     // GIR_Coverage, 1227,
     /* 72055 */     GIR_Done,
     /* 72056 */   // Label 1715: @72056
     /* 72056 */   GIM_Reject,
     /* 72057 */ // Label 1713: @72057
     /* 72057 */ GIM_Reject,
     /* 72058 */ // Label 1709: @72058
     /* 72058 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(72167),
     /* 72063 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72066 */   GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(72093), // Rule ID 127 //
     /* 72071 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs),
     /* 72074 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 72078 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 72082 */     // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 72082 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32),
     /* 72087 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 72091 */     GIR_RootConstrainSelectedInstOperands,
     /* 72092 */     // GIR_Coverage, 127,
     /* 72092 */     GIR_Done,
     /* 72093 */   // Label 1717: @72093
     /* 72093 */   GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(72120), // Rule ID 128 //
     /* 72098 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs),
     /* 72101 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72105 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72109 */     // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 72109 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64),
     /* 72114 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 72118 */     GIR_RootConstrainSelectedInstOperands,
     /* 72119 */     // GIR_Coverage, 128,
     /* 72119 */     GIR_Done,
     /* 72120 */   // Label 1718: @72120
     /* 72120 */   GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(72143), // Rule ID 1225 //
     /* 72125 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 72128 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 72132 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 72136 */     // (fabs:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 72136 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D32_MM),
     /* 72141 */     GIR_RootConstrainSelectedInstOperands,
     /* 72142 */     // GIR_Coverage, 1225,
     /* 72142 */     GIR_Done,
     /* 72143 */   // Label 1719: @72143
     /* 72143 */   GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(72166), // Rule ID 1226 //
     /* 72148 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 72151 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72155 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72159 */     // (fabs:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FABS_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 72159 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D64_MM),
     /* 72164 */     GIR_RootConstrainSelectedInstOperands,
     /* 72165 */     // GIR_Coverage, 1226,
     /* 72165 */     GIR_Done,
     /* 72166 */   // Label 1720: @72166
     /* 72166 */   GIM_Reject,
     /* 72167 */ // Label 1716: @72167
     /* 72167 */ GIM_Reject,
     /* 72168 */ // Label 1710: @72168
     /* 72168 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(72194), // Rule ID 1118 //
     /* 72173 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72176 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 72179 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72183 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72187 */   // (fabs:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FABS_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 72187 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_D),
     /* 72192 */   GIR_RootConstrainSelectedInstOperands,
     /* 72193 */   // GIR_Coverage, 1118,
     /* 72193 */   GIR_Done,
     /* 72194 */ // Label 1721: @72194
     /* 72194 */ GIM_Reject,
     /* 72195 */ // Label 1711: @72195
     /* 72195 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(72221), // Rule ID 1117 //
     /* 72200 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72203 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 72206 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72210 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72214 */   // (fabs:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FABS_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 72214 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FABS_W),
     /* 72219 */   GIR_RootConstrainSelectedInstOperands,
     /* 72220 */   // GIR_Coverage, 1117,
     /* 72220 */   GIR_Done,
     /* 72221 */ // Label 1722: @72221
     /* 72221 */ GIM_Reject,
     /* 72222 */ // Label 1712: @72222
     /* 72222 */ GIM_Reject,
     /* 72223 */ // Label 61: @72223
     /* 72223 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1725*/ GIMT_Encode4(72296),
     /* 72234 */ /*GILLT_s32*//*Label 1723*/ GIMT_Encode4(72242),
     /* 72238 */ /*GILLT_s64*//*Label 1724*/ GIMT_Encode4(72269),
     /* 72242 */ // Label 1723: @72242
     /* 72242 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(72268), // Rule ID 1889 //
     /* 72247 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72250 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72253 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72257 */   // (fcanonicalize:{ *:[f32] } f32:{ *:[f32] }:$src)  =>  (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$src)
     /* 72257 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
     /* 72260 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 72262 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 72264 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 72266 */   GIR_RootConstrainSelectedInstOperands,
     /* 72267 */   // GIR_Coverage, 1889,
     /* 72267 */   GIR_EraseRootFromParent_Done,
     /* 72268 */ // Label 1726: @72268
     /* 72268 */ GIM_Reject,
     /* 72269 */ // Label 1724: @72269
     /* 72269 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(72295), // Rule ID 1890 //
     /* 72274 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72277 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72280 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72284 */   // (fcanonicalize:{ *:[f64] } f64:{ *:[f64] }:$src)  =>  (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$src)
     /* 72284 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
     /* 72287 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 72289 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 72291 */   GIR_RootToRootCopy, /*OpIdx*/1, // src
     /* 72293 */   GIR_RootConstrainSelectedInstOperands,
     /* 72294 */   // GIR_Coverage, 1890,
     /* 72294 */   GIR_EraseRootFromParent_Done,
     /* 72295 */ // Label 1727: @72295
     /* 72295 */ GIM_Reject,
     /* 72296 */ // Label 1725: @72296
     /* 72296 */ GIM_Reject,
     /* 72297 */ // Label 62: @72297
     /* 72297 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1730*/ GIMT_Encode4(72368),
     /* 72308 */ /*GILLT_s32*//*Label 1728*/ GIMT_Encode4(72316),
     /* 72312 */ /*GILLT_s64*//*Label 1729*/ GIMT_Encode4(72342),
     /* 72316 */ // Label 1728: @72316
     /* 72316 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(72341), // Rule ID 1886 //
     /* 72321 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72324 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72327 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 72330 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72334 */   // (fminnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)  =>  (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
     /* 72334 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
     /* 72339 */   GIR_RootConstrainSelectedInstOperands,
     /* 72340 */   // GIR_Coverage, 1886,
     /* 72340 */   GIR_Done,
     /* 72341 */ // Label 1731: @72341
     /* 72341 */ GIM_Reject,
     /* 72342 */ // Label 1729: @72342
     /* 72342 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(72367), // Rule ID 1888 //
     /* 72347 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72350 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72353 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 72356 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72360 */   // (fminnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)  =>  (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
     /* 72360 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
     /* 72365 */   GIR_RootConstrainSelectedInstOperands,
     /* 72366 */   // GIR_Coverage, 1888,
     /* 72366 */   GIR_Done,
     /* 72367 */ // Label 1732: @72367
     /* 72367 */ GIM_Reject,
     /* 72368 */ // Label 1730: @72368
     /* 72368 */ GIM_Reject,
     /* 72369 */ // Label 63: @72369
     /* 72369 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1735*/ GIMT_Encode4(72440),
     /* 72380 */ /*GILLT_s32*//*Label 1733*/ GIMT_Encode4(72388),
     /* 72384 */ /*GILLT_s64*//*Label 1734*/ GIMT_Encode4(72414),
     /* 72388 */ // Label 1733: @72388
     /* 72388 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(72413), // Rule ID 1882 //
     /* 72393 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72396 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72399 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 72402 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72406 */   // (fmaxnum:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)  =>  (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
     /* 72406 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
     /* 72411 */   GIR_RootConstrainSelectedInstOperands,
     /* 72412 */   // GIR_Coverage, 1882,
     /* 72412 */   GIR_Done,
     /* 72413 */ // Label 1736: @72413
     /* 72413 */ GIM_Reject,
     /* 72414 */ // Label 1734: @72414
     /* 72414 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(72439), // Rule ID 1884 //
     /* 72419 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72422 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72425 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 72428 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72432 */   // (fmaxnum:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)  =>  (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
     /* 72432 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
     /* 72437 */   GIR_RootConstrainSelectedInstOperands,
     /* 72438 */   // GIR_Coverage, 1884,
     /* 72438 */   GIR_Done,
     /* 72439 */ // Label 1737: @72439
     /* 72439 */ GIM_Reject,
     /* 72440 */ // Label 1735: @72440
     /* 72440 */ GIM_Reject,
     /* 72441 */ // Label 64: @72441
     /* 72441 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1740*/ GIMT_Encode4(72512),
     /* 72452 */ /*GILLT_s32*//*Label 1738*/ GIMT_Encode4(72460),
     /* 72456 */ /*GILLT_s64*//*Label 1739*/ GIMT_Encode4(72486),
     /* 72460 */ // Label 1738: @72460
     /* 72460 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(72485), // Rule ID 1885 //
     /* 72465 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72468 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72471 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 72474 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72478 */   // (fminnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)  =>  (MIN_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
     /* 72478 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S),
     /* 72483 */   GIR_RootConstrainSelectedInstOperands,
     /* 72484 */   // GIR_Coverage, 1885,
     /* 72484 */   GIR_Done,
     /* 72485 */ // Label 1741: @72485
     /* 72485 */ GIM_Reject,
     /* 72486 */ // Label 1739: @72486
     /* 72486 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(72511), // Rule ID 1887 //
     /* 72491 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72494 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72497 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 72500 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72504 */   // (fminnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)  =>  (MIN_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
     /* 72504 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_D),
     /* 72509 */   GIR_RootConstrainSelectedInstOperands,
     /* 72510 */   // GIR_Coverage, 1887,
     /* 72510 */   GIR_Done,
     /* 72511 */ // Label 1742: @72511
     /* 72511 */ GIM_Reject,
     /* 72512 */ // Label 1740: @72512
     /* 72512 */ GIM_Reject,
     /* 72513 */ // Label 65: @72513
     /* 72513 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1745*/ GIMT_Encode4(72584),
     /* 72524 */ /*GILLT_s32*//*Label 1743*/ GIMT_Encode4(72532),
     /* 72528 */ /*GILLT_s64*//*Label 1744*/ GIMT_Encode4(72558),
     /* 72532 */ // Label 1743: @72532
     /* 72532 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(72557), // Rule ID 1881 //
     /* 72537 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72540 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 72543 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 72546 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 72550 */   // (fmaxnum_ieee:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)  =>  (MAX_S:{ *:[f32] } f32:{ *:[f32] }:$lhs, f32:{ *:[f32] }:$rhs)
     /* 72550 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S),
     /* 72555 */   GIR_RootConstrainSelectedInstOperands,
     /* 72556 */   // GIR_Coverage, 1881,
     /* 72556 */   GIR_Done,
     /* 72557 */ // Label 1746: @72557
     /* 72557 */ GIM_Reject,
     /* 72558 */ // Label 1744: @72558
     /* 72558 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(72583), // Rule ID 1883 //
     /* 72563 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips),
     /* 72566 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 72569 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 72572 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 72576 */   // (fmaxnum_ieee:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)  =>  (MAX_D:{ *:[f64] } f64:{ *:[f64] }:$lhs, f64:{ *:[f64] }:$rhs)
     /* 72576 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_D),
     /* 72581 */   GIR_RootConstrainSelectedInstOperands,
     /* 72582 */   // GIR_Coverage, 1883,
     /* 72582 */   GIR_Done,
     /* 72583 */ // Label 1747: @72583
     /* 72583 */ GIM_Reject,
     /* 72584 */ // Label 1745: @72584
     /* 72584 */ GIM_Reject,
     /* 72585 */ // Label 66: @72585
     /* 72585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1752*/ GIMT_Encode4(72752),
     /* 72596 */ /*GILLT_v2s64*//*Label 1748*/ GIMT_Encode4(72616), GIMT_Encode4(0),
     /* 72604 */ /*GILLT_v4s32*//*Label 1749*/ GIMT_Encode4(72650),
     /* 72608 */ /*GILLT_v8s16*//*Label 1750*/ GIMT_Encode4(72684),
     /* 72612 */ /*GILLT_v16s8*//*Label 1751*/ GIMT_Encode4(72718),
     /* 72616 */ // Label 1748: @72616
     /* 72616 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(72649), // Rule ID 946 //
     /* 72621 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72624 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 72627 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 72630 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72634 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72638 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72642 */   // (smin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 72642 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_D),
     /* 72647 */   GIR_RootConstrainSelectedInstOperands,
     /* 72648 */   // GIR_Coverage, 946,
     /* 72648 */   GIR_Done,
     /* 72649 */ // Label 1753: @72649
     /* 72649 */ GIM_Reject,
     /* 72650 */ // Label 1749: @72650
     /* 72650 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(72683), // Rule ID 945 //
     /* 72655 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72658 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 72661 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 72664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72668 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72672 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72676 */   // (smin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 72676 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_W),
     /* 72681 */   GIR_RootConstrainSelectedInstOperands,
     /* 72682 */   // GIR_Coverage, 945,
     /* 72682 */   GIR_Done,
     /* 72683 */ // Label 1754: @72683
     /* 72683 */ GIM_Reject,
     /* 72684 */ // Label 1750: @72684
     /* 72684 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(72717), // Rule ID 944 //
     /* 72689 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72692 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 72695 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 72698 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72702 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72706 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72710 */   // (smin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 72710 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_H),
     /* 72715 */   GIR_RootConstrainSelectedInstOperands,
     /* 72716 */   // GIR_Coverage, 944,
     /* 72716 */   GIR_Done,
     /* 72717 */ // Label 1755: @72717
     /* 72717 */ GIM_Reject,
     /* 72718 */ // Label 1751: @72718
     /* 72718 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(72751), // Rule ID 943 //
     /* 72723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 72729 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 72732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72736 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72740 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72744 */   // (smin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 72744 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_S_B),
     /* 72749 */   GIR_RootConstrainSelectedInstOperands,
     /* 72750 */   // GIR_Coverage, 943,
     /* 72750 */   GIR_Done,
     /* 72751 */ // Label 1756: @72751
     /* 72751 */ GIM_Reject,
     /* 72752 */ // Label 1752: @72752
     /* 72752 */ GIM_Reject,
     /* 72753 */ // Label 67: @72753
     /* 72753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1761*/ GIMT_Encode4(72920),
     /* 72764 */ /*GILLT_v2s64*//*Label 1757*/ GIMT_Encode4(72784), GIMT_Encode4(0),
     /* 72772 */ /*GILLT_v4s32*//*Label 1758*/ GIMT_Encode4(72818),
     /* 72776 */ /*GILLT_v8s16*//*Label 1759*/ GIMT_Encode4(72852),
     /* 72780 */ /*GILLT_v16s8*//*Label 1760*/ GIMT_Encode4(72886),
     /* 72784 */ // Label 1757: @72784
     /* 72784 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(72817), // Rule ID 926 //
     /* 72789 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72792 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 72795 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 72798 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72802 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72806 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72810 */   // (smax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 72810 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_D),
     /* 72815 */   GIR_RootConstrainSelectedInstOperands,
     /* 72816 */   // GIR_Coverage, 926,
     /* 72816 */   GIR_Done,
     /* 72817 */ // Label 1762: @72817
     /* 72817 */ GIM_Reject,
     /* 72818 */ // Label 1758: @72818
     /* 72818 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(72851), // Rule ID 925 //
     /* 72823 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72826 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 72829 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 72832 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72836 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72840 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 72844 */   // (smax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 72844 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_W),
     /* 72849 */   GIR_RootConstrainSelectedInstOperands,
     /* 72850 */   // GIR_Coverage, 925,
     /* 72850 */   GIR_Done,
     /* 72851 */ // Label 1763: @72851
     /* 72851 */ GIM_Reject,
     /* 72852 */ // Label 1759: @72852
     /* 72852 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(72885), // Rule ID 924 //
     /* 72857 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72860 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 72863 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 72866 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72870 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72874 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 72878 */   // (smax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 72878 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_H),
     /* 72883 */   GIR_RootConstrainSelectedInstOperands,
     /* 72884 */   // GIR_Coverage, 924,
     /* 72884 */   GIR_Done,
     /* 72885 */ // Label 1764: @72885
     /* 72885 */ GIM_Reject,
     /* 72886 */ // Label 1760: @72886
     /* 72886 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(72919), // Rule ID 923 //
     /* 72891 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72894 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 72897 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 72900 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72904 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72908 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 72912 */   // (smax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 72912 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_S_B),
     /* 72917 */   GIR_RootConstrainSelectedInstOperands,
     /* 72918 */   // GIR_Coverage, 923,
     /* 72918 */   GIR_Done,
     /* 72919 */ // Label 1765: @72919
     /* 72919 */ GIM_Reject,
     /* 72920 */ // Label 1761: @72920
     /* 72920 */ GIM_Reject,
     /* 72921 */ // Label 68: @72921
     /* 72921 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1770*/ GIMT_Encode4(73088),
     /* 72932 */ /*GILLT_v2s64*//*Label 1766*/ GIMT_Encode4(72952), GIMT_Encode4(0),
     /* 72940 */ /*GILLT_v4s32*//*Label 1767*/ GIMT_Encode4(72986),
     /* 72944 */ /*GILLT_v8s16*//*Label 1768*/ GIMT_Encode4(73020),
     /* 72948 */ /*GILLT_v16s8*//*Label 1769*/ GIMT_Encode4(73054),
     /* 72952 */ // Label 1766: @72952
     /* 72952 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(72985), // Rule ID 950 //
     /* 72957 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72960 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 72963 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 72966 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72970 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72974 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 72978 */   // (umin:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MIN_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 72978 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_D),
     /* 72983 */   GIR_RootConstrainSelectedInstOperands,
     /* 72984 */   // GIR_Coverage, 950,
     /* 72984 */   GIR_Done,
     /* 72985 */ // Label 1771: @72985
     /* 72985 */ GIM_Reject,
     /* 72986 */ // Label 1767: @72986
     /* 72986 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(73019), // Rule ID 949 //
     /* 72991 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 72994 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 72997 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 73000 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73004 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73008 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73012 */   // (umin:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MIN_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 73012 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_W),
     /* 73017 */   GIR_RootConstrainSelectedInstOperands,
     /* 73018 */   // GIR_Coverage, 949,
     /* 73018 */   GIR_Done,
     /* 73019 */ // Label 1772: @73019
     /* 73019 */ GIM_Reject,
     /* 73020 */ // Label 1768: @73020
     /* 73020 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(73053), // Rule ID 948 //
     /* 73025 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73028 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 73031 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 73034 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73038 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73042 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73046 */   // (umin:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MIN_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 73046 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_H),
     /* 73051 */   GIR_RootConstrainSelectedInstOperands,
     /* 73052 */   // GIR_Coverage, 948,
     /* 73052 */   GIR_Done,
     /* 73053 */ // Label 1773: @73053
     /* 73053 */ GIM_Reject,
     /* 73054 */ // Label 1769: @73054
     /* 73054 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(73087), // Rule ID 947 //
     /* 73059 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73062 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 73065 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 73068 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73072 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73076 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73080 */   // (umin:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MIN_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 73080 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MIN_U_B),
     /* 73085 */   GIR_RootConstrainSelectedInstOperands,
     /* 73086 */   // GIR_Coverage, 947,
     /* 73086 */   GIR_Done,
     /* 73087 */ // Label 1774: @73087
     /* 73087 */ GIM_Reject,
     /* 73088 */ // Label 1770: @73088
     /* 73088 */ GIM_Reject,
     /* 73089 */ // Label 69: @73089
     /* 73089 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1779*/ GIMT_Encode4(73256),
     /* 73100 */ /*GILLT_v2s64*//*Label 1775*/ GIMT_Encode4(73120), GIMT_Encode4(0),
     /* 73108 */ /*GILLT_v4s32*//*Label 1776*/ GIMT_Encode4(73154),
     /* 73112 */ /*GILLT_v8s16*//*Label 1777*/ GIMT_Encode4(73188),
     /* 73116 */ /*GILLT_v16s8*//*Label 1778*/ GIMT_Encode4(73222),
     /* 73120 */ // Label 1775: @73120
     /* 73120 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(73153), // Rule ID 930 //
     /* 73125 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73128 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 73131 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
     /* 73134 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73138 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73142 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73146 */   // (umax:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)  =>  (MAX_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
     /* 73146 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_D),
     /* 73151 */   GIR_RootConstrainSelectedInstOperands,
     /* 73152 */   // GIR_Coverage, 930,
     /* 73152 */   GIR_Done,
     /* 73153 */ // Label 1780: @73153
     /* 73153 */ GIM_Reject,
     /* 73154 */ // Label 1776: @73154
     /* 73154 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(73187), // Rule ID 929 //
     /* 73159 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73162 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 73165 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
     /* 73168 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73172 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73176 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73180 */   // (umax:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)  =>  (MAX_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
     /* 73180 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_W),
     /* 73185 */   GIR_RootConstrainSelectedInstOperands,
     /* 73186 */   // GIR_Coverage, 929,
     /* 73186 */   GIR_Done,
     /* 73187 */ // Label 1781: @73187
     /* 73187 */ GIM_Reject,
     /* 73188 */ // Label 1777: @73188
     /* 73188 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(73221), // Rule ID 928 //
     /* 73193 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73196 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 73199 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
     /* 73202 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73206 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73210 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73214 */   // (umax:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)  =>  (MAX_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
     /* 73214 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_H),
     /* 73219 */   GIR_RootConstrainSelectedInstOperands,
     /* 73220 */   // GIR_Coverage, 928,
     /* 73220 */   GIR_Done,
     /* 73221 */ // Label 1782: @73221
     /* 73221 */ GIM_Reject,
     /* 73222 */ // Label 1778: @73222
     /* 73222 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(73255), // Rule ID 927 //
     /* 73227 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73230 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 73233 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
     /* 73236 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73240 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73244 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73248 */   // (umax:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)  =>  (MAX_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
     /* 73248 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::MAX_U_B),
     /* 73253 */   GIR_RootConstrainSelectedInstOperands,
     /* 73254 */   // GIR_Coverage, 927,
     /* 73254 */   GIR_Done,
     /* 73255 */ // Label 1783: @73255
     /* 73255 */ GIM_Reject,
     /* 73256 */ // Label 1779: @73256
     /* 73256 */ GIM_Reject,
     /* 73257 */ // Label 70: @73257
     /* 73257 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(73380),
     /* 73262 */   GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
     /* 73265 */   GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(73286), // Rule ID 91 //
     /* 73270 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC),
     /* 73273 */     // (br (bb:{ *:[Other] }):$target)  =>  (J (bb:{ *:[Other] }):$target)
     /* 73273 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J),
     /* 73278 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
     /* 73284 */     GIR_RootConstrainSelectedInstOperands,
     /* 73285 */     // GIR_Coverage, 91,
     /* 73285 */     GIR_Done,
     /* 73286 */   // Label 1785: @73286
     /* 73286 */   GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(73307), // Rule ID 98 //
     /* 73291 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 73294 */     // (br (bb:{ *:[Other] }):$offset)  =>  (B (bb:{ *:[Other] }):$offset)
     /* 73294 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B),
     /* 73299 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
     /* 73305 */     GIR_RootConstrainSelectedInstOperands,
     /* 73306 */     // GIR_Coverage, 98,
     /* 73306 */     GIR_Done,
     /* 73307 */   // Label 1786: @73307
     /* 73307 */   GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(73328), // Rule ID 1179 //
     /* 73312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocNotPIC),
     /* 73315 */     // (br (bb:{ *:[Other] }):$target)  =>  (J_MM (bb:{ *:[Other] }):$target)
     /* 73315 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::J_MM),
     /* 73320 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
     /* 73326 */     GIR_RootConstrainSelectedInstOperands,
     /* 73327 */     // GIR_Coverage, 1179,
     /* 73327 */     GIR_Done,
     /* 73328 */   // Label 1787: @73328
     /* 73328 */   GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(73349), // Rule ID 1188 //
     /* 73333 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_NotMips32r6_RelocPIC),
     /* 73336 */     // (br (bb:{ *:[Other] }):$offset)  =>  (B_MM (bb:{ *:[Other] }):$offset)
     /* 73336 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::B_MM),
     /* 73341 */     GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(Mips::AT), GIMT_Encode2(RegState::Dead),
     /* 73347 */     GIR_RootConstrainSelectedInstOperands,
     /* 73348 */     // GIR_Coverage, 1188,
     /* 73348 */     GIR_Done,
     /* 73349 */   // Label 1788: @73349
     /* 73349 */   GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(73364), // Rule ID 1246 //
     /* 73354 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_InMicroMips),
     /* 73357 */     // (br (bb:{ *:[Other] }):$offset)  =>  (BC_MMR6 (bb:{ *:[Other] }):$offset)
     /* 73357 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::BC_MMR6),
     /* 73362 */     GIR_RootConstrainSelectedInstOperands,
     /* 73363 */     // GIR_Coverage, 1246,
     /* 73363 */     GIR_Done,
     /* 73364 */   // Label 1789: @73364
     /* 73364 */   GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(73379), // Rule ID 1994 //
     /* 73369 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 73372 */     // (br (bb:{ *:[Other] }):$imm16)  =>  (Bimm16 (bb:{ *:[Other] }):$imm16)
     /* 73372 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Bimm16),
     /* 73377 */     GIR_RootConstrainSelectedInstOperands,
     /* 73378 */     // GIR_Coverage, 1994,
     /* 73378 */     GIR_Done,
     /* 73379 */   // Label 1790: @73379
     /* 73379 */   GIM_Reject,
     /* 73380 */ // Label 1784: @73380
     /* 73380 */ GIM_Reject,
     /* 73381 */ // Label 71: @73381
     /* 73381 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(9), /*)*//*default:*//*Label 1795*/ GIMT_Encode4(73944),
     /* 73392 */ /*GILLT_v2s64*//*Label 1791*/ GIMT_Encode4(73412), GIMT_Encode4(0),
     /* 73400 */ /*GILLT_v4s32*//*Label 1792*/ GIMT_Encode4(73585),
     /* 73404 */ /*GILLT_v8s16*//*Label 1793*/ GIMT_Encode4(73758),
     /* 73408 */ /*GILLT_v16s8*//*Label 1794*/ GIMT_Encode4(73851),
     /* 73412 */ // Label 1791: @73412
     /* 73412 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(73584),
     /* 73417 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 73420 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 73423 */   GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(73463), // Rule ID 896 //
     /* 73428 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73431 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73434 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73438 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73442 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73446 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73450 */     // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_D_VIDX_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
     /* 73450 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX_PSEUDO),
     /* 73453 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73455 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73457 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73459 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73461 */     GIR_RootConstrainSelectedInstOperands,
     /* 73462 */     // GIR_Coverage, 896,
     /* 73462 */     GIR_EraseRootFromParent_Done,
     /* 73463 */   // Label 1797: @73463
     /* 73463 */   GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(73503), // Rule ID 898 //
     /* 73468 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73471 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73474 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73478 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73482 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 73486 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73490 */     // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_FD_VIDX_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
     /* 73490 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX_PSEUDO),
     /* 73493 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73495 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73497 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73499 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73501 */     GIR_RootConstrainSelectedInstOperands,
     /* 73502 */     // GIR_Coverage, 898,
     /* 73502 */     GIR_EraseRootFromParent_Done,
     /* 73503 */   // Label 1798: @73503
     /* 73503 */   GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(73543), // Rule ID 902 //
     /* 73508 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73511 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73514 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73518 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73522 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73526 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73530 */     // (vector_insert:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_D_VIDX64_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR64Opnd:{ *:[i64] }:$fs)
     /* 73530 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_D_VIDX64_PSEUDO),
     /* 73533 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73535 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73537 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73539 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73541 */     GIR_RootConstrainSelectedInstOperands,
     /* 73542 */     // GIR_Coverage, 902,
     /* 73542 */     GIR_EraseRootFromParent_Done,
     /* 73543 */   // Label 1799: @73543
     /* 73543 */   GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(73583), // Rule ID 904 //
     /* 73548 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73551 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73554 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73558 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 73562 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 73566 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73570 */     // (vector_insert:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, FGR64Opnd:{ *:[f64] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_FD_VIDX64_PSEUDO:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR64Opnd:{ *:[f64] }:$fs)
     /* 73570 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FD_VIDX64_PSEUDO),
     /* 73573 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73575 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73577 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73579 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73581 */     GIR_RootConstrainSelectedInstOperands,
     /* 73582 */     // GIR_Coverage, 904,
     /* 73582 */     GIR_EraseRootFromParent_Done,
     /* 73583 */   // Label 1800: @73583
     /* 73583 */   GIM_Reject,
     /* 73584 */ // Label 1796: @73584
     /* 73584 */ GIM_Reject,
     /* 73585 */ // Label 1792: @73585
     /* 73585 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(73757),
     /* 73590 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 73593 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 73596 */   GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(73636), // Rule ID 895 //
     /* 73601 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73604 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73607 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73611 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73619 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73623 */     // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_W_VIDX_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73623 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX_PSEUDO),
     /* 73626 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73628 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73630 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73632 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73634 */     GIR_RootConstrainSelectedInstOperands,
     /* 73635 */     // GIR_Coverage, 895,
     /* 73635 */     GIR_EraseRootFromParent_Done,
     /* 73636 */   // Label 1802: @73636
     /* 73636 */   GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(73676), // Rule ID 897 //
     /* 73641 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73644 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73647 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73651 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73655 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 73659 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73663 */     // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_FW_VIDX_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
     /* 73663 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX_PSEUDO),
     /* 73666 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73668 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73670 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73672 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73674 */     GIR_RootConstrainSelectedInstOperands,
     /* 73675 */     // GIR_Coverage, 897,
     /* 73675 */     GIR_EraseRootFromParent_Done,
     /* 73676 */   // Label 1803: @73676
     /* 73676 */   GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(73716), // Rule ID 901 //
     /* 73681 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73684 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73687 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73691 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73695 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73699 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73703 */     // (vector_insert:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_W_VIDX64_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73703 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_W_VIDX64_PSEUDO),
     /* 73706 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73708 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73710 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73712 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73714 */     GIR_RootConstrainSelectedInstOperands,
     /* 73715 */     // GIR_Coverage, 901,
     /* 73715 */     GIR_EraseRootFromParent_Done,
     /* 73716 */   // Label 1804: @73716
     /* 73716 */   GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(73756), // Rule ID 903 //
     /* 73721 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73724 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73727 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73731 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73735 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 73739 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73743 */     // (vector_insert:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, FGR32Opnd:{ *:[f32] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_FW_VIDX64_PSEUDO:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, FGR32Opnd:{ *:[f32] }:$fs)
     /* 73743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_FW_VIDX64_PSEUDO),
     /* 73746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73748 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73750 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73752 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73754 */     GIR_RootConstrainSelectedInstOperands,
     /* 73755 */     // GIR_Coverage, 903,
     /* 73755 */     GIR_EraseRootFromParent_Done,
     /* 73756 */   // Label 1805: @73756
     /* 73756 */   GIM_Reject,
     /* 73757 */ // Label 1801: @73757
     /* 73757 */ GIM_Reject,
     /* 73758 */ // Label 1793: @73758
     /* 73758 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(73850),
     /* 73763 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 73766 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 73769 */   GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(73809), // Rule ID 894 //
     /* 73774 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73777 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73780 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73784 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73788 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73792 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73796 */     // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_H_VIDX_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73796 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX_PSEUDO),
     /* 73799 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73801 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73803 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73805 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73807 */     GIR_RootConstrainSelectedInstOperands,
     /* 73808 */     // GIR_Coverage, 894,
     /* 73808 */     GIR_EraseRootFromParent_Done,
     /* 73809 */   // Label 1807: @73809
     /* 73809 */   GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(73849), // Rule ID 900 //
     /* 73814 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73817 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73820 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73824 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 73828 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73832 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73836 */     // (vector_insert:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_H_VIDX64_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73836 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_H_VIDX64_PSEUDO),
     /* 73839 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73841 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73843 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73845 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73847 */     GIR_RootConstrainSelectedInstOperands,
     /* 73848 */     // GIR_Coverage, 900,
     /* 73848 */     GIR_EraseRootFromParent_Done,
     /* 73849 */   // Label 1808: @73849
     /* 73849 */   GIM_Reject,
     /* 73850 */ // Label 1806: @73850
     /* 73850 */ GIM_Reject,
     /* 73851 */ // Label 1794: @73851
     /* 73851 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(73943),
     /* 73856 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 73859 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 73862 */   GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(73902), // Rule ID 893 //
     /* 73867 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73870 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
     /* 73873 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73877 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73881 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73885 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73889 */     // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR32Opnd:{ *:[i32] }:$n)  =>  (INSERT_B_VIDX_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73889 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX_PSEUDO),
     /* 73892 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73894 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73896 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73898 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73900 */     GIR_RootConstrainSelectedInstOperands,
     /* 73901 */     // GIR_Coverage, 893,
     /* 73901 */     GIR_EraseRootFromParent_Done,
     /* 73902 */   // Label 1810: @73902
     /* 73902 */   GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(73942), // Rule ID 899 //
     /* 73907 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 73910 */     GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
     /* 73913 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73917 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 73921 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73925 */     GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 73929 */     // (vector_insert:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR32Opnd:{ *:[i32] }:$fs, GPR64Opnd:{ *:[i64] }:$n)  =>  (INSERT_B_VIDX64_PSEUDO:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, GPR64Opnd:{ *:[i64] }:$n, GPR32Opnd:{ *:[i32] }:$fs)
     /* 73929 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::INSERT_B_VIDX64_PSEUDO),
     /* 73932 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wd]
     /* 73934 */     GIR_RootToRootCopy, /*OpIdx*/1, // wd_in
     /* 73936 */     GIR_RootToRootCopy, /*OpIdx*/3, // n
     /* 73938 */     GIR_RootToRootCopy, /*OpIdx*/2, // fs
     /* 73940 */     GIR_RootConstrainSelectedInstOperands,
     /* 73941 */     // GIR_Coverage, 899,
     /* 73941 */     GIR_EraseRootFromParent_Done,
     /* 73942 */   // Label 1811: @73942
     /* 73942 */   GIM_Reject,
     /* 73943 */ // Label 1809: @73943
     /* 73943 */ GIM_Reject,
     /* 73944 */ // Label 1795: @73944
     /* 73944 */ GIM_Reject,
     /* 73945 */ // Label 72: @73945
     /* 73945 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(73996), // Rule ID 2121 //
     /* 73950 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA),
     /* 73953 */   GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
     /* 73956 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 73959 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 73962 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 73966 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 73970 */   GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 73974 */   GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
     /* 73978 */   GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_immZExt4),
     /* 73982 */   // MIs[1] Operand 1
     /* 73982 */   // No operand predicates
     /* 73982 */   GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 73984 */   // (extractelt:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)  =>  (COPY_S_W:{ *:[i32] } MSA128W:{ *:[v4i32] }:$ws, (imm:{ *:[i32] })<<P:Predicate_immZExt4>>:$idx)
     /* 73984 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::COPY_S_W),
     /* 73987 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 73989 */   GIR_RootToRootCopy, /*OpIdx*/1, // ws
     /* 73991 */   GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // idx
     /* 73994 */   GIR_RootConstrainSelectedInstOperands,
     /* 73995 */   // GIR_Coverage, 2121,
     /* 73995 */   GIR_EraseRootFromParent_Done,
     /* 73996 */ // Label 1812: @73996
     /* 73996 */ GIM_Reject,
     /* 73997 */ // Label 73: @73997
     /* 73997 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1819*/ GIMT_Encode4(74501),
     /* 74008 */ /*GILLT_s32*//*Label 1813*/ GIMT_Encode4(74040),
     /* 74012 */ /*GILLT_s64*//*Label 1814*/ GIMT_Encode4(74249), GIMT_Encode4(0),
     /* 74020 */ /*GILLT_v2s64*//*Label 1815*/ GIMT_Encode4(74393), GIMT_Encode4(0),
     /* 74028 */ /*GILLT_v4s32*//*Label 1816*/ GIMT_Encode4(74420),
     /* 74032 */ /*GILLT_v8s16*//*Label 1817*/ GIMT_Encode4(74447),
     /* 74036 */ /*GILLT_v16s8*//*Label 1818*/ GIMT_Encode4(74474),
     /* 74040 */ // Label 1813: @74040
     /* 74040 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(74248),
     /* 74045 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 74048 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74052 */   GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(74098), // Rule ID 109 //
     /* 74057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 74060 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 74064 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 74068 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 74072 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 74076 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74081 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /* 74085 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 74087 */     // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74087 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO),
     /* 74090 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74092 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /* 74096 */     GIR_RootConstrainSelectedInstOperands,
     /* 74097 */     // GIR_Coverage, 109,
     /* 74097 */     GIR_EraseRootFromParent_Done,
     /* 74098 */   // Label 1821: @74098
     /* 74098 */   GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(74144), // Rule ID 385 //
     /* 74103 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
     /* 74106 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 74110 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 74114 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 74118 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 74122 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74127 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /* 74131 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 74133 */     // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74133 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_R6),
     /* 74136 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74138 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /* 74142 */     GIR_RootConstrainSelectedInstOperands,
     /* 74143 */     // GIR_Coverage, 385,
     /* 74143 */     GIR_EraseRootFromParent_Done,
     /* 74144 */   // Label 1822: @74144
     /* 74144 */   GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(74190), // Rule ID 1175 //
     /* 74149 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 74152 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 74156 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 74160 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 74164 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 74168 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74173 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /* 74177 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 74179 */     // (ctlz:{ *:[i32] } (xor:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, -1:{ *:[i32] }))  =>  (CLO_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74179 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::CLO_MM),
     /* 74182 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74184 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /* 74188 */     GIR_RootConstrainSelectedInstOperands,
     /* 74189 */     // GIR_Coverage, 1175,
     /* 74189 */     GIR_EraseRootFromParent_Done,
     /* 74190 */   // Label 1823: @74190
     /* 74190 */   GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(74209), // Rule ID 108 //
     /* 74195 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 74198 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74202 */     // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74202 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ),
     /* 74207 */     GIR_RootConstrainSelectedInstOperands,
     /* 74208 */     // GIR_Coverage, 108,
     /* 74208 */     GIR_Done,
     /* 74209 */   // Label 1824: @74209
     /* 74209 */   GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(74228), // Rule ID 386 //
     /* 74214 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r6_HasStdEnc),
     /* 74217 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74221 */     // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74221 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_R6),
     /* 74226 */     GIR_RootConstrainSelectedInstOperands,
     /* 74227 */     // GIR_Coverage, 386,
     /* 74227 */     GIR_Done,
     /* 74228 */   // Label 1825: @74228
     /* 74228 */   GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(74247), // Rule ID 1174 //
     /* 74233 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 74236 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74240 */     // (ctlz:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (CLZ_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74240 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::CLZ_MM),
     /* 74245 */     GIR_RootConstrainSelectedInstOperands,
     /* 74246 */     // GIR_Coverage, 1174,
     /* 74246 */     GIR_Done,
     /* 74247 */   // Label 1826: @74247
     /* 74247 */   GIM_Reject,
     /* 74248 */ // Label 1820: @74248
     /* 74248 */ GIM_Reject,
     /* 74249 */ // Label 1814: @74249
     /* 74249 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(74392),
     /* 74254 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 74257 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74261 */   GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(74307), // Rule ID 339 //
     /* 74266 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
     /* 74269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 74273 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 74277 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 74281 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 74285 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74290 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /* 74294 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 74296 */     // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /* 74296 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO),
     /* 74299 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74301 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /* 74305 */     GIR_RootConstrainSelectedInstOperands,
     /* 74306 */     // GIR_Coverage, 339,
     /* 74306 */     GIR_EraseRootFromParent_Done,
     /* 74307 */   // Label 1828: @74307
     /* 74307 */   GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(74353), // Rule ID 414 //
     /* 74312 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /* 74315 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 74319 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
     /* 74323 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 74327 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 74331 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74336 */     GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
     /* 74340 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 74342 */     // (ctlz:{ *:[i64] } (xor:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, -1:{ *:[i64] }))  =>  (DCLO_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /* 74342 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DCLO_R6),
     /* 74345 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74347 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
     /* 74351 */     GIR_RootConstrainSelectedInstOperands,
     /* 74352 */     // GIR_Coverage, 414,
     /* 74352 */     GIR_EraseRootFromParent_Done,
     /* 74353 */   // Label 1829: @74353
     /* 74353 */   GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(74372), // Rule ID 338 //
     /* 74358 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6),
     /* 74361 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74365 */     // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /* 74365 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ),
     /* 74370 */     GIR_RootConstrainSelectedInstOperands,
     /* 74371 */     // GIR_Coverage, 338,
     /* 74371 */     GIR_Done,
     /* 74372 */   // Label 1830: @74372
     /* 74372 */   GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(74391), // Rule ID 415 //
     /* 74377 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips),
     /* 74380 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74384 */     // (ctlz:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DCLZ_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /* 74384 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DCLZ_R6),
     /* 74389 */     GIR_RootConstrainSelectedInstOperands,
     /* 74390 */     // GIR_Coverage, 415,
     /* 74390 */     GIR_Done,
     /* 74391 */   // Label 1831: @74391
     /* 74391 */   GIM_Reject,
     /* 74392 */ // Label 1827: @74392
     /* 74392 */ GIM_Reject,
     /* 74393 */ // Label 1815: @74393
     /* 74393 */ GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(74419), // Rule ID 990 //
     /* 74398 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74401 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 74404 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 74408 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 74412 */   // (ctlz:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (NLZC_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
     /* 74412 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_D),
     /* 74417 */   GIR_RootConstrainSelectedInstOperands,
     /* 74418 */   // GIR_Coverage, 990,
     /* 74418 */   GIR_Done,
     /* 74419 */ // Label 1832: @74419
     /* 74419 */ GIM_Reject,
     /* 74420 */ // Label 1816: @74420
     /* 74420 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(74446), // Rule ID 989 //
     /* 74425 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74428 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 74431 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 74435 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 74439 */   // (ctlz:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (NLZC_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 74439 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_W),
     /* 74444 */   GIR_RootConstrainSelectedInstOperands,
     /* 74445 */   // GIR_Coverage, 989,
     /* 74445 */   GIR_Done,
     /* 74446 */ // Label 1833: @74446
     /* 74446 */ GIM_Reject,
     /* 74447 */ // Label 1817: @74447
     /* 74447 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(74473), // Rule ID 988 //
     /* 74452 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74455 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 74458 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 74462 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 74466 */   // (ctlz:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (NLZC_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
     /* 74466 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_H),
     /* 74471 */   GIR_RootConstrainSelectedInstOperands,
     /* 74472 */   // GIR_Coverage, 988,
     /* 74472 */   GIR_Done,
     /* 74473 */ // Label 1834: @74473
     /* 74473 */ GIM_Reject,
     /* 74474 */ // Label 1818: @74474
     /* 74474 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(74500), // Rule ID 987 //
     /* 74479 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74482 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 74485 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 74489 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 74493 */   // (ctlz:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (NLZC_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
     /* 74493 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::NLZC_B),
     /* 74498 */   GIR_RootConstrainSelectedInstOperands,
     /* 74499 */   // GIR_Coverage, 987,
     /* 74499 */   GIR_Done,
     /* 74500 */ // Label 1835: @74500
     /* 74500 */ GIM_Reject,
     /* 74501 */ // Label 1819: @74501
     /* 74501 */ GIM_Reject,
     /* 74502 */ // Label 74: @74502
     /* 74502 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 1842*/ GIMT_Encode4(74707),
     /* 74513 */ /*GILLT_s32*//*Label 1836*/ GIMT_Encode4(74545),
     /* 74517 */ /*GILLT_s64*//*Label 1837*/ GIMT_Encode4(74572), GIMT_Encode4(0),
     /* 74525 */ /*GILLT_v2s64*//*Label 1838*/ GIMT_Encode4(74599), GIMT_Encode4(0),
     /* 74533 */ /*GILLT_v4s32*//*Label 1839*/ GIMT_Encode4(74626),
     /* 74537 */ /*GILLT_v8s16*//*Label 1840*/ GIMT_Encode4(74653),
     /* 74541 */ /*GILLT_v16s8*//*Label 1841*/ GIMT_Encode4(74680),
     /* 74545 */ // Label 1836: @74545
     /* 74545 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(74571), // Rule ID 353 //
     /* 74550 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 74553 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 74556 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74560 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74564 */   // (ctpop:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)  =>  (POP:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs)
     /* 74564 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::POP),
     /* 74569 */   GIR_RootConstrainSelectedInstOperands,
     /* 74570 */   // GIR_Coverage, 353,
     /* 74570 */   GIR_Done,
     /* 74571 */ // Label 1843: @74571
     /* 74571 */ GIM_Reject,
     /* 74572 */ // Label 1837: @74572
     /* 74572 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(74598), // Rule ID 354 //
     /* 74577 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCnMips),
     /* 74580 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 74583 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74587 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74591 */   // (ctpop:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)  =>  (DPOP:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs)
     /* 74591 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::DPOP),
     /* 74596 */   GIR_RootConstrainSelectedInstOperands,
     /* 74597 */   // GIR_Coverage, 354,
     /* 74597 */   GIR_Done,
     /* 74598 */ // Label 1844: @74598
     /* 74598 */ GIM_Reject,
     /* 74599 */ // Label 1838: @74599
     /* 74599 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(74625), // Rule ID 1012 //
     /* 74604 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74607 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 74610 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 74614 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 74618 */   // (ctpop:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)  =>  (PCNT_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws)
     /* 74618 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_D),
     /* 74623 */   GIR_RootConstrainSelectedInstOperands,
     /* 74624 */   // GIR_Coverage, 1012,
     /* 74624 */   GIR_Done,
     /* 74625 */ // Label 1845: @74625
     /* 74625 */ GIM_Reject,
     /* 74626 */ // Label 1839: @74626
     /* 74626 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(74652), // Rule ID 1011 //
     /* 74631 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74634 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 74637 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 74641 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 74645 */   // (ctpop:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)  =>  (PCNT_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws)
     /* 74645 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_W),
     /* 74650 */   GIR_RootConstrainSelectedInstOperands,
     /* 74651 */   // GIR_Coverage, 1011,
     /* 74651 */   GIR_Done,
     /* 74652 */ // Label 1846: @74652
     /* 74652 */ GIM_Reject,
     /* 74653 */ // Label 1840: @74653
     /* 74653 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(74679), // Rule ID 1010 //
     /* 74658 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74661 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
     /* 74664 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 74668 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128HRegClassID),
     /* 74672 */   // (ctpop:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)  =>  (PCNT_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws)
     /* 74672 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_H),
     /* 74677 */   GIR_RootConstrainSelectedInstOperands,
     /* 74678 */   // GIR_Coverage, 1010,
     /* 74678 */   GIR_Done,
     /* 74679 */ // Label 1847: @74679
     /* 74679 */ GIM_Reject,
     /* 74680 */ // Label 1841: @74680
     /* 74680 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(74706), // Rule ID 1009 //
     /* 74685 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 74688 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
     /* 74691 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 74695 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128BRegClassID),
     /* 74699 */   // (ctpop:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)  =>  (PCNT_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws)
     /* 74699 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::PCNT_B),
     /* 74704 */   GIR_RootConstrainSelectedInstOperands,
     /* 74705 */   // GIR_Coverage, 1009,
     /* 74705 */   GIR_Done,
     /* 74706 */ // Label 1848: @74706
     /* 74706 */ GIM_Reject,
     /* 74707 */ // Label 1842: @74707
     /* 74707 */ GIM_Reject,
     /* 74708 */ // Label 75: @74708
     /* 74708 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1851*/ GIMT_Encode4(74871),
     /* 74719 */ /*GILLT_s32*//*Label 1849*/ GIMT_Encode4(74727),
     /* 74723 */ /*GILLT_s64*//*Label 1850*/ GIMT_Encode4(74823),
     /* 74727 */ // Label 1849: @74727
     /* 74727 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(74822),
     /* 74732 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 74735 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74739 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR32RegClassID),
     /* 74743 */   GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(74782), // Rule ID 1502 //
     /* 74748 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips),
     /* 74751 */     // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR:{ *:[i32] } (WSBH:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
     /* 74751 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 74754 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH),
     /* 74758 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 74763 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
     /* 74767 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 74769 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR),
     /* 74772 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74774 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 74777 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /* 74780 */     GIR_RootConstrainSelectedInstOperands,
     /* 74781 */     // GIR_Coverage, 1502,
     /* 74781 */     GIR_EraseRootFromParent_Done,
     /* 74782 */   // Label 1853: @74782
     /* 74782 */   GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(74821), // Rule ID 2318 //
     /* 74787 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 74790 */     // (bswap:{ *:[i32] } GPR32:{ *:[i32] }:$rt)  =>  (ROTR_MM:{ *:[i32] } (WSBH_MM:{ *:[i32] } GPR32:{ *:[i32] }:$rt), 16:{ *:[i32] })
     /* 74790 */     GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
     /* 74793 */     GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::WSBH_MM),
     /* 74797 */     GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 74802 */     GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
     /* 74806 */     GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 74808 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::ROTR_MM),
     /* 74811 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74813 */     GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 74816 */     GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
     /* 74819 */     GIR_RootConstrainSelectedInstOperands,
     /* 74820 */     // GIR_Coverage, 2318,
     /* 74820 */     GIR_EraseRootFromParent_Done,
     /* 74821 */   // Label 1854: @74821
     /* 74821 */   GIM_Reject,
     /* 74822 */ // Label 1852: @74822
     /* 74822 */ GIM_Reject,
     /* 74823 */ // Label 1850: @74823
     /* 74823 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(74870), // Rule ID 1692 //
     /* 74828 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips64r2_HasStdEnc),
     /* 74831 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 74834 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74838 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::GPR64RegClassID),
     /* 74842 */   // (bswap:{ *:[i64] } GPR64:{ *:[i64] }:$rt)  =>  (DSHD:{ *:[i64] } (DSBH:{ *:[i64] } GPR64:{ *:[i64] }:$rt))
     /* 74842 */   GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
     /* 74845 */   GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(Mips::DSBH),
     /* 74849 */   GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
     /* 74854 */   GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rt
     /* 74858 */   GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
     /* 74860 */   GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::DSHD),
     /* 74863 */   GIR_RootToRootCopy, /*OpIdx*/0, // DstI[rd]
     /* 74865 */   GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
     /* 74868 */   GIR_RootConstrainSelectedInstOperands,
     /* 74869 */   // GIR_Coverage, 1692,
     /* 74869 */   GIR_EraseRootFromParent_Done,
     /* 74870 */ // Label 1855: @74870
     /* 74870 */ GIM_Reject,
     /* 74871 */ // Label 1851: @74871
     /* 74871 */ GIM_Reject,
     /* 74872 */ // Label 76: @74872
     /* 74872 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(7), /*)*//*default:*//*Label 1860*/ GIMT_Encode4(75135),
     /* 74883 */ /*GILLT_s32*//*Label 1856*/ GIMT_Encode4(74907),
     /* 74887 */ /*GILLT_s64*//*Label 1857*/ GIMT_Encode4(74963), GIMT_Encode4(0),
     /* 74895 */ /*GILLT_v2s64*//*Label 1858*/ GIMT_Encode4(75081), GIMT_Encode4(0),
     /* 74903 */ /*GILLT_v4s32*//*Label 1859*/ GIMT_Encode4(75108),
     /* 74907 */ // Label 1856: @74907
     /* 74907 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(74962),
     /* 74912 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 74915 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 74919 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 74923 */   GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(74942), // Rule ID 133 //
     /* 74928 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 74931 */     // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 74931 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
     /* 74936 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 74940 */     GIR_RootConstrainSelectedInstOperands,
     /* 74941 */     // GIR_Coverage, 133,
     /* 74941 */     GIR_Done,
     /* 74942 */   // Label 1862: @74942
     /* 74942 */   GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(74961), // Rule ID 1237 //
     /* 74947 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat),
     /* 74950 */     // (fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S_MM:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 74950 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S_MM),
     /* 74955 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 74959 */     GIR_RootConstrainSelectedInstOperands,
     /* 74960 */     // GIR_Coverage, 1237,
     /* 74960 */     GIR_Done,
     /* 74961 */   // Label 1863: @74961
     /* 74961 */   GIM_Reject,
     /* 74962 */ // Label 1861: @74962
     /* 74962 */ GIM_Reject,
     /* 74963 */ // Label 1857: @74963
     /* 74963 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(75080),
     /* 74968 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 74971 */   GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(74998), // Rule ID 135 //
     /* 74976 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 74979 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 74983 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 74987 */     // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 74987 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
     /* 74992 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 74996 */     GIR_RootConstrainSelectedInstOperands,
     /* 74997 */     // GIR_Coverage, 135,
     /* 74997 */     GIR_Done,
     /* 74998 */   // Label 1865: @74998
     /* 74998 */   GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(75025), // Rule ID 137 //
     /* 75003 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 75006 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75010 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75014 */     // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 75014 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
     /* 75019 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 75023 */     GIR_RootConstrainSelectedInstOperands,
     /* 75024 */     // GIR_Coverage, 137,
     /* 75024 */     GIR_Done,
     /* 75025 */   // Label 1866: @75025
     /* 75025 */   GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(75052), // Rule ID 1223 //
     /* 75030 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit),
     /* 75033 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75037 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75041 */     // (fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32_MM:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 75041 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32_MM),
     /* 75046 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 75050 */     GIR_RootConstrainSelectedInstOperands,
     /* 75051 */     // GIR_Coverage, 1223,
     /* 75051 */     GIR_Done,
     /* 75052 */   // Label 1867: @75052
     /* 75052 */   GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(75079), // Rule ID 1224 //
     /* 75057 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat),
     /* 75060 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75064 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75068 */     // (fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64_MM:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 75068 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64_MM),
     /* 75073 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 75077 */     GIR_RootConstrainSelectedInstOperands,
     /* 75078 */     // GIR_Coverage, 1224,
     /* 75078 */     GIR_Done,
     /* 75079 */   // Label 1868: @75079
     /* 75079 */   GIM_Reject,
     /* 75080 */ // Label 1864: @75080
     /* 75080 */ GIM_Reject,
     /* 75081 */ // Label 1858: @75081
     /* 75081 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(75107), // Rule ID 832 //
     /* 75086 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 75089 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 75092 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 75096 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 75100 */   // (fsqrt:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FSQRT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 75100 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D),
     /* 75105 */   GIR_RootConstrainSelectedInstOperands,
     /* 75106 */   // GIR_Coverage, 832,
     /* 75106 */   GIR_Done,
     /* 75107 */ // Label 1869: @75107
     /* 75107 */ GIM_Reject,
     /* 75108 */ // Label 1859: @75108
     /* 75108 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(75134), // Rule ID 831 //
     /* 75113 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 75116 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 75119 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 75123 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 75127 */   // (fsqrt:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FSQRT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 75127 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_W),
     /* 75132 */   GIR_RootConstrainSelectedInstOperands,
     /* 75133 */   // GIR_Coverage, 831,
     /* 75133 */   GIR_Done,
     /* 75134 */ // Label 1870: @75134
     /* 75134 */ GIM_Reject,
     /* 75135 */ // Label 1860: @75135
     /* 75135 */ GIM_Reject,
     /* 75136 */ // Label 77: @75136
     /* 75136 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(7), /*)*//*default:*//*Label 1873*/ GIMT_Encode4(75213),
     /* 75147 */ /*GILLT_v2s64*//*Label 1871*/ GIMT_Encode4(75159), GIMT_Encode4(0),
     /* 75155 */ /*GILLT_v4s32*//*Label 1872*/ GIMT_Encode4(75186),
     /* 75159 */ // Label 1871: @75159
     /* 75159 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(75185), // Rule ID 814 //
     /* 75164 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 75167 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
     /* 75170 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 75174 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128DRegClassID),
     /* 75178 */   // (frint:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)  =>  (FRINT_D:{ *:[v2f64] } MSA128DOpnd:{ *:[v2f64] }:$ws)
     /* 75178 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_D),
     /* 75183 */   GIR_RootConstrainSelectedInstOperands,
     /* 75184 */   // GIR_Coverage, 814,
     /* 75184 */   GIR_Done,
     /* 75185 */ // Label 1874: @75185
     /* 75185 */ GIM_Reject,
     /* 75186 */ // Label 1872: @75186
     /* 75186 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(75212), // Rule ID 813 //
     /* 75191 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMSA_HasStdEnc),
     /* 75194 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
     /* 75197 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 75201 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::MSA128WRegClassID),
     /* 75205 */   // (frint:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)  =>  (FRINT_W:{ *:[v4f32] } MSA128WOpnd:{ *:[v4f32] }:$ws)
     /* 75205 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FRINT_W),
     /* 75210 */   GIR_RootConstrainSelectedInstOperands,
     /* 75211 */   // GIR_Coverage, 813,
     /* 75211 */   GIR_Done,
     /* 75212 */ // Label 1875: @75212
     /* 75212 */ GIM_Reject,
     /* 75213 */ // Label 1873: @75213
     /* 75213 */ GIM_Reject,
     /* 75214 */ // Label 78: @75214
     /* 75214 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1878*/ GIMT_Encode4(76068),
     /* 75225 */ /*GILLT_s32*//*Label 1876*/ GIMT_Encode4(75233),
     /* 75229 */ /*GILLT_s64*//*Label 1877*/ GIMT_Encode4(75505),
     /* 75233 */ // Label 1876: @75233
     /* 75233 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(75504),
     /* 75238 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 75241 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 75244 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75248 */   GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(75305), // Rule ID 179 //
     /* 75253 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75256 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75260 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75264 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 75268 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 75272 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75277 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75282 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75286 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75288 */     // (strict_fadd:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 75288 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 75291 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75293 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75295 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75299 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75303 */     GIR_RootConstrainSelectedInstOperands,
     /* 75304 */     // GIR_Coverage, 179,
     /* 75304 */     GIR_EraseRootFromParent_Done,
     /* 75305 */   // Label 1880: @75305
     /* 75305 */   GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(75362), // Rule ID 178 //
     /* 75310 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75313 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75317 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75321 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 75325 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 75329 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75334 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75339 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75343 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75345 */     // (strict_fadd:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 75345 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 75348 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75350 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75352 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75356 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75360 */     GIR_RootConstrainSelectedInstOperands,
     /* 75361 */     // GIR_Coverage, 178,
     /* 75361 */     GIR_EraseRootFromParent_Done,
     /* 75362 */   // Label 1881: @75362
     /* 75362 */   GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(75419), // Rule ID 2488 //
     /* 75367 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75370 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75374 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75378 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75382 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 75386 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 75390 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75395 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75400 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75402 */     // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 75402 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 75405 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75407 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75409 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75413 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75417 */     GIR_RootConstrainSelectedInstOperands,
     /* 75418 */     // GIR_Coverage, 2488,
     /* 75418 */     GIR_EraseRootFromParent_Done,
     /* 75419 */   // Label 1882: @75419
     /* 75419 */   GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(75476), // Rule ID 2487 //
     /* 75424 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75427 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75431 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75435 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75439 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 75443 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 75447 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75452 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75457 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75459 */     // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft))  =>  (MADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 75459 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_S),
     /* 75462 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75464 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75466 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75470 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75474 */     GIR_RootConstrainSelectedInstOperands,
     /* 75475 */     // GIR_Coverage, 2487,
     /* 75475 */     GIR_EraseRootFromParent_Done,
     /* 75476 */   // Label 1883: @75476
     /* 75476 */   GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(75503), // Rule ID 154 //
     /* 75481 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 75484 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75488 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 75492 */     // (strict_fadd:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FADD_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 75492 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_S),
     /* 75497 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 75501 */     GIR_RootConstrainSelectedInstOperands,
     /* 75502 */     // GIR_Coverage, 154,
     /* 75502 */     GIR_Done,
     /* 75503 */   // Label 1884: @75503
     /* 75503 */   GIM_Reject,
     /* 75504 */ // Label 1879: @75504
     /* 75504 */ GIM_Reject,
     /* 75505 */ // Label 1877: @75505
     /* 75505 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(76067),
     /* 75510 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 75513 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 75516 */   GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(75577), // Rule ID 187 //
     /* 75521 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75524 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75528 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75532 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75536 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75540 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75544 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75549 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75554 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75558 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75560 */     // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 75560 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 75563 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75565 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75567 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75571 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75575 */     GIR_RootConstrainSelectedInstOperands,
     /* 75576 */     // GIR_Coverage, 187,
     /* 75576 */     GIR_EraseRootFromParent_Done,
     /* 75577 */   // Label 1886: @75577
     /* 75577 */   GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(75638), // Rule ID 195 //
     /* 75582 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75585 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75589 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75593 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75597 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75601 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75605 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75610 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75615 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75619 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75621 */     // (strict_fadd:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 75621 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 75624 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75626 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75628 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75632 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75636 */     GIR_RootConstrainSelectedInstOperands,
     /* 75637 */     // GIR_Coverage, 195,
     /* 75637 */     GIR_EraseRootFromParent_Done,
     /* 75638 */   // Label 1887: @75638
     /* 75638 */   GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(75699), // Rule ID 186 //
     /* 75643 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75646 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75650 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75654 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75658 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75662 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75666 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75671 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75676 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75680 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75682 */     // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 75682 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 75685 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75687 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75689 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75693 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75697 */     GIR_RootConstrainSelectedInstOperands,
     /* 75698 */     // GIR_Coverage, 186,
     /* 75698 */     GIR_EraseRootFromParent_Done,
     /* 75699 */   // Label 1888: @75699
     /* 75699 */   GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(75760), // Rule ID 194 //
     /* 75704 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75707 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75711 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 75715 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75719 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75723 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75727 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75732 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75737 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75741 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75743 */     // (strict_fadd:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 75743 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 75746 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75748 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 75750 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75754 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75758 */     GIR_RootConstrainSelectedInstOperands,
     /* 75759 */     // GIR_Coverage, 194,
     /* 75759 */     GIR_EraseRootFromParent_Done,
     /* 75760 */   // Label 1889: @75760
     /* 75760 */   GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(75821), // Rule ID 2492 //
     /* 75765 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75768 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75772 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75776 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75780 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75784 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75788 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75792 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75797 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75802 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75804 */     // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 75804 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 75807 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75809 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75811 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75815 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75819 */     GIR_RootConstrainSelectedInstOperands,
     /* 75820 */     // GIR_Coverage, 2492,
     /* 75820 */     GIR_EraseRootFromParent_Done,
     /* 75821 */   // Label 1890: @75821
     /* 75821 */   GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(75882), // Rule ID 2496 //
     /* 75826 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75829 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75833 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75837 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75841 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 75845 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75849 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75853 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75858 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75863 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75865 */     // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 75865 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 75868 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75870 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75872 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75876 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75880 */     GIR_RootConstrainSelectedInstOperands,
     /* 75881 */     // GIR_Coverage, 2496,
     /* 75881 */     GIR_EraseRootFromParent_Done,
     /* 75882 */   // Label 1891: @75882
     /* 75882 */   GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(75943), // Rule ID 2491 //
     /* 75887 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75890 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75894 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75898 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75902 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75906 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75910 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75914 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75919 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 75924 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75926 */     // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 75926 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D32),
     /* 75929 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75931 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75933 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75937 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 75941 */     GIR_RootConstrainSelectedInstOperands,
     /* 75942 */     // GIR_Coverage, 2491,
     /* 75942 */     GIR_EraseRootFromParent_Done,
     /* 75943 */   // Label 1892: @75943
     /* 75943 */   GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(76004), // Rule ID 2495 //
     /* 75948 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 75951 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75955 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75959 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
     /* 75963 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 75967 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 75971 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 75975 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75980 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 75985 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 75987 */     // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft))  =>  (MADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 75987 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MADD_D64),
     /* 75990 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 75992 */     GIR_RootToRootCopy, /*OpIdx*/1, // fr
     /* 75994 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 75998 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76002 */     GIR_RootConstrainSelectedInstOperands,
     /* 76003 */     // GIR_Coverage, 2495,
     /* 76003 */     GIR_EraseRootFromParent_Done,
     /* 76004 */   // Label 1893: @76004
     /* 76004 */   GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(76035), // Rule ID 156 //
     /* 76009 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 76012 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76016 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76020 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76024 */     // (strict_fadd:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76024 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D32),
     /* 76029 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76033 */     GIR_RootConstrainSelectedInstOperands,
     /* 76034 */     // GIR_Coverage, 156,
     /* 76034 */     GIR_Done,
     /* 76035 */   // Label 1894: @76035
     /* 76035 */   GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(76066), // Rule ID 158 //
     /* 76040 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 76043 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76047 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76051 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76055 */     // (strict_fadd:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FADD_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76055 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FADD_D64),
     /* 76060 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76064 */     GIR_RootConstrainSelectedInstOperands,
     /* 76065 */     // GIR_Coverage, 158,
     /* 76065 */     GIR_Done,
     /* 76066 */   // Label 1895: @76066
     /* 76066 */   GIM_Reject,
     /* 76067 */ // Label 1885: @76067
     /* 76067 */ GIM_Reject,
     /* 76068 */ // Label 1878: @76068
     /* 76068 */ GIM_Reject,
     /* 76069 */ // Label 79: @76069
     /* 76069 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1898*/ GIMT_Encode4(76565),
     /* 76080 */ /*GILLT_s32*//*Label 1896*/ GIMT_Encode4(76088),
     /* 76084 */ /*GILLT_s64*//*Label 1897*/ GIMT_Encode4(76246),
     /* 76088 */ // Label 1896: @76088
     /* 76088 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(76245),
     /* 76093 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 76096 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 76099 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76103 */   GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(76160), // Rule ID 183 //
     /* 76108 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76111 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76115 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 76119 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 76123 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 76127 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76132 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76137 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76141 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76143 */     // (strict_fsub:{ *:[f32] } (fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 76143 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
     /* 76146 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76148 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76150 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76154 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76158 */     GIR_RootConstrainSelectedInstOperands,
     /* 76159 */     // GIR_Coverage, 183,
     /* 76159 */     GIR_EraseRootFromParent_Done,
     /* 76160 */   // Label 1900: @76160
     /* 76160 */   GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(76217), // Rule ID 182 //
     /* 76165 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76168 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76172 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 76176 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
     /* 76180 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
     /* 76184 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76189 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76194 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76198 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76200 */     // (strict_fsub:{ *:[f32] } (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft), FGR32Opnd:{ *:[f32] }:$fr)  =>  (MSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fr, FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 76200 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_S),
     /* 76203 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76205 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76207 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76211 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76215 */     GIR_RootConstrainSelectedInstOperands,
     /* 76216 */     // GIR_Coverage, 182,
     /* 76216 */     GIR_EraseRootFromParent_Done,
     /* 76217 */   // Label 1901: @76217
     /* 76217 */   GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(76244), // Rule ID 172 //
     /* 76222 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 76225 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76229 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76233 */     // (strict_fsub:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FSUB_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 76233 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_S),
     /* 76238 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76242 */     GIR_RootConstrainSelectedInstOperands,
     /* 76243 */     // GIR_Coverage, 172,
     /* 76243 */     GIR_Done,
     /* 76244 */   // Label 1902: @76244
     /* 76244 */   GIM_Reject,
     /* 76245 */ // Label 1899: @76245
     /* 76245 */ GIM_Reject,
     /* 76246 */ // Label 1897: @76246
     /* 76246 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(76564),
     /* 76251 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 76254 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 76257 */   GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(76318), // Rule ID 191 //
     /* 76262 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76265 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76269 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76273 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 76277 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 76281 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 76285 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76290 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76295 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76299 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76301 */     // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76301 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
     /* 76304 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76306 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76308 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76312 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76316 */     GIR_RootConstrainSelectedInstOperands,
     /* 76317 */     // GIR_Coverage, 191,
     /* 76317 */     GIR_EraseRootFromParent_Done,
     /* 76318 */   // Label 1904: @76318
     /* 76318 */   GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(76379), // Rule ID 199 //
     /* 76323 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76326 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76330 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76334 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
     /* 76338 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 76342 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 76346 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76351 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76356 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76360 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76362 */     // (strict_fsub:{ *:[f64] } (fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76362 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
     /* 76365 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76367 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76369 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76373 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76377 */     GIR_RootConstrainSelectedInstOperands,
     /* 76378 */     // GIR_Coverage, 199,
     /* 76378 */     GIR_EraseRootFromParent_Done,
     /* 76379 */   // Label 1905: @76379
     /* 76379 */   GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(76440), // Rule ID 190 //
     /* 76384 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76387 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76391 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76395 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 76399 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 76403 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 76407 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76412 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76417 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76421 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76423 */     // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft), AFGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fr, AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76423 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D32),
     /* 76426 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76428 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76430 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76434 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76438 */     GIR_RootConstrainSelectedInstOperands,
     /* 76439 */     // GIR_Coverage, 190,
     /* 76439 */     GIR_EraseRootFromParent_Done,
     /* 76440 */   // Label 1906: @76440
     /* 76440 */   GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(76501), // Rule ID 198 //
     /* 76445 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6),
     /* 76448 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76452 */     GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
     /* 76456 */     GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
     /* 76460 */     GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
     /* 76464 */     GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
     /* 76468 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76473 */     GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76478 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76482 */     GIM_CheckIsSafeToFold, /*NumInsns*/1,
     /* 76484 */     // (strict_fsub:{ *:[f64] } (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft), FGR64Opnd:{ *:[f64] }:$fr)  =>  (MSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fr, FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76484 */     GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(Mips::MSUB_D64),
     /* 76487 */     GIR_RootToRootCopy, /*OpIdx*/0, // DstI[fd]
     /* 76489 */     GIR_RootToRootCopy, /*OpIdx*/2, // fr
     /* 76491 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // fs
     /* 76495 */     GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // ft
     /* 76499 */     GIR_RootConstrainSelectedInstOperands,
     /* 76500 */     // GIR_Coverage, 198,
     /* 76500 */     GIR_EraseRootFromParent_Done,
     /* 76501 */   // Label 1907: @76501
     /* 76501 */   GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(76532), // Rule ID 174 //
     /* 76506 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 76509 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76513 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76517 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76521 */     // (strict_fsub:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76521 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D32),
     /* 76526 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76530 */     GIR_RootConstrainSelectedInstOperands,
     /* 76531 */     // GIR_Coverage, 174,
     /* 76531 */     GIR_Done,
     /* 76532 */   // Label 1908: @76532
     /* 76532 */   GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(76563), // Rule ID 176 //
     /* 76537 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 76540 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76544 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76548 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76552 */     // (strict_fsub:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FSUB_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76552 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSUB_D64),
     /* 76557 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76561 */     GIR_RootConstrainSelectedInstOperands,
     /* 76562 */     // GIR_Coverage, 176,
     /* 76562 */     GIR_Done,
     /* 76563 */   // Label 1909: @76563
     /* 76563 */   GIM_Reject,
     /* 76564 */ // Label 1903: @76564
     /* 76564 */ GIM_Reject,
     /* 76565 */ // Label 1898: @76565
     /* 76565 */ GIM_Reject,
     /* 76566 */ // Label 80: @76566
     /* 76566 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1912*/ GIMT_Encode4(76698),
     /* 76577 */ /*GILLT_s32*//*Label 1910*/ GIMT_Encode4(76585),
     /* 76581 */ /*GILLT_s64*//*Label 1911*/ GIMT_Encode4(76623),
     /* 76585 */ // Label 1910: @76585
     /* 76585 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(76622), // Rule ID 166 //
     /* 76590 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 76593 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 76596 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 76599 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76603 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76607 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76611 */   // (strict_fmul:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FMUL_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 76611 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_S),
     /* 76616 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76620 */   GIR_RootConstrainSelectedInstOperands,
     /* 76621 */   // GIR_Coverage, 166,
     /* 76621 */   GIR_Done,
     /* 76622 */ // Label 1913: @76622
     /* 76622 */ GIM_Reject,
     /* 76623 */ // Label 1911: @76623
     /* 76623 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(76697),
     /* 76628 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 76631 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 76634 */   GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(76665), // Rule ID 168 //
     /* 76639 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 76642 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76646 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76650 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76654 */     // (strict_fmul:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76654 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D32),
     /* 76659 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76663 */     GIR_RootConstrainSelectedInstOperands,
     /* 76664 */     // GIR_Coverage, 168,
     /* 76664 */     GIR_Done,
     /* 76665 */   // Label 1915: @76665
     /* 76665 */   GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(76696), // Rule ID 170 //
     /* 76670 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 76673 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76677 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76681 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76685 */     // (strict_fmul:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FMUL_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76685 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FMUL_D64),
     /* 76690 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76694 */     GIR_RootConstrainSelectedInstOperands,
     /* 76695 */     // GIR_Coverage, 170,
     /* 76695 */     GIR_Done,
     /* 76696 */   // Label 1916: @76696
     /* 76696 */   GIM_Reject,
     /* 76697 */ // Label 1914: @76697
     /* 76697 */ GIM_Reject,
     /* 76698 */ // Label 1912: @76698
     /* 76698 */ GIM_Reject,
     /* 76699 */ // Label 81: @76699
     /* 76699 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1919*/ GIMT_Encode4(76831),
     /* 76710 */ /*GILLT_s32*//*Label 1917*/ GIMT_Encode4(76718),
     /* 76714 */ /*GILLT_s64*//*Label 1918*/ GIMT_Encode4(76756),
     /* 76718 */ // Label 1917: @76718
     /* 76718 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(76755), // Rule ID 160 //
     /* 76723 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 76726 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 76729 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
     /* 76732 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76736 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76740 */   GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76744 */   // (strict_fdiv:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)  =>  (FDIV_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs, FGR32Opnd:{ *:[f32] }:$ft)
     /* 76744 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_S),
     /* 76749 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76753 */   GIR_RootConstrainSelectedInstOperands,
     /* 76754 */   // GIR_Coverage, 160,
     /* 76754 */   GIR_Done,
     /* 76755 */ // Label 1920: @76755
     /* 76755 */ GIM_Reject,
     /* 76756 */ // Label 1918: @76756
     /* 76756 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(76830),
     /* 76761 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 76764 */   GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
     /* 76767 */   GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(76798), // Rule ID 162 //
     /* 76772 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 76775 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76779 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76783 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76787 */     // (strict_fdiv:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs, AFGR64Opnd:{ *:[f64] }:$ft)
     /* 76787 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D32),
     /* 76792 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76796 */     GIR_RootConstrainSelectedInstOperands,
     /* 76797 */     // GIR_Coverage, 162,
     /* 76797 */     GIR_Done,
     /* 76798 */   // Label 1922: @76798
     /* 76798 */   GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(76829), // Rule ID 164 //
     /* 76803 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 76806 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76810 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76814 */     GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76818 */     // (strict_fdiv:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)  =>  (FDIV_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs, FGR64Opnd:{ *:[f64] }:$ft)
     /* 76818 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FDIV_D64),
     /* 76823 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76827 */     GIR_RootConstrainSelectedInstOperands,
     /* 76828 */     // GIR_Coverage, 164,
     /* 76828 */     GIR_Done,
     /* 76829 */   // Label 1923: @76829
     /* 76829 */   GIM_Reject,
     /* 76830 */ // Label 1921: @76830
     /* 76830 */ GIM_Reject,
     /* 76831 */ // Label 1919: @76831
     /* 76831 */ GIM_Reject,
     /* 76832 */ // Label 82: @76832
     /* 76832 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1926*/ GIMT_Encode4(76946),
     /* 76843 */ /*GILLT_s32*//*Label 1924*/ GIMT_Encode4(76851),
     /* 76847 */ /*GILLT_s64*//*Label 1925*/ GIMT_Encode4(76882),
     /* 76851 */ // Label 1924: @76851
     /* 76851 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(76881), // Rule ID 132 //
     /* 76856 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips),
     /* 76859 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
     /* 76862 */   GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76866 */   GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR32RegClassID),
     /* 76870 */   // (strict_fsqrt:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)  =>  (FSQRT_S:{ *:[f32] } FGR32Opnd:{ *:[f32] }:$fs)
     /* 76870 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_S),
     /* 76875 */   GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76879 */   GIR_RootConstrainSelectedInstOperands,
     /* 76880 */   // GIR_Coverage, 132,
     /* 76880 */   GIR_Done,
     /* 76881 */ // Label 1927: @76881
     /* 76881 */ GIM_Reject,
     /* 76882 */ // Label 1925: @76882
     /* 76882 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(76945),
     /* 76887 */   GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
     /* 76890 */   GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(76917), // Rule ID 134 //
     /* 76895 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips),
     /* 76898 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76902 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::AFGR64RegClassID),
     /* 76906 */     // (strict_fsqrt:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D32:{ *:[f64] } AFGR64Opnd:{ *:[f64] }:$fs)
     /* 76906 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D32),
     /* 76911 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76915 */     GIR_RootConstrainSelectedInstOperands,
     /* 76916 */     // GIR_Coverage, 134,
     /* 76916 */     GIR_Done,
     /* 76917 */   // Label 1929: @76917
     /* 76917 */   GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(76944), // Rule ID 136 //
     /* 76922 */     GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips),
     /* 76925 */     GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76929 */     GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Mips::FGR64RegClassID),
     /* 76933 */     // (strict_fsqrt:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)  =>  (FSQRT_D64:{ *:[f64] } FGR64Opnd:{ *:[f64] }:$fs)
     /* 76933 */     GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::FSQRT_D64),
     /* 76938 */     GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(Mips::FCR31),
     /* 76942 */     GIR_RootConstrainSelectedInstOperands,
     /* 76943 */     // GIR_Coverage, 136,
     /* 76943 */     GIR_Done,
     /* 76944 */   // Label 1930: @76944
     /* 76944 */   GIM_Reject,
     /* 76945 */ // Label 1928: @76945
     /* 76945 */ GIM_Reject,
     /* 76946 */ // Label 1926: @76946
     /* 76946 */ GIM_Reject,
     /* 76947 */ // Label 83: @76947
     /* 76947 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(76962), // Rule ID 90 //
     /* 76952 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasStdEnc_NotInMicroMips),
     /* 76955 */   // (trap)  =>  (TRAP)
     /* 76955 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP),
     /* 76960 */   GIR_RootConstrainSelectedInstOperands,
     /* 76961 */   // GIR_Coverage, 90,
     /* 76961 */   GIR_Done,
     /* 76962 */ // Label 1931: @76962
     /* 76962 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(76977), // Rule ID 1190 //
     /* 76967 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMicroMips),
     /* 76970 */   // (trap)  =>  (TRAP_MM)
     /* 76970 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::TRAP_MM),
     /* 76975 */   GIR_RootConstrainSelectedInstOperands,
     /* 76976 */   // GIR_Coverage, 1190,
     /* 76976 */   GIR_Done,
     /* 76977 */ // Label 1932: @76977
     /* 76977 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(76992), // Rule ID 2037 //
     /* 76982 */   GIM_CheckFeatures, GIMT_Encode2(GIFBS_InMips16Mode),
     /* 76985 */   // (trap)  =>  (Break16)
     /* 76985 */   GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(Mips::Break16),
     /* 76990 */   GIR_RootConstrainSelectedInstOperands,
     /* 76991 */   // GIR_Coverage, 2037,
     /* 76991 */   GIR_Done,
     /* 76992 */ // Label 1933: @76992
     /* 76992 */ GIM_Reject,
     /* 76993 */ // Label 84: @76993
     /* 76993 */ GIM_Reject,
     /* 76994 */ }; // Size: 76994 bytes
  return MatchTable0;
}
#undef GIMT_Encode2
#undef GIMT_Encode4
#undef GIMT_Encode8

#endif // ifdef GET_GLOBALISEL_IMPL

#ifdef GET_GLOBALISEL_PREDICATES_DECL
PredicateBitset AvailableModuleFeatures;
mutable PredicateBitset AvailableFunctionFeatures;
PredicateBitset getAvailableFeatures() const {
  return AvailableModuleFeatures | AvailableFunctionFeatures;
}
PredicateBitset
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const;
PredicateBitset
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget,
                                 const MachineFunction *MF) const;
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
#ifdef GET_GLOBALISEL_PREDICATES_INIT
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
AvailableFunctionFeatures()
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
