/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

extern const MCRegisterClass MipsMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::v4i8, MVT::v2i16, MVT::i32, MVT::Other,
  /* 4 */ MVT::i64, MVT::Other,
  /* 6 */ MVT::f16, MVT::Other,
  /* 8 */ MVT::f32, MVT::Other,
  /* 10 */ MVT::i32, MVT::f32, MVT::f64, MVT::Other,
  /* 14 */ MVT::v16i8, MVT::Other,
  /* 16 */ MVT::v4i8, MVT::v2i16, MVT::Other,
  /* 19 */ MVT::v8i16, MVT::v8f16, MVT::Other,
  /* 22 */ MVT::v4i32, MVT::v4f32, MVT::Other,
  /* 25 */ MVT::v2i64, MVT::v2f64, MVT::Other,
  /* 28 */ MVT::Untyped, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };

static const TargetRegisterInfo::SubRegCoveredBits SubRegIdxRangeTable[] = {
  { 65535, 65535 },
  { 0, 32 },	// sub_32
  { 0, 64 },	// sub_64
  { 16, 4 },	// sub_dsp16_19
  { 20, 1 },	// sub_dsp20
  { 21, 1 },	// sub_dsp21
  { 22, 1 },	// sub_dsp22
  { 23, 1 },	// sub_dsp23
  { 32, 32 },	// sub_hi
  { 0, 32 },	// sub_lo
  { 32, 32 },	// sub_hi_then_sub_32
  { 0, 64 },	// sub_32_sub_hi_then_sub_32
  { 65535, 65535 },
  { 0, 32 },	// sub_32
  { 0, 64 },	// sub_64
  { 16, 4 },	// sub_dsp16_19
  { 20, 1 },	// sub_dsp20
  { 21, 1 },	// sub_dsp21
  { 22, 1 },	// sub_dsp22
  { 23, 1 },	// sub_dsp23
  { 32, 32 },	// sub_hi
  { 0, 32 },	// sub_lo
  { 32, 32 },	// sub_hi_then_sub_32
  { 0, 64 },	// sub_32_sub_hi_then_sub_32
};


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_32
  LaneBitmask(0x0000000000000041), // sub_64
  LaneBitmask(0x0000000000000002), // sub_dsp16_19
  LaneBitmask(0x0000000000000004), // sub_dsp20
  LaneBitmask(0x0000000000000008), // sub_dsp21
  LaneBitmask(0x0000000000000010), // sub_dsp22
  LaneBitmask(0x0000000000000020), // sub_dsp23
  LaneBitmask(0x0000000000000040), // sub_hi
  LaneBitmask(0x0000000000000001), // sub_lo
  LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
  LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 16, 16, 128, /*VTLists+*/6 },    // MSA128F16
  { 32, 32, 32, /*VTLists+*/2 },    // CCR
  { 32, 32, 32, /*VTLists+*/2 },    // COP0
  { 32, 32, 32, /*VTLists+*/2 },    // COP2
  { 32, 32, 32, /*VTLists+*/2 },    // COP3
  { 32, 32, 32, /*VTLists+*/0 },    // DSPR
  { 32, 32, 32, /*VTLists+*/8 },    // FGR32
  { 32, 32, 32, /*VTLists+*/2 },    // FGR32CC
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32
  { 32, 32, 32, /*VTLists+*/2 },    // HWRegs
  { 32, 32, 32, /*VTLists+*/2 },    // MSACtrl
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32NONZERO
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16RegsPlusSP
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs
  { 32, 32, 32, /*VTLists+*/2 },    // FCC
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32NONZERO_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // HI32DSP
  { 32, 32, 32, /*VTLists+*/2 },    // LO32DSP
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairFirst
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // CPURAReg
  { 32, 32, 32, /*VTLists+*/2 },    // CPUSPReg
  { 32, 32, 32, /*VTLists+*/16 },    // DSPCC
  { 32, 32, 32, /*VTLists+*/2 },    // GP32
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32ZERO
  { 32, 32, 32, /*VTLists+*/2 },    // HI32
  { 32, 32, 32, /*VTLists+*/2 },    // LO32
  { 32, 32, 32, /*VTLists+*/2 },    // SP32
  { 32, 32, 64, /*VTLists+*/10 },    // FGR64CC
  { 64, 64, 64, /*VTLists+*/12 },    // FGR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32NONZERO
  { 64, 64, 64, /*VTLists+*/12 },    // AFGR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/28 },    // ACC64DSP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // OCTEON_MPL
  { 64, 64, 64, /*VTLists+*/4 },    // OCTEON_P
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/28 },    // ACC64
  { 64, 64, 64, /*VTLists+*/4 },    // GP64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPURAReg
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32ZERO
  { 64, 64, 64, /*VTLists+*/4 },    // HI64
  { 64, 64, 64, /*VTLists+*/4 },    // LO64
  { 64, 64, 64, /*VTLists+*/4 },    // SP64
  { 128, 128, 128, /*VTLists+*/14 },    // MSA128B
  { 128, 128, 128, /*VTLists+*/25 },    // MSA128D
  { 128, 128, 128, /*VTLists+*/19 },    // MSA128H
  { 128, 128, 128, /*VTLists+*/22 },    // MSA128W
  { 128, 128, 128, /*VTLists+*/22 },    // MSA128WEvens
  { 128, 128, 128, /*VTLists+*/28 },    // ACC128
  // Mode = 1 (MIPS64)
  { 16, 16, 128, /*VTLists+*/6 },    // MSA128F16
  { 32, 32, 32, /*VTLists+*/2 },    // CCR
  { 32, 32, 32, /*VTLists+*/2 },    // COP0
  { 32, 32, 32, /*VTLists+*/2 },    // COP2
  { 32, 32, 32, /*VTLists+*/2 },    // COP3
  { 32, 32, 32, /*VTLists+*/0 },    // DSPR
  { 32, 32, 32, /*VTLists+*/8 },    // FGR32
  { 32, 32, 32, /*VTLists+*/2 },    // FGR32CC
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32
  { 32, 32, 32, /*VTLists+*/2 },    // HWRegs
  { 32, 32, 32, /*VTLists+*/2 },    // MSACtrl
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32NONZERO
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16RegsPlusSP
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs
  { 32, 32, 32, /*VTLists+*/2 },    // FCC
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32NONZERO_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // HI32DSP
  { 32, 32, 32, /*VTLists+*/2 },    // LO32DSP
  { 32, 32, 32, /*VTLists+*/2 },    // CPU16Regs_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairFirst
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/2 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/2 },    // CPURAReg
  { 32, 32, 32, /*VTLists+*/2 },    // CPUSPReg
  { 32, 32, 32, /*VTLists+*/16 },    // DSPCC
  { 32, 32, 32, /*VTLists+*/2 },    // GP32
  { 32, 32, 32, /*VTLists+*/2 },    // GPR32ZERO
  { 32, 32, 32, /*VTLists+*/2 },    // HI32
  { 32, 32, 32, /*VTLists+*/2 },    // LO32
  { 32, 32, 32, /*VTLists+*/2 },    // SP32
  { 32, 32, 64, /*VTLists+*/10 },    // FGR64CC
  { 64, 64, 64, /*VTLists+*/12 },    // FGR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32NONZERO
  { 64, 64, 64, /*VTLists+*/12 },    // AFGR64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/28 },    // ACC64DSP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/4 },    // OCTEON_MPL
  { 64, 64, 64, /*VTLists+*/4 },    // OCTEON_P
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/28 },    // ACC64
  { 64, 64, 64, /*VTLists+*/4 },    // GP64
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_CPURAReg
  { 64, 64, 64, /*VTLists+*/4 },    // GPR64_with_sub_32_in_GPR32ZERO
  { 64, 64, 64, /*VTLists+*/4 },    // HI64
  { 64, 64, 64, /*VTLists+*/4 },    // LO64
  { 64, 64, 64, /*VTLists+*/4 },    // SP64
  { 128, 128, 128, /*VTLists+*/14 },    // MSA128B
  { 128, 128, 128, /*VTLists+*/25 },    // MSA128D
  { 128, 128, 128, /*VTLists+*/19 },    // MSA128H
  { 128, 128, 128, /*VTLists+*/22 },    // MSA128W
  { 128, 128, 128, /*VTLists+*/22 },    // MSA128WEvens
  { 128, 128, 128, /*VTLists+*/28 },    // ACC128
};
static const uint32_t MSA128F16SubClassMask[] = {
  0x00000001, 0x00000000, 0x0000003e, 
};

static const uint32_t CCRSubClassMask[] = {
  0x00000002, 0x00000000, 0x00000000, 
};

static const uint32_t COP0SubClassMask[] = {
  0x00000004, 0x00000000, 0x00000000, 
};

static const uint32_t COP2SubClassMask[] = {
  0x00000008, 0x00000000, 0x00000000, 
};

static const uint32_t COP3SubClassMask[] = {
  0x00000010, 0x00000000, 0x00000000, 
};

static const uint32_t DSPRSubClassMask[] = {
  0x7e7fb920, 0x00000013, 0x00000000, 
  0x00000000, 0x3a7dfd80, 0x00000001, // sub_32
};

static const uint32_t FGR32SubClassMask[] = {
  0x000000c0, 0x00000000, 0x00000000, 
  0x00000000, 0x00000200, 0x00000000, // sub_hi
  0x00000001, 0x00000260, 0x0000003e, // sub_lo
};

static const uint32_t FGR32CCSubClassMask[] = {
  0x000000c0, 0x00000000, 0x00000000, 
  0x00000000, 0x00000200, 0x00000000, // sub_hi
  0x00000001, 0x00000260, 0x0000003e, // sub_lo
};

static const uint32_t GPR32SubClassMask[] = {
  0x7e7fb900, 0x00000013, 0x00000000, 
  0x00000000, 0x3a7dfd80, 0x00000001, // sub_32
};

static const uint32_t HWRegsSubClassMask[] = {
  0x00000200, 0x00000000, 0x00000000, 
};

static const uint32_t MSACtrlSubClassMask[] = {
  0x00000400, 0x00000000, 0x00000000, 
};

static const uint32_t GPR32NONZEROSubClassMask[] = {
  0x7e3cb800, 0x00000011, 0x00000000, 
  0x00000000, 0x1a75cd00, 0x00000001, // sub_32
};

static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
  0x5e24b000, 0x00000010, 0x00000000, 
  0x00000000, 0x02744c00, 0x00000001, // sub_32
};

static const uint32_t CPU16RegsSubClassMask[] = {
  0x1e24a000, 0x00000000, 0x00000000, 
  0x00000000, 0x02744800, 0x00000000, // sub_32
};

static const uint32_t FCCSubClassMask[] = {
  0x00004000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRMM16SubClassMask[] = {
  0x1e248000, 0x00000000, 0x00000000, 
  0x00000000, 0x02744800, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePSubClassMask[] = {
  0x08690000, 0x00000002, 0x00000000, 
  0x00000000, 0x204c9000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16ZeroSubClassMask[] = {
  0x1e460000, 0x00000002, 0x00000000, 
  0x00000000, 0x22786000, 0x00000000, // sub_32
};

static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x1e040000, 0x00000000, 0x00000000, 
  0x00000000, 0x02704000, 0x00000000, // sub_32
};

static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
  0x08280000, 0x00000000, 0x00000000, 
  0x00000000, 0x00448000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
  0x12100000, 0x00000000, 0x00000000, 
  0x00000000, 0x02110000, 0x00000000, // sub_32
};

static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
  0x08200000, 0x00000000, 0x00000000, 
  0x00000000, 0x00440000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
  0x08400000, 0x00000002, 0x00000000, 
  0x00000000, 0x20480000, 0x00000000, // sub_32
};

static const uint32_t HI32DSPSubClassMask[] = {
  0x00800000, 0x00000004, 0x00000000, 
  0x00000000, 0x40000000, 0x00000000, // sub_32
  0x00000000, 0x04020000, 0x00000000, // sub_hi
  0x00000000, 0x00000000, 0x00000040, // sub_hi_then_sub_32
};

static const uint32_t LO32DSPSubClassMask[] = {
  0x01000000, 0x00000008, 0x00000000, 
  0x00000000, 0x80000000, 0x00000040, // sub_32
  0x00000000, 0x04020000, 0x00000000, // sub_lo
};

static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x12000000, 0x00000000, 0x00000000, 
  0x00000000, 0x02100000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
  0x14000000, 0x00000000, 0x00000000, 
  0x00000000, 0x02200000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x08000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00400000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x10000000, 0x00000000, 0x00000000, 
  0x00000000, 0x02000000, 0x00000000, // sub_32
};

static const uint32_t CPURARegSubClassMask[] = {
  0x20000000, 0x00000000, 0x00000000, 
  0x00000000, 0x10000000, 0x00000000, // sub_32
};

static const uint32_t CPUSPRegSubClassMask[] = {
  0x40000000, 0x00000010, 0x00000000, 
  0x00000000, 0x00000000, 0x00000001, // sub_32
};

static const uint32_t DSPCCSubClassMask[] = {
  0x80000000, 0x00000000, 0x00000000, 
};

static const uint32_t GP32SubClassMask[] = {
  0x00000000, 0x00000001, 0x00000000, 
  0x00000000, 0x08000000, 0x00000000, // sub_32
};

static const uint32_t GPR32ZEROSubClassMask[] = {
  0x00000000, 0x00000002, 0x00000000, 
  0x00000000, 0x20000000, 0x00000000, // sub_32
};

static const uint32_t HI32SubClassMask[] = {
  0x00000000, 0x00000004, 0x00000000, 
  0x00000000, 0x40000000, 0x00000000, // sub_32
  0x00000000, 0x04000000, 0x00000000, // sub_hi
  0x00000000, 0x00000000, 0x00000040, // sub_hi_then_sub_32
};

static const uint32_t LO32SubClassMask[] = {
  0x00000000, 0x00000008, 0x00000000, 
  0x00000000, 0x80000000, 0x00000040, // sub_32
  0x00000000, 0x04000000, 0x00000000, // sub_lo
};

static const uint32_t SP32SubClassMask[] = {
  0x00000000, 0x00000010, 0x00000000, 
  0x00000000, 0x00000000, 0x00000001, // sub_32
};

static const uint32_t FGR64CCSubClassMask[] = {
  0x00000000, 0x00000060, 0x00000000, 
  0x00000001, 0x00000000, 0x0000003e, // sub_64
};

static const uint32_t FGR64SubClassMask[] = {
  0x00000000, 0x00000040, 0x00000000, 
  0x00000001, 0x00000000, 0x0000003e, // sub_64
};

static const uint32_t GPR64SubClassMask[] = {
  0x00000000, 0x3a7dfd80, 0x00000001, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
  0x00000000, 0x1a75cd00, 0x00000001, 
};

static const uint32_t AFGR64SubClassMask[] = {
  0x00000000, 0x00000200, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
  0x00000000, 0x02744c00, 0x00000001, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
  0x00000000, 0x02744800, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x204c9000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x22786000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x02704000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x00448000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x02110000, 0x00000000, 
};

static const uint32_t ACC64DSPSubClassMask[] = {
  0x00000000, 0x04020000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000040, // sub_32_sub_hi_then_sub_32
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x00440000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x20480000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x02100000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
  0x00000000, 0x02200000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x00400000, 0x00000000, 
};

static const uint32_t OCTEON_MPLSubClassMask[] = {
  0x00000000, 0x00800000, 0x00000000, 
};

static const uint32_t OCTEON_PSubClassMask[] = {
  0x00000000, 0x01000000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x02000000, 0x00000000, 
};

static const uint32_t ACC64SubClassMask[] = {
  0x00000000, 0x04000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000040, // sub_32_sub_hi_then_sub_32
};

static const uint32_t GP64SubClassMask[] = {
  0x00000000, 0x08000000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
  0x00000000, 0x10000000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
  0x00000000, 0x20000000, 0x00000000, 
};

static const uint32_t HI64SubClassMask[] = {
  0x00000000, 0x40000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000040, // sub_hi
};

static const uint32_t LO64SubClassMask[] = {
  0x00000000, 0x80000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000040, // sub_lo
};

static const uint32_t SP64SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000001, 
};

static const uint32_t MSA128BSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000003e, 
};

static const uint32_t MSA128DSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000003e, 
};

static const uint32_t MSA128HSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000003e, 
};

static const uint32_t MSA128WSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000003e, 
};

static const uint32_t MSA128WEvensSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000020, 
};

static const uint32_t ACC128SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000040, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
  /* 2 */ 2, 0,
  /* 4 */ 8, 0,
  /* 6 */ 1, 9, 0,
  /* 9 */ 8, 9, 0,
  /* 12 */ 1, 8, 10, 0,
  /* 16 */ 11, 0,
};

static unsigned const FGR32Superclasses[] = {
  Mips::FGR32CCRegClassID,
};

static unsigned const FGR32CCSuperclasses[] = {
  Mips::FGR32RegClassID,
};

static unsigned const GPR32Superclasses[] = {
  Mips::DSPRRegClassID,
};

static unsigned const GPR32NONZEROSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
};

static unsigned const CPU16RegsPlusSPSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
};

static unsigned const CPU16RegsSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
};

static unsigned const GPRMM16Superclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
};

static unsigned const GPRMM16MovePSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
};

static unsigned const GPRMM16ZeroSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
};

static unsigned const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16ZeroRegClassID,
};

static unsigned const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::GPRMM16MovePRegClassID,
};

static unsigned const GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
};

static unsigned const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16MovePRegClassID,
  Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
};

static unsigned const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPRMM16MovePRegClassID,
  Mips::GPRMM16ZeroRegClassID,
};

static unsigned const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16ZeroRegClassID,
  Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPRMM16MovePPairSecondRegClassID,
};

static unsigned const GPRMM16MovePPairFirstSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16ZeroRegClassID,
  Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
};

static unsigned const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16MovePRegClassID,
  Mips::GPRMM16ZeroRegClassID,
  Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID,
  Mips::CPU16Regs_and_GPRMM16MovePRegClassID,
  Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
};

static unsigned const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPU16RegsRegClassID,
  Mips::GPRMM16RegClassID,
  Mips::GPRMM16ZeroRegClassID,
  Mips::CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPRMM16MovePPairSecondRegClassID,
  Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
  Mips::GPRMM16MovePPairFirstRegClassID,
};

static unsigned const CPURARegSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
};

static unsigned const CPUSPRegSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
};

static unsigned const GP32Superclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
};

static unsigned const GPR32ZEROSuperclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPRMM16MovePRegClassID,
  Mips::GPRMM16ZeroRegClassID,
  Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
};

static unsigned const HI32Superclasses[] = {
  Mips::HI32DSPRegClassID,
};

static unsigned const LO32Superclasses[] = {
  Mips::LO32DSPRegClassID,
};

static unsigned const SP32Superclasses[] = {
  Mips::DSPRRegClassID,
  Mips::GPR32RegClassID,
  Mips::GPR32NONZERORegClassID,
  Mips::CPU16RegsPlusSPRegClassID,
  Mips::CPUSPRegRegClassID,
};

static unsigned const FGR64Superclasses[] = {
  Mips::FGR64CCRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
  Mips::GPR64RegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
  Mips::GPR64RegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
  Mips::GPR64RegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID,
  Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID,
};

static unsigned const ACC64Superclasses[] = {
  Mips::ACC64DSPRegClassID,
};

static unsigned const GP64Superclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
};

static unsigned const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
};

static unsigned const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID,
  Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID,
};

static unsigned const SP64Superclasses[] = {
  Mips::GPR64RegClassID,
  Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID,
  Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID,
};

static unsigned const MSA128BSuperclasses[] = {
  Mips::MSA128F16RegClassID,
  Mips::MSA128DRegClassID,
  Mips::MSA128HRegClassID,
  Mips::MSA128WRegClassID,
};

static unsigned const MSA128DSuperclasses[] = {
  Mips::MSA128F16RegClassID,
  Mips::MSA128BRegClassID,
  Mips::MSA128HRegClassID,
  Mips::MSA128WRegClassID,
};

static unsigned const MSA128HSuperclasses[] = {
  Mips::MSA128F16RegClassID,
  Mips::MSA128BRegClassID,
  Mips::MSA128DRegClassID,
  Mips::MSA128WRegClassID,
};

static unsigned const MSA128WSuperclasses[] = {
  Mips::MSA128F16RegClassID,
  Mips::MSA128BRegClassID,
  Mips::MSA128DRegClassID,
  Mips::MSA128HRegClassID,
};

static unsigned const MSA128WEvensSuperclasses[] = {
  Mips::MSA128F16RegClassID,
  Mips::MSA128BRegClassID,
  Mips::MSA128DRegClassID,
  Mips::MSA128HRegClassID,
  Mips::MSA128WRegClassID,
};


static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF, bool Rev) {
    const auto & S = MF.getSubtarget<MipsSubtarget>();
    return S.isABI_O32() && !S.useOddSPReg();
  }

static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
  static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = FGR32AltOrderSelect(MF, Rev);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF, bool Rev) {
    const auto & S = MF.getSubtarget<MipsSubtarget>();
    return S.isABI_O32() && !S.useOddSPReg();
  }

static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {
  static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = FGR64AltOrderSelect(MF, Rev);
  assert(Select < 2);
  return Order[Select];
}

namespace Mips {   // Register class instances
  extern const TargetRegisterClass MSA128F16RegClass = {
    &MipsMCRegisterClasses[MSA128F16RegClassID],
    MSA128F16SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass CCRRegClass = {
    &MipsMCRegisterClasses[CCRRegClassID],
    CCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass COP0RegClass = {
    &MipsMCRegisterClasses[COP0RegClassID],
    COP0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass COP2RegClass = {
    &MipsMCRegisterClasses[COP2RegClassID],
    COP2SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass COP3RegClass = {
    &MipsMCRegisterClasses[COP3RegClassID],
    COP3SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass DSPRRegClass = {
    &MipsMCRegisterClasses[DSPRRegClassID],
    DSPRSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass FGR32RegClass = {
    &MipsMCRegisterClasses[FGR32RegClassID],
    FGR32SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FGR32Superclasses,  1,
    FGR32GetRawAllocationOrder
  };

  extern const TargetRegisterClass FGR32CCRegClass = {
    &MipsMCRegisterClasses[FGR32CCRegClassID],
    FGR32CCSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FGR32CCSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass GPR32RegClass = {
    &MipsMCRegisterClasses[GPR32RegClassID],
    GPR32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32Superclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass HWRegsRegClass = {
    &MipsMCRegisterClasses[HWRegsRegClassID],
    HWRegsSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass MSACtrlRegClass = {
    &MipsMCRegisterClasses[MSACtrlRegClassID],
    MSACtrlSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPR32NONZERORegClass = {
    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
    GPR32NONZEROSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32NONZEROSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
    CPU16RegsPlusSPSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16RegsPlusSPSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass CPU16RegsRegClass = {
    &MipsMCRegisterClasses[CPU16RegsRegClassID],
    CPU16RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16RegsSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass FCCRegClass = {
    &MipsMCRegisterClasses[FCCRegClassID],
    FCCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16RegClass = {
    &MipsMCRegisterClasses[GPRMM16RegClassID],
    GPRMM16SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16Superclasses,  5,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
    GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
    GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16ZeroSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
    CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16ZeroSuperclasses,  7,
    nullptr
  };

  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32NONZERO_and_GPRMM16MovePSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
    GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairSecondSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
    CPU16Regs_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16MovePSuperclasses,  8,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass HI32DSPRegClass = {
    &MipsMCRegisterClasses[HI32DSPRegClassID],
    HI32DSPSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass LO32DSPRegClass = {
    &MipsMCRegisterClasses[LO32DSPRegClassID],
    LO32DSPSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
    CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,  9,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
    GPRMM16MovePPairFirstSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairFirstSuperclasses,  8,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,  12,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,  11,
    nullptr
  };

  extern const TargetRegisterClass CPURARegRegClass = {
    &MipsMCRegisterClasses[CPURARegRegClassID],
    CPURARegSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPURARegSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass CPUSPRegRegClass = {
    &MipsMCRegisterClasses[CPUSPRegRegClassID],
    CPUSPRegSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPUSPRegSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass DSPCCRegClass = {
    &MipsMCRegisterClasses[DSPCCRegClassID],
    DSPCCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GP32RegClass = {
    &MipsMCRegisterClasses[GP32RegClassID],
    GP32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GP32Superclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass GPR32ZERORegClass = {
    &MipsMCRegisterClasses[GPR32ZERORegClassID],
    GPR32ZEROSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32ZEROSuperclasses,  5,
    nullptr
  };

  extern const TargetRegisterClass HI32RegClass = {
    &MipsMCRegisterClasses[HI32RegClassID],
    HI32SubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    HI32Superclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass LO32RegClass = {
    &MipsMCRegisterClasses[LO32RegClassID],
    LO32SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LO32Superclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass SP32RegClass = {
    &MipsMCRegisterClasses[SP32RegClassID],
    SP32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SP32Superclasses,  5,
    nullptr
  };

  extern const TargetRegisterClass FGR64CCRegClass = {
    &MipsMCRegisterClasses[FGR64CCRegClassID],
    FGR64CCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass FGR64RegClass = {
    &MipsMCRegisterClasses[FGR64RegClassID],
    FGR64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    FGR64Superclasses,  1,
    FGR64GetRawAllocationOrder
  };

  extern const TargetRegisterClass GPR64RegClass = {
    &MipsMCRegisterClasses[GPR64RegClassID],
    GPR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass AFGR64RegClass = {
    &MipsMCRegisterClasses[AFGR64RegClassID],
    AFGR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
    GPR64_with_sub_32_in_CPU16RegsSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16RegsSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,  5,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass ACC64DSPRegClass = {
    &MipsMCRegisterClasses[ACC64DSPRegClassID],
    ACC64DSPSubClassMask,
    SuperRegIdxSeqs + 16,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,  6,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,  7,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,  6,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,  10,
    nullptr
  };

  extern const TargetRegisterClass OCTEON_MPLRegClass = {
    &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
    OCTEON_MPLSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass OCTEON_PRegClass = {
    &MipsMCRegisterClasses[OCTEON_PRegClassID],
    OCTEON_PSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,  9,
    nullptr
  };

  extern const TargetRegisterClass ACC64RegClass = {
    &MipsMCRegisterClasses[ACC64RegClassID],
    ACC64SubClassMask,
    SuperRegIdxSeqs + 16,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    ACC64Superclasses,  1,
    nullptr
  };

  extern const TargetRegisterClass GP64RegClass = {
    &MipsMCRegisterClasses[GP64RegClassID],
    GP64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GP64Superclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
    GPR64_with_sub_32_in_CPURARegSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPURARegSuperclasses,  2,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
    GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32ZEROSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass HI64RegClass = {
    &MipsMCRegisterClasses[HI64RegClassID],
    HI64SubClassMask,
    SuperRegIdxSeqs + 4,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass LO64RegClass = {
    &MipsMCRegisterClasses[LO64RegClassID],
    LO64SubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

  extern const TargetRegisterClass SP64RegClass = {
    &MipsMCRegisterClasses[SP64RegClassID],
    SP64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SP64Superclasses,  3,
    nullptr
  };

  extern const TargetRegisterClass MSA128BRegClass = {
    &MipsMCRegisterClasses[MSA128BRegClassID],
    MSA128BSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128BSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass MSA128DRegClass = {
    &MipsMCRegisterClasses[MSA128DRegClassID],
    MSA128DSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128DSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass MSA128HRegClass = {
    &MipsMCRegisterClasses[MSA128HRegClassID],
    MSA128HSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128HSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass MSA128WRegClass = {
    &MipsMCRegisterClasses[MSA128WRegClassID],
    MSA128WSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128WSuperclasses,  4,
    nullptr
  };

  extern const TargetRegisterClass MSA128WEvensRegClass = {
    &MipsMCRegisterClasses[MSA128WEvensRegClassID],
    MSA128WEvensSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128WEvensSuperclasses,  5,
    nullptr
  };

  extern const TargetRegisterClass ACC128RegClass = {
    &MipsMCRegisterClasses[ACC128RegClassID],
    ACC128SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    nullptr, 0,
    nullptr
  };

} // end namespace Mips

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &Mips::MSA128F16RegClass,
    &Mips::CCRRegClass,
    &Mips::COP0RegClass,
    &Mips::COP2RegClass,
    &Mips::COP3RegClass,
    &Mips::DSPRRegClass,
    &Mips::FGR32RegClass,
    &Mips::FGR32CCRegClass,
    &Mips::GPR32RegClass,
    &Mips::HWRegsRegClass,
    &Mips::MSACtrlRegClass,
    &Mips::GPR32NONZERORegClass,
    &Mips::CPU16RegsPlusSPRegClass,
    &Mips::CPU16RegsRegClass,
    &Mips::FCCRegClass,
    &Mips::GPRMM16RegClass,
    &Mips::GPRMM16MovePRegClass,
    &Mips::GPRMM16ZeroRegClass,
    &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
    &Mips::GPRMM16MovePPairSecondRegClass,
    &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
    &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
    &Mips::HI32DSPRegClass,
    &Mips::LO32DSPRegClass,
    &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
    &Mips::GPRMM16MovePPairFirstRegClass,
    &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
    &Mips::CPURARegRegClass,
    &Mips::CPUSPRegRegClass,
    &Mips::DSPCCRegClass,
    &Mips::GP32RegClass,
    &Mips::GPR32ZERORegClass,
    &Mips::HI32RegClass,
    &Mips::LO32RegClass,
    &Mips::SP32RegClass,
    &Mips::FGR64CCRegClass,
    &Mips::FGR64RegClass,
    &Mips::GPR64RegClass,
    &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
    &Mips::AFGR64RegClass,
    &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
    &Mips::ACC64DSPRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::OCTEON_MPLRegClass,
    &Mips::OCTEON_PRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
    &Mips::ACC64RegClass,
    &Mips::GP64RegClass,
    &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
    &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
    &Mips::HI64RegClass,
    &Mips::LO64RegClass,
    &Mips::SP64RegClass,
    &Mips::MSA128BRegClass,
    &Mips::MSA128DRegClass,
    &Mips::MSA128HRegClass,
    &Mips::MSA128WRegClass,
    &Mips::MSA128WEvensRegClass,
    &Mips::ACC128RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[11] = {
    0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
  };
  static const uint8_t Rows[2][11] = {
    { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
    { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
  };

  --IdxA; assert(IdxA < 11); (void) IdxA;
  --IdxB; assert(IdxB < 11);
  return Rows[RowMap[IdxA]][IdxB];
}

unsigned MipsGenRegisterInfo::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Table[11][11] = {
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
    { 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, Mips::sub_32, 0, },
    { Mips::sub_32, 0, 0, 0, 0, 0, 0, 0, 0, Mips::sub_hi, 0, },
  };

  --IdxA; assert(IdxA < 11);
  --IdxB; assert(IdxB < 11);
  return Table[IdxA][IdxB];
  }

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_32
    0, // to sub_64
    2, // to sub_dsp16_19
    4, // to sub_dsp20
    6, // to sub_dsp21
    8, // to sub_dsp22
    10, // to sub_dsp23
    12, // to sub_hi
    0, // to sub_lo
    12, // to sub_hi_then_sub_32
    0 // to sub_32_sub_hi_then_sub_32
  };

LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[71][11] = {
    {	// MSA128F16
      0,	// sub_32
      1,	// sub_64 -> MSA128F16
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      1,	// sub_hi -> MSA128F16
      1,	// sub_lo -> MSA128F16
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CCR
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// COP0
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// COP2
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// COP3
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// DSPR
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// FGR32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// FGR32CC
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// HWRegs
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSACtrl
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR32NONZERO
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPU16RegsPlusSP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// FCC
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16Zero
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16Zero
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR32NONZERO_and_GPRMM16MoveP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairSecond
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16MoveP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP_and_GPRMM16Zero
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// HI32DSP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// LO32DSP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16MovePPairSecond
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairFirst
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPURAReg
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// CPUSPReg
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// DSPCC
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GP32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR32ZERO
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// HI32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// LO32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// SP32
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// FGR64CC
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      38,	// sub_hi -> FGR64CC
      38,	// sub_lo -> FGR64CC
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// FGR64
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      39,	// sub_hi -> FGR64
      39,	// sub_lo -> FGR64
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64
      40,	// sub_32 -> GPR64
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32NONZERO
      41,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// AFGR64
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      42,	// sub_hi -> AFGR64
      42,	// sub_lo -> AFGR64
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
      43,	// sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs
      44,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP
      45,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16Zero
      46,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      47,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      48,	// sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      49,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// ACC64DSP
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      50,	// sub_hi -> ACC64DSP
      50,	// sub_lo -> ACC64DSP
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      51,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      52,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      53,	// sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      54,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      55,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// OCTEON_MPL
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// OCTEON_P
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      58,	// sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// ACC64
      0,	// sub_32
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      59,	// sub_hi -> ACC64
      59,	// sub_lo -> ACC64
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GP64
      60,	// sub_32 -> GP64
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPURAReg
      61,	// sub_32 -> GPR64_with_sub_32_in_CPURAReg
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32ZERO
      62,	// sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// HI64
      63,	// sub_32 -> HI64
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// LO64
      64,	// sub_32 -> LO64
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// SP64
      65,	// sub_32 -> SP64
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      0,	// sub_hi
      0,	// sub_lo
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSA128B
      0,	// sub_32
      66,	// sub_64 -> MSA128B
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      66,	// sub_hi -> MSA128B
      66,	// sub_lo -> MSA128B
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSA128D
      0,	// sub_32
      67,	// sub_64 -> MSA128D
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      67,	// sub_hi -> MSA128D
      67,	// sub_lo -> MSA128D
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSA128H
      0,	// sub_32
      68,	// sub_64 -> MSA128H
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      68,	// sub_hi -> MSA128H
      68,	// sub_lo -> MSA128H
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSA128W
      0,	// sub_32
      69,	// sub_64 -> MSA128W
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      69,	// sub_hi -> MSA128W
      69,	// sub_lo -> MSA128W
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// MSA128WEvens
      0,	// sub_32
      70,	// sub_64 -> MSA128WEvens
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      70,	// sub_hi -> MSA128WEvens
      70,	// sub_lo -> MSA128WEvens
      0,	// sub_hi_then_sub_32
      0,	// sub_32_sub_hi_then_sub_32
    },
    {	// ACC128
      71,	// sub_32 -> ACC128
      0,	// sub_64
      0,	// sub_dsp16_19
      0,	// sub_dsp20
      0,	// sub_dsp21
      0,	// sub_dsp22
      0,	// sub_dsp23
      71,	// sub_hi -> ACC128
      71,	// sub_lo -> ACC128
      71,	// sub_hi_then_sub_32 -> ACC128
      71,	// sub_32_sub_hi_then_sub_32 -> ACC128
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[71][11] = {
    {	// MSA128F16
      0,	// MSA128F16:sub_32
      38,	// MSA128F16:sub_64 -> FGR64CC
      0,	// MSA128F16:sub_dsp16_19
      0,	// MSA128F16:sub_dsp20
      0,	// MSA128F16:sub_dsp21
      0,	// MSA128F16:sub_dsp22
      0,	// MSA128F16:sub_dsp23
      0,	// MSA128F16:sub_hi
      7,	// MSA128F16:sub_lo -> FGR32
      0,	// MSA128F16:sub_hi_then_sub_32
      0,	// MSA128F16:sub_32_sub_hi_then_sub_32
    },
    {	// CCR
      0,	// CCR:sub_32
      0,	// CCR:sub_64
      0,	// CCR:sub_dsp16_19
      0,	// CCR:sub_dsp20
      0,	// CCR:sub_dsp21
      0,	// CCR:sub_dsp22
      0,	// CCR:sub_dsp23
      0,	// CCR:sub_hi
      0,	// CCR:sub_lo
      0,	// CCR:sub_hi_then_sub_32
      0,	// CCR:sub_32_sub_hi_then_sub_32
    },
    {	// COP0
      0,	// COP0:sub_32
      0,	// COP0:sub_64
      0,	// COP0:sub_dsp16_19
      0,	// COP0:sub_dsp20
      0,	// COP0:sub_dsp21
      0,	// COP0:sub_dsp22
      0,	// COP0:sub_dsp23
      0,	// COP0:sub_hi
      0,	// COP0:sub_lo
      0,	// COP0:sub_hi_then_sub_32
      0,	// COP0:sub_32_sub_hi_then_sub_32
    },
    {	// COP2
      0,	// COP2:sub_32
      0,	// COP2:sub_64
      0,	// COP2:sub_dsp16_19
      0,	// COP2:sub_dsp20
      0,	// COP2:sub_dsp21
      0,	// COP2:sub_dsp22
      0,	// COP2:sub_dsp23
      0,	// COP2:sub_hi
      0,	// COP2:sub_lo
      0,	// COP2:sub_hi_then_sub_32
      0,	// COP2:sub_32_sub_hi_then_sub_32
    },
    {	// COP3
      0,	// COP3:sub_32
      0,	// COP3:sub_64
      0,	// COP3:sub_dsp16_19
      0,	// COP3:sub_dsp20
      0,	// COP3:sub_dsp21
      0,	// COP3:sub_dsp22
      0,	// COP3:sub_dsp23
      0,	// COP3:sub_hi
      0,	// COP3:sub_lo
      0,	// COP3:sub_hi_then_sub_32
      0,	// COP3:sub_32_sub_hi_then_sub_32
    },
    {	// DSPR
      0,	// DSPR:sub_32
      0,	// DSPR:sub_64
      0,	// DSPR:sub_dsp16_19
      0,	// DSPR:sub_dsp20
      0,	// DSPR:sub_dsp21
      0,	// DSPR:sub_dsp22
      0,	// DSPR:sub_dsp23
      0,	// DSPR:sub_hi
      0,	// DSPR:sub_lo
      0,	// DSPR:sub_hi_then_sub_32
      0,	// DSPR:sub_32_sub_hi_then_sub_32
    },
    {	// FGR32
      0,	// FGR32:sub_32
      0,	// FGR32:sub_64
      0,	// FGR32:sub_dsp16_19
      0,	// FGR32:sub_dsp20
      0,	// FGR32:sub_dsp21
      0,	// FGR32:sub_dsp22
      0,	// FGR32:sub_dsp23
      0,	// FGR32:sub_hi
      0,	// FGR32:sub_lo
      0,	// FGR32:sub_hi_then_sub_32
      0,	// FGR32:sub_32_sub_hi_then_sub_32
    },
    {	// FGR32CC
      0,	// FGR32CC:sub_32
      0,	// FGR32CC:sub_64
      0,	// FGR32CC:sub_dsp16_19
      0,	// FGR32CC:sub_dsp20
      0,	// FGR32CC:sub_dsp21
      0,	// FGR32CC:sub_dsp22
      0,	// FGR32CC:sub_dsp23
      0,	// FGR32CC:sub_hi
      0,	// FGR32CC:sub_lo
      0,	// FGR32CC:sub_hi_then_sub_32
      0,	// FGR32CC:sub_32_sub_hi_then_sub_32
    },
    {	// GPR32
      0,	// GPR32:sub_32
      0,	// GPR32:sub_64
      0,	// GPR32:sub_dsp16_19
      0,	// GPR32:sub_dsp20
      0,	// GPR32:sub_dsp21
      0,	// GPR32:sub_dsp22
      0,	// GPR32:sub_dsp23
      0,	// GPR32:sub_hi
      0,	// GPR32:sub_lo
      0,	// GPR32:sub_hi_then_sub_32
      0,	// GPR32:sub_32_sub_hi_then_sub_32
    },
    {	// HWRegs
      0,	// HWRegs:sub_32
      0,	// HWRegs:sub_64
      0,	// HWRegs:sub_dsp16_19
      0,	// HWRegs:sub_dsp20
      0,	// HWRegs:sub_dsp21
      0,	// HWRegs:sub_dsp22
      0,	// HWRegs:sub_dsp23
      0,	// HWRegs:sub_hi
      0,	// HWRegs:sub_lo
      0,	// HWRegs:sub_hi_then_sub_32
      0,	// HWRegs:sub_32_sub_hi_then_sub_32
    },
    {	// MSACtrl
      0,	// MSACtrl:sub_32
      0,	// MSACtrl:sub_64
      0,	// MSACtrl:sub_dsp16_19
      0,	// MSACtrl:sub_dsp20
      0,	// MSACtrl:sub_dsp21
      0,	// MSACtrl:sub_dsp22
      0,	// MSACtrl:sub_dsp23
      0,	// MSACtrl:sub_hi
      0,	// MSACtrl:sub_lo
      0,	// MSACtrl:sub_hi_then_sub_32
      0,	// MSACtrl:sub_32_sub_hi_then_sub_32
    },
    {	// GPR32NONZERO
      0,	// GPR32NONZERO:sub_32
      0,	// GPR32NONZERO:sub_64
      0,	// GPR32NONZERO:sub_dsp16_19
      0,	// GPR32NONZERO:sub_dsp20
      0,	// GPR32NONZERO:sub_dsp21
      0,	// GPR32NONZERO:sub_dsp22
      0,	// GPR32NONZERO:sub_dsp23
      0,	// GPR32NONZERO:sub_hi
      0,	// GPR32NONZERO:sub_lo
      0,	// GPR32NONZERO:sub_hi_then_sub_32
      0,	// GPR32NONZERO:sub_32_sub_hi_then_sub_32
    },
    {	// CPU16RegsPlusSP
      0,	// CPU16RegsPlusSP:sub_32
      0,	// CPU16RegsPlusSP:sub_64
      0,	// CPU16RegsPlusSP:sub_dsp16_19
      0,	// CPU16RegsPlusSP:sub_dsp20
      0,	// CPU16RegsPlusSP:sub_dsp21
      0,	// CPU16RegsPlusSP:sub_dsp22
      0,	// CPU16RegsPlusSP:sub_dsp23
      0,	// CPU16RegsPlusSP:sub_hi
      0,	// CPU16RegsPlusSP:sub_lo
      0,	// CPU16RegsPlusSP:sub_hi_then_sub_32
      0,	// CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs
      0,	// CPU16Regs:sub_32
      0,	// CPU16Regs:sub_64
      0,	// CPU16Regs:sub_dsp16_19
      0,	// CPU16Regs:sub_dsp20
      0,	// CPU16Regs:sub_dsp21
      0,	// CPU16Regs:sub_dsp22
      0,	// CPU16Regs:sub_dsp23
      0,	// CPU16Regs:sub_hi
      0,	// CPU16Regs:sub_lo
      0,	// CPU16Regs:sub_hi_then_sub_32
      0,	// CPU16Regs:sub_32_sub_hi_then_sub_32
    },
    {	// FCC
      0,	// FCC:sub_32
      0,	// FCC:sub_64
      0,	// FCC:sub_dsp16_19
      0,	// FCC:sub_dsp20
      0,	// FCC:sub_dsp21
      0,	// FCC:sub_dsp22
      0,	// FCC:sub_dsp23
      0,	// FCC:sub_hi
      0,	// FCC:sub_lo
      0,	// FCC:sub_hi_then_sub_32
      0,	// FCC:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16
      0,	// GPRMM16:sub_32
      0,	// GPRMM16:sub_64
      0,	// GPRMM16:sub_dsp16_19
      0,	// GPRMM16:sub_dsp20
      0,	// GPRMM16:sub_dsp21
      0,	// GPRMM16:sub_dsp22
      0,	// GPRMM16:sub_dsp23
      0,	// GPRMM16:sub_hi
      0,	// GPRMM16:sub_lo
      0,	// GPRMM16:sub_hi_then_sub_32
      0,	// GPRMM16:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP
      0,	// GPRMM16MoveP:sub_32
      0,	// GPRMM16MoveP:sub_64
      0,	// GPRMM16MoveP:sub_dsp16_19
      0,	// GPRMM16MoveP:sub_dsp20
      0,	// GPRMM16MoveP:sub_dsp21
      0,	// GPRMM16MoveP:sub_dsp22
      0,	// GPRMM16MoveP:sub_dsp23
      0,	// GPRMM16MoveP:sub_hi
      0,	// GPRMM16MoveP:sub_lo
      0,	// GPRMM16MoveP:sub_hi_then_sub_32
      0,	// GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16Zero
      0,	// GPRMM16Zero:sub_32
      0,	// GPRMM16Zero:sub_64
      0,	// GPRMM16Zero:sub_dsp16_19
      0,	// GPRMM16Zero:sub_dsp20
      0,	// GPRMM16Zero:sub_dsp21
      0,	// GPRMM16Zero:sub_dsp22
      0,	// GPRMM16Zero:sub_dsp23
      0,	// GPRMM16Zero:sub_hi
      0,	// GPRMM16Zero:sub_lo
      0,	// GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16Zero
      0,	// CPU16Regs_and_GPRMM16Zero:sub_32
      0,	// CPU16Regs_and_GPRMM16Zero:sub_64
      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,	// CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,	// CPU16Regs_and_GPRMM16Zero:sub_hi
      0,	// CPU16Regs_and_GPRMM16Zero:sub_lo
      0,	// CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// GPR32NONZERO_and_GPRMM16MoveP
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_32
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_64
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_hi
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_lo
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,	// GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairSecond
      0,	// GPRMM16MovePPairSecond:sub_32
      0,	// GPRMM16MovePPairSecond:sub_64
      0,	// GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// GPRMM16MovePPairSecond:sub_dsp20
      0,	// GPRMM16MovePPairSecond:sub_dsp21
      0,	// GPRMM16MovePPairSecond:sub_dsp22
      0,	// GPRMM16MovePPairSecond:sub_dsp23
      0,	// GPRMM16MovePPairSecond:sub_hi
      0,	// GPRMM16MovePPairSecond:sub_lo
      0,	// GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16MoveP
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_32
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_64
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp20
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp21
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp22
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_dsp23
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_hi
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_lo
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,	// CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP_and_GPRMM16Zero
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_32
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_64
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_hi
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_lo
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// HI32DSP
      0,	// HI32DSP:sub_32
      0,	// HI32DSP:sub_64
      0,	// HI32DSP:sub_dsp16_19
      0,	// HI32DSP:sub_dsp20
      0,	// HI32DSP:sub_dsp21
      0,	// HI32DSP:sub_dsp22
      0,	// HI32DSP:sub_dsp23
      0,	// HI32DSP:sub_hi
      0,	// HI32DSP:sub_lo
      0,	// HI32DSP:sub_hi_then_sub_32
      0,	// HI32DSP:sub_32_sub_hi_then_sub_32
    },
    {	// LO32DSP
      0,	// LO32DSP:sub_32
      0,	// LO32DSP:sub_64
      0,	// LO32DSP:sub_dsp16_19
      0,	// LO32DSP:sub_dsp20
      0,	// LO32DSP:sub_dsp21
      0,	// LO32DSP:sub_dsp22
      0,	// LO32DSP:sub_dsp23
      0,	// LO32DSP:sub_hi
      0,	// LO32DSP:sub_lo
      0,	// LO32DSP:sub_hi_then_sub_32
      0,	// LO32DSP:sub_32_sub_hi_then_sub_32
    },
    {	// CPU16Regs_and_GPRMM16MovePPairSecond
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairFirst
      0,	// GPRMM16MovePPairFirst:sub_32
      0,	// GPRMM16MovePPairFirst:sub_64
      0,	// GPRMM16MovePPairFirst:sub_dsp16_19
      0,	// GPRMM16MovePPairFirst:sub_dsp20
      0,	// GPRMM16MovePPairFirst:sub_dsp21
      0,	// GPRMM16MovePPairFirst:sub_dsp22
      0,	// GPRMM16MovePPairFirst:sub_dsp23
      0,	// GPRMM16MovePPairFirst:sub_hi
      0,	// GPRMM16MovePPairFirst:sub_lo
      0,	// GPRMM16MovePPairFirst:sub_hi_then_sub_32
      0,	// GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// CPURAReg
      0,	// CPURAReg:sub_32
      0,	// CPURAReg:sub_64
      0,	// CPURAReg:sub_dsp16_19
      0,	// CPURAReg:sub_dsp20
      0,	// CPURAReg:sub_dsp21
      0,	// CPURAReg:sub_dsp22
      0,	// CPURAReg:sub_dsp23
      0,	// CPURAReg:sub_hi
      0,	// CPURAReg:sub_lo
      0,	// CPURAReg:sub_hi_then_sub_32
      0,	// CPURAReg:sub_32_sub_hi_then_sub_32
    },
    {	// CPUSPReg
      0,	// CPUSPReg:sub_32
      0,	// CPUSPReg:sub_64
      0,	// CPUSPReg:sub_dsp16_19
      0,	// CPUSPReg:sub_dsp20
      0,	// CPUSPReg:sub_dsp21
      0,	// CPUSPReg:sub_dsp22
      0,	// CPUSPReg:sub_dsp23
      0,	// CPUSPReg:sub_hi
      0,	// CPUSPReg:sub_lo
      0,	// CPUSPReg:sub_hi_then_sub_32
      0,	// CPUSPReg:sub_32_sub_hi_then_sub_32
    },
    {	// DSPCC
      0,	// DSPCC:sub_32
      0,	// DSPCC:sub_64
      0,	// DSPCC:sub_dsp16_19
      0,	// DSPCC:sub_dsp20
      0,	// DSPCC:sub_dsp21
      0,	// DSPCC:sub_dsp22
      0,	// DSPCC:sub_dsp23
      0,	// DSPCC:sub_hi
      0,	// DSPCC:sub_lo
      0,	// DSPCC:sub_hi_then_sub_32
      0,	// DSPCC:sub_32_sub_hi_then_sub_32
    },
    {	// GP32
      0,	// GP32:sub_32
      0,	// GP32:sub_64
      0,	// GP32:sub_dsp16_19
      0,	// GP32:sub_dsp20
      0,	// GP32:sub_dsp21
      0,	// GP32:sub_dsp22
      0,	// GP32:sub_dsp23
      0,	// GP32:sub_hi
      0,	// GP32:sub_lo
      0,	// GP32:sub_hi_then_sub_32
      0,	// GP32:sub_32_sub_hi_then_sub_32
    },
    {	// GPR32ZERO
      0,	// GPR32ZERO:sub_32
      0,	// GPR32ZERO:sub_64
      0,	// GPR32ZERO:sub_dsp16_19
      0,	// GPR32ZERO:sub_dsp20
      0,	// GPR32ZERO:sub_dsp21
      0,	// GPR32ZERO:sub_dsp22
      0,	// GPR32ZERO:sub_dsp23
      0,	// GPR32ZERO:sub_hi
      0,	// GPR32ZERO:sub_lo
      0,	// GPR32ZERO:sub_hi_then_sub_32
      0,	// GPR32ZERO:sub_32_sub_hi_then_sub_32
    },
    {	// HI32
      0,	// HI32:sub_32
      0,	// HI32:sub_64
      0,	// HI32:sub_dsp16_19
      0,	// HI32:sub_dsp20
      0,	// HI32:sub_dsp21
      0,	// HI32:sub_dsp22
      0,	// HI32:sub_dsp23
      0,	// HI32:sub_hi
      0,	// HI32:sub_lo
      0,	// HI32:sub_hi_then_sub_32
      0,	// HI32:sub_32_sub_hi_then_sub_32
    },
    {	// LO32
      0,	// LO32:sub_32
      0,	// LO32:sub_64
      0,	// LO32:sub_dsp16_19
      0,	// LO32:sub_dsp20
      0,	// LO32:sub_dsp21
      0,	// LO32:sub_dsp22
      0,	// LO32:sub_dsp23
      0,	// LO32:sub_hi
      0,	// LO32:sub_lo
      0,	// LO32:sub_hi_then_sub_32
      0,	// LO32:sub_32_sub_hi_then_sub_32
    },
    {	// SP32
      0,	// SP32:sub_32
      0,	// SP32:sub_64
      0,	// SP32:sub_dsp16_19
      0,	// SP32:sub_dsp20
      0,	// SP32:sub_dsp21
      0,	// SP32:sub_dsp22
      0,	// SP32:sub_dsp23
      0,	// SP32:sub_hi
      0,	// SP32:sub_lo
      0,	// SP32:sub_hi_then_sub_32
      0,	// SP32:sub_32_sub_hi_then_sub_32
    },
    {	// FGR64CC
      0,	// FGR64CC:sub_32
      0,	// FGR64CC:sub_64
      0,	// FGR64CC:sub_dsp16_19
      0,	// FGR64CC:sub_dsp20
      0,	// FGR64CC:sub_dsp21
      0,	// FGR64CC:sub_dsp22
      0,	// FGR64CC:sub_dsp23
      0,	// FGR64CC:sub_hi
      7,	// FGR64CC:sub_lo -> FGR32
      0,	// FGR64CC:sub_hi_then_sub_32
      0,	// FGR64CC:sub_32_sub_hi_then_sub_32
    },
    {	// FGR64
      0,	// FGR64:sub_32
      0,	// FGR64:sub_64
      0,	// FGR64:sub_dsp16_19
      0,	// FGR64:sub_dsp20
      0,	// FGR64:sub_dsp21
      0,	// FGR64:sub_dsp22
      0,	// FGR64:sub_dsp23
      0,	// FGR64:sub_hi
      7,	// FGR64:sub_lo -> FGR32
      0,	// FGR64:sub_hi_then_sub_32
      0,	// FGR64:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64
      6,	// GPR64:sub_32 -> DSPR
      0,	// GPR64:sub_64
      0,	// GPR64:sub_dsp16_19
      0,	// GPR64:sub_dsp20
      0,	// GPR64:sub_dsp21
      0,	// GPR64:sub_dsp22
      0,	// GPR64:sub_dsp23
      0,	// GPR64:sub_hi
      0,	// GPR64:sub_lo
      0,	// GPR64:sub_hi_then_sub_32
      0,	// GPR64:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32NONZERO
      12,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_64
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
    },
    {	// AFGR64
      0,	// AFGR64:sub_32
      0,	// AFGR64:sub_64
      0,	// AFGR64:sub_dsp16_19
      0,	// AFGR64:sub_dsp20
      0,	// AFGR64:sub_dsp21
      0,	// AFGR64:sub_dsp22
      0,	// AFGR64:sub_dsp23
      8,	// AFGR64:sub_hi -> FGR32CC
      8,	// AFGR64:sub_lo -> FGR32CC
      0,	// AFGR64:sub_hi_then_sub_32
      0,	// AFGR64:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16RegsPlusSP
      13,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs
      14,	// GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_64
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_hi
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_lo
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP
      17,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16Zero
      18,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      19,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      20,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      21,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// ACC64DSP
      0,	// ACC64DSP:sub_32
      0,	// ACC64DSP:sub_64
      0,	// ACC64DSP:sub_dsp16_19
      0,	// ACC64DSP:sub_dsp20
      0,	// ACC64DSP:sub_dsp21
      0,	// ACC64DSP:sub_dsp22
      0,	// ACC64DSP:sub_dsp23
      24,	// ACC64DSP:sub_hi -> HI32DSP
      25,	// ACC64DSP:sub_lo -> LO32DSP
      0,	// ACC64DSP:sub_hi_then_sub_32
      0,	// ACC64DSP:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      22,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      23,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      26,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      27,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      28,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    {	// OCTEON_MPL
      0,	// OCTEON_MPL:sub_32
      0,	// OCTEON_MPL:sub_64
      0,	// OCTEON_MPL:sub_dsp16_19
      0,	// OCTEON_MPL:sub_dsp20
      0,	// OCTEON_MPL:sub_dsp21
      0,	// OCTEON_MPL:sub_dsp22
      0,	// OCTEON_MPL:sub_dsp23
      0,	// OCTEON_MPL:sub_hi
      0,	// OCTEON_MPL:sub_lo
      0,	// OCTEON_MPL:sub_hi_then_sub_32
      0,	// OCTEON_MPL:sub_32_sub_hi_then_sub_32
    },
    {	// OCTEON_P
      0,	// OCTEON_P:sub_32
      0,	// OCTEON_P:sub_64
      0,	// OCTEON_P:sub_dsp16_19
      0,	// OCTEON_P:sub_dsp20
      0,	// OCTEON_P:sub_dsp21
      0,	// OCTEON_P:sub_dsp22
      0,	// OCTEON_P:sub_dsp23
      0,	// OCTEON_P:sub_hi
      0,	// OCTEON_P:sub_lo
      0,	// OCTEON_P:sub_hi_then_sub_32
      0,	// OCTEON_P:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      29,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    {	// ACC64
      0,	// ACC64:sub_32
      0,	// ACC64:sub_64
      0,	// ACC64:sub_dsp16_19
      0,	// ACC64:sub_dsp20
      0,	// ACC64:sub_dsp21
      0,	// ACC64:sub_dsp22
      0,	// ACC64:sub_dsp23
      35,	// ACC64:sub_hi -> HI32
      36,	// ACC64:sub_lo -> LO32
      0,	// ACC64:sub_hi_then_sub_32
      0,	// ACC64:sub_32_sub_hi_then_sub_32
    },
    {	// GP64
      33,	// GP64:sub_32 -> GP32
      0,	// GP64:sub_64
      0,	// GP64:sub_dsp16_19
      0,	// GP64:sub_dsp20
      0,	// GP64:sub_dsp21
      0,	// GP64:sub_dsp22
      0,	// GP64:sub_dsp23
      0,	// GP64:sub_hi
      0,	// GP64:sub_lo
      0,	// GP64:sub_hi_then_sub_32
      0,	// GP64:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_CPURAReg
      30,	// GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_64
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp20
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp21
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp22
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_dsp23
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_hi
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_lo
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
    },
    {	// GPR64_with_sub_32_in_GPR32ZERO
      34,	// GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_64
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_hi
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_lo
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
      0,	// GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
    },
    {	// HI64
      35,	// HI64:sub_32 -> HI32
      0,	// HI64:sub_64
      0,	// HI64:sub_dsp16_19
      0,	// HI64:sub_dsp20
      0,	// HI64:sub_dsp21
      0,	// HI64:sub_dsp22
      0,	// HI64:sub_dsp23
      0,	// HI64:sub_hi
      0,	// HI64:sub_lo
      0,	// HI64:sub_hi_then_sub_32
      0,	// HI64:sub_32_sub_hi_then_sub_32
    },
    {	// LO64
      36,	// LO64:sub_32 -> LO32
      0,	// LO64:sub_64
      0,	// LO64:sub_dsp16_19
      0,	// LO64:sub_dsp20
      0,	// LO64:sub_dsp21
      0,	// LO64:sub_dsp22
      0,	// LO64:sub_dsp23
      0,	// LO64:sub_hi
      0,	// LO64:sub_lo
      0,	// LO64:sub_hi_then_sub_32
      0,	// LO64:sub_32_sub_hi_then_sub_32
    },
    {	// SP64
      31,	// SP64:sub_32 -> CPUSPReg
      0,	// SP64:sub_64
      0,	// SP64:sub_dsp16_19
      0,	// SP64:sub_dsp20
      0,	// SP64:sub_dsp21
      0,	// SP64:sub_dsp22
      0,	// SP64:sub_dsp23
      0,	// SP64:sub_hi
      0,	// SP64:sub_lo
      0,	// SP64:sub_hi_then_sub_32
      0,	// SP64:sub_32_sub_hi_then_sub_32
    },
    {	// MSA128B
      0,	// MSA128B:sub_32
      38,	// MSA128B:sub_64 -> FGR64CC
      0,	// MSA128B:sub_dsp16_19
      0,	// MSA128B:sub_dsp20
      0,	// MSA128B:sub_dsp21
      0,	// MSA128B:sub_dsp22
      0,	// MSA128B:sub_dsp23
      0,	// MSA128B:sub_hi
      7,	// MSA128B:sub_lo -> FGR32
      0,	// MSA128B:sub_hi_then_sub_32
      0,	// MSA128B:sub_32_sub_hi_then_sub_32
    },
    {	// MSA128D
      0,	// MSA128D:sub_32
      38,	// MSA128D:sub_64 -> FGR64CC
      0,	// MSA128D:sub_dsp16_19
      0,	// MSA128D:sub_dsp20
      0,	// MSA128D:sub_dsp21
      0,	// MSA128D:sub_dsp22
      0,	// MSA128D:sub_dsp23
      0,	// MSA128D:sub_hi
      7,	// MSA128D:sub_lo -> FGR32
      0,	// MSA128D:sub_hi_then_sub_32
      0,	// MSA128D:sub_32_sub_hi_then_sub_32
    },
    {	// MSA128H
      0,	// MSA128H:sub_32
      38,	// MSA128H:sub_64 -> FGR64CC
      0,	// MSA128H:sub_dsp16_19
      0,	// MSA128H:sub_dsp20
      0,	// MSA128H:sub_dsp21
      0,	// MSA128H:sub_dsp22
      0,	// MSA128H:sub_dsp23
      0,	// MSA128H:sub_hi
      7,	// MSA128H:sub_lo -> FGR32
      0,	// MSA128H:sub_hi_then_sub_32
      0,	// MSA128H:sub_32_sub_hi_then_sub_32
    },
    {	// MSA128W
      0,	// MSA128W:sub_32
      38,	// MSA128W:sub_64 -> FGR64CC
      0,	// MSA128W:sub_dsp16_19
      0,	// MSA128W:sub_dsp20
      0,	// MSA128W:sub_dsp21
      0,	// MSA128W:sub_dsp22
      0,	// MSA128W:sub_dsp23
      0,	// MSA128W:sub_hi
      7,	// MSA128W:sub_lo -> FGR32
      0,	// MSA128W:sub_hi_then_sub_32
      0,	// MSA128W:sub_32_sub_hi_then_sub_32
    },
    {	// MSA128WEvens
      0,	// MSA128WEvens:sub_32
      39,	// MSA128WEvens:sub_64 -> FGR64
      0,	// MSA128WEvens:sub_dsp16_19
      0,	// MSA128WEvens:sub_dsp20
      0,	// MSA128WEvens:sub_dsp21
      0,	// MSA128WEvens:sub_dsp22
      0,	// MSA128WEvens:sub_dsp23
      0,	// MSA128WEvens:sub_hi
      8,	// MSA128WEvens:sub_lo -> FGR32CC
      0,	// MSA128WEvens:sub_hi_then_sub_32
      0,	// MSA128WEvens:sub_32_sub_hi_then_sub_32
    },
    {	// ACC128
      36,	// ACC128:sub_32 -> LO32
      0,	// ACC128:sub_64
      0,	// ACC128:sub_dsp16_19
      0,	// ACC128:sub_dsp20
      0,	// ACC128:sub_dsp21
      0,	// ACC128:sub_dsp22
      0,	// ACC128:sub_dsp23
      63,	// ACC128:sub_hi -> HI64
      64,	// ACC128:sub_lo -> LO64
      35,	// ACC128:sub_hi_then_sub_32 -> HI32
      59,	// ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &MipsGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {2, 64},  	// MSA128F16
    {0, 0},  	// CCR
    {0, 0},  	// COP0
    {0, 0},  	// COP2
    {0, 0},  	// COP3
    {1, 32},  	// DSPR
    {1, 32},  	// FGR32
    {1, 32},  	// FGR32CC
    {1, 32},  	// GPR32
    {0, 0},  	// HWRegs
    {0, 0},  	// MSACtrl
    {1, 31},  	// GPR32NONZERO
    {1, 9},  	// CPU16RegsPlusSP
    {1, 8},  	// CPU16Regs
    {0, 0},  	// FCC
    {1, 8},  	// GPRMM16
    {1, 8},  	// GPRMM16MoveP
    {1, 8},  	// GPRMM16Zero
    {1, 7},  	// CPU16Regs_and_GPRMM16Zero
    {1, 7},  	// GPR32NONZERO_and_GPRMM16MoveP
    {1, 5},  	// GPRMM16MovePPairSecond
    {1, 4},  	// CPU16Regs_and_GPRMM16MoveP
    {1, 4},  	// GPRMM16MoveP_and_GPRMM16Zero
    {1, 4},  	// HI32DSP
    {1, 4},  	// LO32DSP
    {1, 3},  	// CPU16Regs_and_GPRMM16MovePPairSecond
    {1, 3},  	// GPRMM16MovePPairFirst
    {1, 3},  	// GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
    {1, 2},  	// GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
    {1, 1},  	// CPURAReg
    {1, 1},  	// CPUSPReg
    {1, 1},  	// DSPCC
    {1, 1},  	// GP32
    {1, 1},  	// GPR32ZERO
    {1, 1},  	// HI32
    {1, 1},  	// LO32
    {1, 1},  	// SP32
    {2, 64},  	// FGR64CC
    {2, 64},  	// FGR64
    {1, 32},  	// GPR64
    {1, 31},  	// GPR64_with_sub_32_in_GPR32NONZERO
    {2, 32},  	// AFGR64
    {1, 9},  	// GPR64_with_sub_32_in_CPU16RegsPlusSP
    {1, 8},  	// GPR64_with_sub_32_in_CPU16Regs
    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16MoveP
    {1, 8},  	// GPR64_with_sub_32_in_GPRMM16Zero
    {1, 7},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
    {1, 7},  	// GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
    {1, 5},  	// GPR64_with_sub_32_in_GPRMM16MovePPairSecond
    {2, 8},  	// ACC64DSP
    {1, 4},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
    {1, 4},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
    {1, 3},  	// GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst
    {1, 3},  	// GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
    {0, 0},  	// OCTEON_MPL
    {0, 0},  	// OCTEON_P
    {1, 2},  	// GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
    {2, 2},  	// ACC64
    {1, 1},  	// GP64
    {1, 1},  	// GPR64_with_sub_32_in_CPURAReg
    {1, 1},  	// GPR64_with_sub_32_in_GPR32ZERO
    {1, 1},  	// HI64
    {1, 1},  	// LO64
    {1, 1},  	// SP64
    {2, 64},  	// MSA128B
    {2, 64},  	// MSA128D
    {2, 64},  	// MSA128H
    {2, 64},  	// MSA128W
    {2, 32},  	// MSA128WEvens
    {2, 2},  	// ACC128
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned MipsGenRegisterInfo::
getRegUnitWeight(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
  return 20;
}

// Get the name of this register unit pressure set.
const char *MipsGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "DSPCC",
    "GPR32ZERO",
    "GPR64_with_sub_32_in_CPURAReg",
    "HI32",
    "GPRMM16MovePPairFirst",
    "CPU16Regs_and_GPRMM16MoveP",
    "HI32DSP",
    "LO32DSP",
    "GPRMM16MovePPairSecond",
    "GPRMM16MoveP",
    "ACC64DSP",
    "CPU16Regs",
    "GPRMM16Zero_with_GPRMM16MovePPairSecond",
    "CPU16Regs_with_GPRMM16MovePPairSecond",
    "CPU16Regs_with_GPRMM16MoveP",
    "DSPR",
    "FGR32",
    "MSA128WEvens",
    "FGR32_with_MSA128WEvens",
    "MSA128F16",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned MipsGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,  	// 0: DSPCC
    1,  	// 1: GPR32ZERO
    1,  	// 2: GPR64_with_sub_32_in_CPURAReg
    2,  	// 3: HI32
    3,  	// 4: GPRMM16MovePPairFirst
    5,  	// 5: CPU16Regs_and_GPRMM16MoveP
    5,  	// 6: HI32DSP
    5,  	// 7: LO32DSP
    6,  	// 8: GPRMM16MovePPairSecond
    8,  	// 9: GPRMM16MoveP
    8,  	// 10: ACC64DSP
    10,  	// 11: CPU16Regs
    10,  	// 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
    11,  	// 13: CPU16Regs_with_GPRMM16MovePPairSecond
    13,  	// 14: CPU16Regs_with_GPRMM16MoveP
    32,  	// 15: DSPR
    32,  	// 16: FGR32
    32,  	// 17: MSA128WEvens
    48,  	// 18: FGR32_with_MSA128WEvens
    64,  	// 19: MSA128F16
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 6, 10, -1,
  /* 5 */ 3, 6, 7, 10, -1,
  /* 10 */ 2, 15, -1,
  /* 13 */ 8, 12, 13, 15, -1,
  /* 18 */ 9, 14, 15, -1,
  /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
  /* 30 */ 5, 9, 11, 13, 14, 15, -1,
  /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
  /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
  /* 53 */ 16, 18, 19, -1,
  /* 57 */ 16, 17, 18, 19, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *MipsGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *MipsGenRegisterInfo::
getRegUnitPressureSets(MCRegUnit RegUnit) const {
  assert(static_cast<unsigned>(RegUnit) < 321 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
  return &RCSetsTable[RUSetStartTable[static_cast<unsigned>(RegUnit)]];
}

extern const MCRegisterDesc MipsRegDesc[];
extern const int16_t MipsRegDiffLists[];
extern const LaneBitmask MipsLaneMaskLists[];
extern const char MipsRegStrings[];
extern const char MipsRegClassStrings[];
extern const MCPhysReg MipsRegUnitRoots[][2];
extern const uint16_t MipsSubRegIdxLists[];
extern const uint16_t MipsRegEncodingTable[];
// Mips Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
extern const unsigned MipsDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
extern const unsigned MipsEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
extern const unsigned MipsDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
extern const unsigned MipsEHFlavour0L2DwarfSize;

MipsGenRegisterInfo::
MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+71,
             SubRegIndexNameTable, SubRegIdxRangeTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
                     MipsMCRegisterClasses, 71,
                     MipsRegUnitRoots,
                     321,
                     MipsRegDiffLists,
                     MipsLaneMaskLists,
                     MipsRegStrings,
                     MipsRegClassStrings,
                     MipsSubRegIdxLists,
                     12,
                     MipsRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_N32_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
static const MCPhysReg CSR_N32_SingleFloat_SaveList[] = { Mips::F30, Mips::F28, Mips::F26, Mips::F24, Mips::F22, Mips::F20, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N32_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
static const MCPhysReg CSR_N64_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N64_SingleFloat_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0x00000000, 0x00003fc0, };
static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_O32_SingleFloat_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_SingleFloat_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_Interrupt_32_RegMask,
    CSR_Interrupt_32R6_RegMask,
    CSR_Interrupt_64_RegMask,
    CSR_Interrupt_64R6_RegMask,
    CSR_Mips16RetHelper_RegMask,
    CSR_N32_RegMask,
    CSR_N32_SingleFloat_RegMask,
    CSR_N64_RegMask,
    CSR_N64_SingleFloat_RegMask,
    CSR_O32_RegMask,
    CSR_O32_FP64_RegMask,
    CSR_O32_FPXX_RegMask,
    CSR_O32_SingleFloat_RegMask,
  };
  return ArrayRef(Masks);
}

bool MipsGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isGeneralPurposeRegisterClass(const TargetRegisterClass *RC) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == Mips::ZERO ||
      PhysReg == Mips::ZERO_64 ||
      false;
}

ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_Interrupt_32",
    "CSR_Interrupt_32R6",
    "CSR_Interrupt_64",
    "CSR_Interrupt_64R6",
    "CSR_Mips16RetHelper",
    "CSR_N32",
    "CSR_N32_SingleFloat",
    "CSR_N64",
    "CSR_N64_SingleFloat",
    "CSR_O32",
    "CSR_O32_FP64",
    "CSR_O32_FPXX",
    "CSR_O32_SingleFloat",
  };
  return ArrayRef(Names);
}

const MipsFrameLowering *
MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const MipsFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

