/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

namespace llvm {

extern const int16_t AVRRegDiffLists[] = {
  /* 0 */ -2, 0,
  /* 2 */ 2, -1, 0,
  /* 5 */ -32, 1, 0,
  /* 8 */ -31, 1, 0,
  /* 11 */ -30, 1, 0,
  /* 14 */ -29, 1, 0,
  /* 17 */ -28, 1, 0,
  /* 20 */ -27, 1, 0,
  /* 23 */ -26, 1, 0,
  /* 26 */ 27, 1, 0,
  /* 29 */ 25, 0,
  /* 31 */ 26, 0,
  /* 33 */ 27, 0,
  /* 35 */ 28, 0,
  /* 37 */ 29, 0,
  /* 39 */ 30, 0,
  /* 41 */ 31, 0,
  /* 43 */ 32, 0,
};

extern const LaneBitmask AVRLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), 
  /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), 
};

extern const uint16_t AVRSubRegIdxLists[] = {
  /* 0 */ 2, 1, 
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRRegStrings[] = {
  /* 0 */ "R11R10\000"
  /* 7 */ "R21R20\000"
  /* 14 */ "R31R30\000"
  /* 21 */ "R1R0\000"
  /* 26 */ "R12R11\000"
  /* 33 */ "R22R21\000"
  /* 40 */ "R31\000"
  /* 44 */ "R1\000"
  /* 47 */ "R13R12\000"
  /* 54 */ "R23R22\000"
  /* 61 */ "R3R2\000"
  /* 66 */ "R14R13\000"
  /* 73 */ "R24R23\000"
  /* 80 */ "R3\000"
  /* 83 */ "R15R14\000"
  /* 90 */ "R25R24\000"
  /* 97 */ "R5R4\000"
  /* 102 */ "R16R15\000"
  /* 109 */ "R26R25\000"
  /* 116 */ "R5\000"
  /* 119 */ "R17R16\000"
  /* 126 */ "R27R26\000"
  /* 133 */ "R7R6\000"
  /* 138 */ "R18R17\000"
  /* 145 */ "R27\000"
  /* 149 */ "R7\000"
  /* 152 */ "R19R18\000"
  /* 159 */ "R29R28\000"
  /* 166 */ "R9R8\000"
  /* 171 */ "R20R19\000"
  /* 178 */ "R29\000"
  /* 182 */ "R10R9\000"
  /* 188 */ "SREG\000"
  /* 193 */ "SPH\000"
  /* 197 */ "SPL\000"
  /* 201 */ "SP\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc AVRRegDesc[] = { // Descriptors
  { 6, 0, 0, 0, 0, 0, 0, 0 },
  { 201, 2, 1, 0, 24576, 0, 0, 0 },
  { 193, 1, 3, 2, 4097, 2, 0, 0 },
  { 197, 1, 0, 2, 4096, 2, 0, 0 },
  { 188, 1, 1, 2, 4098, 2, 0, 0 },
  { 23, 1, 43, 2, 4099, 2, 0, 0 },
  { 44, 1, 41, 2, 4100, 2, 0, 0 },
  { 63, 1, 41, 2, 4101, 2, 0, 0 },
  { 80, 1, 39, 2, 4102, 2, 0, 0 },
  { 99, 1, 39, 2, 4103, 2, 0, 0 },
  { 116, 1, 37, 2, 4104, 2, 0, 0 },
  { 135, 1, 37, 2, 4105, 2, 0, 0 },
  { 149, 1, 35, 2, 4106, 2, 0, 0 },
  { 168, 1, 35, 2, 4107, 2, 0, 0 },
  { 185, 1, 26, 2, 4108, 2, 0, 0 },
  { 3, 1, 26, 2, 4109, 2, 0, 0 },
  { 29, 1, 26, 2, 4110, 2, 0, 0 },
  { 50, 1, 26, 2, 4111, 2, 0, 0 },
  { 69, 1, 26, 2, 4112, 2, 0, 0 },
  { 86, 1, 26, 2, 4113, 2, 0, 0 },
  { 105, 1, 26, 2, 4114, 2, 0, 0 },
  { 122, 1, 26, 2, 4115, 2, 0, 0 },
  { 141, 1, 26, 2, 4116, 2, 0, 0 },
  { 155, 1, 26, 2, 4117, 2, 0, 0 },
  { 174, 1, 26, 2, 4118, 2, 0, 0 },
  { 10, 1, 26, 2, 4119, 2, 0, 0 },
  { 36, 1, 26, 2, 4120, 2, 0, 0 },
  { 57, 1, 26, 2, 4121, 2, 0, 0 },
  { 76, 1, 26, 2, 4122, 2, 0, 0 },
  { 93, 1, 26, 2, 4123, 2, 0, 0 },
  { 112, 1, 26, 2, 4124, 2, 0, 0 },
  { 129, 1, 26, 2, 4125, 2, 0, 0 },
  { 145, 1, 33, 2, 4126, 2, 0, 0 },
  { 162, 1, 33, 2, 4127, 2, 0, 0 },
  { 178, 1, 31, 2, 4128, 2, 0, 0 },
  { 17, 1, 31, 2, 4129, 2, 0, 0 },
  { 40, 1, 29, 2, 4130, 2, 0, 0 },
  { 21, 5, 1, 0, 24579, 0, 0, 0 },
  { 61, 8, 1, 0, 24581, 0, 0, 0 },
  { 97, 11, 1, 0, 24583, 0, 0, 0 },
  { 133, 14, 1, 0, 24585, 0, 0, 0 },
  { 166, 17, 1, 0, 24587, 0, 0, 0 },
  { 182, 17, 1, 0, 24588, 0, 0, 0 },
  { 0, 17, 1, 0, 24589, 0, 0, 0 },
  { 26, 17, 1, 0, 24590, 0, 0, 0 },
  { 47, 17, 1, 0, 24591, 0, 0, 0 },
  { 66, 17, 1, 0, 24592, 0, 0, 0 },
  { 83, 17, 1, 0, 24593, 0, 0, 0 },
  { 102, 17, 1, 0, 24594, 0, 0, 0 },
  { 119, 17, 1, 0, 24595, 0, 0, 0 },
  { 138, 17, 1, 0, 24596, 0, 0, 0 },
  { 152, 17, 1, 0, 24597, 0, 0, 0 },
  { 171, 17, 1, 0, 24598, 0, 0, 0 },
  { 7, 17, 1, 0, 24599, 0, 0, 0 },
  { 33, 17, 1, 0, 24600, 0, 0, 0 },
  { 54, 17, 1, 0, 24601, 0, 0, 0 },
  { 73, 17, 1, 0, 24602, 0, 0, 0 },
  { 90, 17, 1, 0, 24603, 0, 0, 0 },
  { 109, 17, 1, 0, 24604, 0, 0, 0 },
  { 126, 17, 1, 0, 24605, 0, 0, 0 },
  { 159, 20, 1, 0, 24607, 0, 0, 0 },
  { 14, 23, 1, 0, 24609, 0, 0, 0 },
};

extern const MCPhysReg AVRRegUnitRoots[][2] = {
  { AVR::SPL },
  { AVR::SPH },
  { AVR::SREG },
  { AVR::R0 },
  { AVR::R1 },
  { AVR::R2 },
  { AVR::R3 },
  { AVR::R4 },
  { AVR::R5 },
  { AVR::R6 },
  { AVR::R7 },
  { AVR::R8 },
  { AVR::R9 },
  { AVR::R10 },
  { AVR::R11 },
  { AVR::R12 },
  { AVR::R13 },
  { AVR::R14 },
  { AVR::R15 },
  { AVR::R16 },
  { AVR::R17 },
  { AVR::R18 },
  { AVR::R19 },
  { AVR::R20 },
  { AVR::R21 },
  { AVR::R22 },
  { AVR::R23 },
  { AVR::R24 },
  { AVR::R25 },
  { AVR::R26 },
  { AVR::R27 },
  { AVR::R28 },
  { AVR::R29 },
  { AVR::R30 },
  { AVR::R31 },
};

namespace {     // Register classes...
  // GPR8 Register Class...
  const MCPhysReg GPR8[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1, 
  };

  // GPR8 Bit set.
  const uint8_t GPR8Bits[] = {
    0xe0, 0xff, 0xff, 0xff, 0x1f, 
  };

  // GPR8NOZ Register Class...
  const MCPhysReg GPR8NOZ[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1, 
  };

  // GPR8NOZ Bit set.
  const uint8_t GPR8NOZBits[] = {
    0xe0, 0xff, 0xff, 0xff, 0x07, 
  };

  // GPR8lo Register Class...
  const MCPhysReg GPR8lo[] = {
    AVR::R15, AVR::R14, AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8, AVR::R7, AVR::R6, AVR::R5, AVR::R4, AVR::R3, AVR::R2, AVR::R0, AVR::R1, 
  };

  // GPR8lo Bit set.
  const uint8_t GPR8loBits[] = {
    0xe0, 0xff, 0x1f, 
  };

  // LD8 Register Class...
  const MCPhysReg LD8[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R30, AVR::R31, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, 
  };

  // LD8 Bit set.
  const uint8_t LD8Bits[] = {
    0x00, 0x00, 0xe0, 0xff, 0x1f, 
  };

  // GPR8NOZ_and_LD8 Register Class...
  const MCPhysReg GPR8NOZ_and_LD8[] = {
    AVR::R24, AVR::R25, AVR::R18, AVR::R19, AVR::R20, AVR::R21, AVR::R22, AVR::R23, AVR::R26, AVR::R27, AVR::R28, AVR::R29, AVR::R17, AVR::R16, 
  };

  // GPR8NOZ_and_LD8 Bit set.
  const uint8_t GPR8NOZ_and_LD8Bits[] = {
    0x00, 0x00, 0xe0, 0xff, 0x07, 
  };

  // LD8lo Register Class...
  const MCPhysReg LD8lo[] = {
    AVR::R23, AVR::R22, AVR::R21, AVR::R20, AVR::R19, AVR::R18, AVR::R17, AVR::R16, 
  };

  // LD8lo Bit set.
  const uint8_t LD8loBits[] = {
    0x00, 0x00, 0xe0, 0x1f, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    AVR::SREG, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x10, 
  };

  // DREGS Register Class...
  const MCPhysReg DREGS[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9, 
  };

  // DREGS Bit set.
  const uint8_t DREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x3f, 
  };

  // DREGSNOZ Register Class...
  const MCPhysReg DREGSNOZ[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9, 
  };

  // DREGSNOZ Bit set.
  const uint8_t DREGSNOZBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x1f, 
  };

  // DREGSMOVW Register Class...
  const MCPhysReg DREGSMOVW[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGSMOVW Bit set.
  const uint8_t DREGSMOVWBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x3a, 
  };

  // DREGSMOVW_and_DREGSNOZ Register Class...
  const MCPhysReg DREGSMOVW_and_DREGSNOZ[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGSMOVW_and_DREGSNOZ Bit set.
  const uint8_t DREGSMOVW_and_DREGSNOZBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 0xaa, 0x1a, 
  };

  // DREGS_with_sub_hi_in_LD8 Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_LD8[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, 
  };

  // DREGS_with_sub_hi_in_LD8 Bit set.
  const uint8_t DREGS_with_sub_hi_in_LD8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
  };

  // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Register Class...
  const MCPhysReg DREGSNOZ_and_DREGS_with_sub_hi_in_LD8[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, 
  };

  // DREGSNOZ_and_DREGS_with_sub_hi_in_LD8 Bit set.
  const uint8_t DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x1f, 
  };

  // DREGS_with_sub_lo_in_LD8 Register Class...
  const MCPhysReg DREGS_with_sub_lo_in_LD8[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, 
  };

  // DREGS_with_sub_lo_in_LD8 Bit set.
  const uint8_t DREGS_with_sub_lo_in_LD8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
  };

  // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Register Class...
  const MCPhysReg DREGSNOZ_and_DREGS_with_sub_lo_in_LD8[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, AVR::R26R25, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, 
  };

  // DREGSNOZ_and_DREGS_with_sub_lo_in_LD8 Bit set.
  const uint8_t DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f, 
  };

  // DREGS_with_sub_lo_in_GPR8lo Register Class...
  const MCPhysReg DREGS_with_sub_lo_in_GPR8lo[] = {
    AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R16R15, AVR::R14R13, AVR::R12R11, AVR::R10R9, 
  };

  // DREGS_with_sub_lo_in_GPR8lo Bit set.
  const uint8_t DREGS_with_sub_lo_in_GPR8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01, 
  };

  // DREGS_with_sub_hi_in_GPR8lo Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_GPR8lo[] = {
    AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, AVR::R14R13, AVR::R12R11, AVR::R10R9, 
  };

  // DREGS_with_sub_hi_in_GPR8lo Bit set.
  const uint8_t DREGS_with_sub_hi_in_GPR8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 
  };

  // DLDREGS Register Class...
  const MCPhysReg DLDREGS[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R31R30, AVR::R27R26, AVR::R29R28, AVR::R17R16, 
  };

  // DLDREGS Bit set.
  const uint8_t DLDREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x3a, 
  };

  // DREGS_with_sub_hi_in_LD8lo Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_LD8lo[] = {
    AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, AVR::R16R15, 
  };

  // DREGS_with_sub_hi_in_LD8lo Bit set.
  const uint8_t DREGS_with_sub_hi_in_LD8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 
  };

  // DREGS_with_sub_lo_in_LD8lo Register Class...
  const MCPhysReg DREGS_with_sub_lo_in_LD8lo[] = {
    AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R24R23, AVR::R22R21, AVR::R20R19, AVR::R18R17, 
  };

  // DREGS_with_sub_lo_in_LD8lo Bit set.
  const uint8_t DREGS_with_sub_lo_in_LD8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
  };

  // DREGSlo Register Class...
  const MCPhysReg DREGSlo[] = {
    AVR::R15R14, AVR::R13R12, AVR::R11R10, AVR::R9R8, AVR::R7R6, AVR::R5R4, AVR::R3R2, AVR::R1R0, 
  };

  // DREGSlo Bit set.
  const uint8_t DREGSloBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xab, 
  };

  // DLDREGS_and_DREGSNOZ Register Class...
  const MCPhysReg DLDREGS_and_DREGSNOZ[] = {
    AVR::R25R24, AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R27R26, AVR::R29R28, AVR::R17R16, 
  };

  // DLDREGS_and_DREGSNOZ Bit set.
  const uint8_t DLDREGS_and_DREGSNOZBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x1a, 
  };

  // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8[] = {
    AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, AVR::R22R21, AVR::R20R19, AVR::R18R17, 
  };

  // DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8 Bit set.
  const uint8_t DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 
  };

  // DREGSLD8lo Register Class...
  const MCPhysReg DREGSLD8lo[] = {
    AVR::R19R18, AVR::R21R20, AVR::R23R22, AVR::R17R16, 
  };

  // DREGSLD8lo Bit set.
  const uint8_t DREGSLD8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 
  };

  // IWREGS Register Class...
  const MCPhysReg IWREGS[] = {
    AVR::R25R24, AVR::R31R30, AVR::R27R26, AVR::R29R28, 
  };

  // IWREGS Bit set.
  const uint8_t IWREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3a, 
  };

  // DREGSNOZ_and_IWREGS Register Class...
  const MCPhysReg DREGSNOZ_and_IWREGS[] = {
    AVR::R25R24, AVR::R27R26, AVR::R29R28, 
  };

  // DREGSNOZ_and_IWREGS Bit set.
  const uint8_t DREGSNOZ_and_IWREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1a, 
  };

  // PTRREGS Register Class...
  const MCPhysReg PTRREGS[] = {
    AVR::R27R26, AVR::R29R28, AVR::R31R30, 
  };

  // PTRREGS Bit set.
  const uint8_t PTRREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DREGSNOZ_and_PTRREGS Register Class...
  const MCPhysReg DREGSNOZ_and_PTRREGS[] = {
    AVR::R27R26, AVR::R29R28, 
  };

  // DREGSNOZ_and_PTRREGS Bit set.
  const uint8_t DREGSNOZ_and_PTRREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // PTRDISPREGS Register Class...
  const MCPhysReg PTRDISPREGS[] = {
    AVR::R31R30, AVR::R29R28, 
  };

  // PTRDISPREGS Bit set.
  const uint8_t PTRDISPREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 
  };

  // DREGSNOZ_and_PTRDISPREGS Register Class...
  const MCPhysReg DREGSNOZ_and_PTRDISPREGS[] = {
    AVR::R29R28, 
  };

  // DREGSNOZ_and_PTRDISPREGS Bit set.
  const uint8_t DREGSNOZ_and_PTRDISPREGSBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Register Class...
  const MCPhysReg DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo[] = {
    AVR::R16R15, 
  };

  // DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo Bit set.
  const uint8_t DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // GPRSP Register Class...
  const MCPhysReg GPRSP[] = {
    AVR::SP, 
  };

  // GPRSP Bit set.
  const uint8_t GPRSPBits[] = {
    0x02, 
  };

  // ZREG Register Class...
  const MCPhysReg ZREG[] = {
    AVR::R31R30, 
  };

  // ZREG Bit set.
  const uint8_t ZREGBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char AVRRegClassStrings[] = {
  /* 0 */ "GPR8NOZ_and_LD8\000"
  /* 16 */ "DREGSNOZ_and_DREGS_with_sub_hi_in_LD8\000"
  /* 54 */ "DREGSNOZ_and_DREGS_with_sub_lo_in_LD8\000"
  /* 92 */ "DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8\000"
  /* 148 */ "GPR8\000"
  /* 153 */ "ZREG\000"
  /* 158 */ "GPRSP\000"
  /* 164 */ "CCR\000"
  /* 168 */ "DLDREGS\000"
  /* 176 */ "DREGSNOZ_and_PTRDISPREGS\000"
  /* 201 */ "DREGSNOZ_and_PTRREGS\000"
  /* 222 */ "DREGSNOZ_and_IWREGS\000"
  /* 242 */ "DREGSMOVW\000"
  /* 252 */ "GPR8NOZ\000"
  /* 260 */ "DLDREGS_and_DREGSNOZ\000"
  /* 281 */ "DREGSMOVW_and_DREGSNOZ\000"
  /* 304 */ "DREGSLD8lo\000"
  /* 315 */ "DREGS_with_sub_hi_in_LD8lo\000"
  /* 342 */ "DREGS_with_sub_lo_in_LD8lo\000"
  /* 369 */ "DREGS_with_sub_hi_in_GPR8lo\000"
  /* 397 */ "DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo\000"
  /* 454 */ "DREGSlo\000"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass AVRMCRegisterClasses[] = {
  { GPR8, GPR8Bits, 148, 32, sizeof(GPR8Bits), AVR::GPR8RegClassID, 8, 1, true, false },
  { GPR8NOZ, GPR8NOZBits, 252, 30, sizeof(GPR8NOZBits), AVR::GPR8NOZRegClassID, 8, 1, true, false },
  { GPR8lo, GPR8loBits, 390, 16, sizeof(GPR8loBits), AVR::GPR8loRegClassID, 8, 1, true, false },
  { LD8, LD8Bits, 12, 16, sizeof(LD8Bits), AVR::LD8RegClassID, 8, 1, true, false },
  { GPR8NOZ_and_LD8, GPR8NOZ_and_LD8Bits, 0, 14, sizeof(GPR8NOZ_and_LD8Bits), AVR::GPR8NOZ_and_LD8RegClassID, 8, 1, true, false },
  { LD8lo, LD8loBits, 309, 8, sizeof(LD8loBits), AVR::LD8loRegClassID, 8, 1, true, false },
  { CCR, CCRBits, 164, 1, sizeof(CCRBits), AVR::CCRRegClassID, 8, 255, true, false },
  { DREGS, DREGSBits, 170, 25, sizeof(DREGSBits), AVR::DREGSRegClassID, 16, 1, true, false },
  { DREGSNOZ, DREGSNOZBits, 272, 24, sizeof(DREGSNOZBits), AVR::DREGSNOZRegClassID, 16, 1, true, false },
  { DREGSMOVW, DREGSMOVWBits, 242, 16, sizeof(DREGSMOVWBits), AVR::DREGSMOVWRegClassID, 16, 1, true, false },
  { DREGSMOVW_and_DREGSNOZ, DREGSMOVW_and_DREGSNOZBits, 281, 15, sizeof(DREGSMOVW_and_DREGSNOZBits), AVR::DREGSMOVW_and_DREGSNOZRegClassID, 16, 1, true, false },
  { DREGS_with_sub_hi_in_LD8, DREGS_with_sub_hi_in_LD8Bits, 29, 14, sizeof(DREGS_with_sub_hi_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8RegClassID, 16, 1, true, false },
  { DREGSNOZ_and_DREGS_with_sub_hi_in_LD8, DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits, 16, 13, sizeof(DREGSNOZ_and_DREGS_with_sub_hi_in_LD8Bits), AVR::DREGSNOZ_and_DREGS_with_sub_hi_in_LD8RegClassID, 16, 1, true, false },
  { DREGS_with_sub_lo_in_LD8, DREGS_with_sub_lo_in_LD8Bits, 67, 13, sizeof(DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
  { DREGSNOZ_and_DREGS_with_sub_lo_in_LD8, DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits, 54, 12, sizeof(DREGSNOZ_and_DREGS_with_sub_lo_in_LD8Bits), AVR::DREGSNOZ_and_DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
  { DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_lo_in_GPR8loBits, 426, 12, sizeof(DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
  { DREGS_with_sub_hi_in_GPR8lo, DREGS_with_sub_hi_in_GPR8loBits, 369, 11, sizeof(DREGS_with_sub_hi_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_GPR8loRegClassID, 16, 1, true, false },
  { DLDREGS, DLDREGSBits, 168, 8, sizeof(DLDREGSBits), AVR::DLDREGSRegClassID, 16, 1, true, false },
  { DREGS_with_sub_hi_in_LD8lo, DREGS_with_sub_hi_in_LD8loBits, 315, 8, sizeof(DREGS_with_sub_hi_in_LD8loBits), AVR::DREGS_with_sub_hi_in_LD8loRegClassID, 16, 1, true, false },
  { DREGS_with_sub_lo_in_LD8lo, DREGS_with_sub_lo_in_LD8loBits, 342, 8, sizeof(DREGS_with_sub_lo_in_LD8loBits), AVR::DREGS_with_sub_lo_in_LD8loRegClassID, 16, 1, true, false },
  { DREGSlo, DREGSloBits, 454, 8, sizeof(DREGSloBits), AVR::DREGSloRegClassID, 16, 1, true, false },
  { DLDREGS_and_DREGSNOZ, DLDREGS_and_DREGSNOZBits, 260, 7, sizeof(DLDREGS_and_DREGSNOZBits), AVR::DLDREGS_and_DREGSNOZRegClassID, 16, 1, true, false },
  { DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8, DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits, 92, 7, sizeof(DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8Bits), AVR::DREGS_with_sub_hi_in_LD8lo_and_DREGS_with_sub_lo_in_LD8RegClassID, 16, 1, true, false },
  { DREGSLD8lo, DREGSLD8loBits, 304, 4, sizeof(DREGSLD8loBits), AVR::DREGSLD8loRegClassID, 16, 1, true, false },
  { IWREGS, IWREGSBits, 235, 4, sizeof(IWREGSBits), AVR::IWREGSRegClassID, 16, 1, true, false },
  { DREGSNOZ_and_IWREGS, DREGSNOZ_and_IWREGSBits, 222, 3, sizeof(DREGSNOZ_and_IWREGSBits), AVR::DREGSNOZ_and_IWREGSRegClassID, 16, 1, true, false },
  { PTRREGS, PTRREGSBits, 214, 3, sizeof(PTRREGSBits), AVR::PTRREGSRegClassID, 16, 1, true, false },
  { DREGSNOZ_and_PTRREGS, DREGSNOZ_and_PTRREGSBits, 201, 2, sizeof(DREGSNOZ_and_PTRREGSBits), AVR::DREGSNOZ_and_PTRREGSRegClassID, 16, 1, true, false },
  { PTRDISPREGS, PTRDISPREGSBits, 189, 2, sizeof(PTRDISPREGSBits), AVR::PTRDISPREGSRegClassID, 16, 1, true, false },
  { DREGSNOZ_and_PTRDISPREGS, DREGSNOZ_and_PTRDISPREGSBits, 176, 1, sizeof(DREGSNOZ_and_PTRDISPREGSBits), AVR::DREGSNOZ_and_PTRDISPREGSRegClassID, 16, 1, true, false },
  { DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8lo, DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits, 397, 1, sizeof(DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loBits), AVR::DREGS_with_sub_hi_in_LD8_and_DREGS_with_sub_lo_in_GPR8loRegClassID, 16, 1, true, false },
  { GPRSP, GPRSPBits, 158, 1, sizeof(GPRSPBits), AVR::GPRSPRegClassID, 16, 1, true, false },
  { ZREG, ZREGBits, 153, 1, sizeof(ZREGBits), AVR::ZREGRegClassID, 16, 1, true, false },
};

// AVR Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0Dwarf2L[] = {
  { 0U, AVR::R1R0 },
  { 1U, AVR::R1 },
  { 2U, AVR::R3R2 },
  { 3U, AVR::R3 },
  { 4U, AVR::R5R4 },
  { 5U, AVR::R5 },
  { 6U, AVR::R7R6 },
  { 7U, AVR::R7 },
  { 8U, AVR::R9R8 },
  { 9U, AVR::R10R9 },
  { 10U, AVR::R11R10 },
  { 11U, AVR::R12R11 },
  { 12U, AVR::R13R12 },
  { 13U, AVR::R14R13 },
  { 14U, AVR::R15R14 },
  { 15U, AVR::R16R15 },
  { 16U, AVR::R17R16 },
  { 17U, AVR::R18R17 },
  { 18U, AVR::R19R18 },
  { 19U, AVR::R20R19 },
  { 20U, AVR::R21R20 },
  { 21U, AVR::R22R21 },
  { 22U, AVR::R23R22 },
  { 23U, AVR::R24R23 },
  { 24U, AVR::R25R24 },
  { 25U, AVR::R26R25 },
  { 26U, AVR::R27R26 },
  { 27U, AVR::R27 },
  { 28U, AVR::R29R28 },
  { 29U, AVR::R29 },
  { 30U, AVR::R31R30 },
  { 31U, AVR::R31 },
  { 32U, AVR::SPL },
  { 33U, AVR::SPH },
  { 88U, AVR::SREG },
};
extern const unsigned AVRDwarfFlavour0Dwarf2LSize = std::size(AVRDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0Dwarf2L[] = {
  { 0U, AVR::R1R0 },
  { 1U, AVR::R1 },
  { 2U, AVR::R3R2 },
  { 3U, AVR::R3 },
  { 4U, AVR::R5R4 },
  { 5U, AVR::R5 },
  { 6U, AVR::R7R6 },
  { 7U, AVR::R7 },
  { 8U, AVR::R9R8 },
  { 9U, AVR::R10R9 },
  { 10U, AVR::R11R10 },
  { 11U, AVR::R12R11 },
  { 12U, AVR::R13R12 },
  { 13U, AVR::R14R13 },
  { 14U, AVR::R15R14 },
  { 15U, AVR::R16R15 },
  { 16U, AVR::R17R16 },
  { 17U, AVR::R18R17 },
  { 18U, AVR::R19R18 },
  { 19U, AVR::R20R19 },
  { 20U, AVR::R21R20 },
  { 21U, AVR::R22R21 },
  { 22U, AVR::R23R22 },
  { 23U, AVR::R24R23 },
  { 24U, AVR::R25R24 },
  { 25U, AVR::R26R25 },
  { 26U, AVR::R27R26 },
  { 27U, AVR::R27 },
  { 28U, AVR::R29R28 },
  { 29U, AVR::R29 },
  { 30U, AVR::R31R30 },
  { 31U, AVR::R31 },
  { 32U, AVR::SPL },
  { 33U, AVR::SPH },
  { 88U, AVR::SREG },
};
extern const unsigned AVREHFlavour0Dwarf2LSize = std::size(AVREHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AVRDwarfFlavour0L2Dwarf[] = {
  { AVR::SP, 32U },
  { AVR::SPH, 33U },
  { AVR::SPL, 32U },
  { AVR::SREG, 88U },
  { AVR::R0, 0U },
  { AVR::R1, 1U },
  { AVR::R2, 2U },
  { AVR::R3, 3U },
  { AVR::R4, 4U },
  { AVR::R5, 5U },
  { AVR::R6, 6U },
  { AVR::R7, 7U },
  { AVR::R8, 8U },
  { AVR::R9, 9U },
  { AVR::R10, 10U },
  { AVR::R11, 11U },
  { AVR::R12, 12U },
  { AVR::R13, 13U },
  { AVR::R14, 14U },
  { AVR::R15, 15U },
  { AVR::R16, 16U },
  { AVR::R17, 17U },
  { AVR::R18, 18U },
  { AVR::R19, 19U },
  { AVR::R20, 20U },
  { AVR::R21, 21U },
  { AVR::R22, 22U },
  { AVR::R23, 23U },
  { AVR::R24, 24U },
  { AVR::R25, 25U },
  { AVR::R26, 26U },
  { AVR::R27, 27U },
  { AVR::R28, 28U },
  { AVR::R29, 29U },
  { AVR::R30, 30U },
  { AVR::R31, 31U },
  { AVR::R1R0, 0U },
  { AVR::R3R2, 2U },
  { AVR::R5R4, 4U },
  { AVR::R7R6, 6U },
  { AVR::R9R8, 8U },
  { AVR::R10R9, 9U },
  { AVR::R11R10, 10U },
  { AVR::R12R11, 11U },
  { AVR::R13R12, 12U },
  { AVR::R14R13, 13U },
  { AVR::R15R14, 14U },
  { AVR::R16R15, 15U },
  { AVR::R17R16, 16U },
  { AVR::R18R17, 17U },
  { AVR::R19R18, 18U },
  { AVR::R20R19, 19U },
  { AVR::R21R20, 20U },
  { AVR::R22R21, 21U },
  { AVR::R23R22, 22U },
  { AVR::R24R23, 23U },
  { AVR::R25R24, 24U },
  { AVR::R26R25, 25U },
  { AVR::R27R26, 26U },
  { AVR::R29R28, 28U },
  { AVR::R31R30, 30U },
};
extern const unsigned AVRDwarfFlavour0L2DwarfSize = std::size(AVRDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair AVREHFlavour0L2Dwarf[] = {
  { AVR::SP, 32U },
  { AVR::SPH, 33U },
  { AVR::SPL, 32U },
  { AVR::SREG, 88U },
  { AVR::R0, 0U },
  { AVR::R1, 1U },
  { AVR::R2, 2U },
  { AVR::R3, 3U },
  { AVR::R4, 4U },
  { AVR::R5, 5U },
  { AVR::R6, 6U },
  { AVR::R7, 7U },
  { AVR::R8, 8U },
  { AVR::R9, 9U },
  { AVR::R10, 10U },
  { AVR::R11, 11U },
  { AVR::R12, 12U },
  { AVR::R13, 13U },
  { AVR::R14, 14U },
  { AVR::R15, 15U },
  { AVR::R16, 16U },
  { AVR::R17, 17U },
  { AVR::R18, 18U },
  { AVR::R19, 19U },
  { AVR::R20, 20U },
  { AVR::R21, 21U },
  { AVR::R22, 22U },
  { AVR::R23, 23U },
  { AVR::R24, 24U },
  { AVR::R25, 25U },
  { AVR::R26, 26U },
  { AVR::R27, 27U },
  { AVR::R28, 28U },
  { AVR::R29, 29U },
  { AVR::R30, 30U },
  { AVR::R31, 31U },
  { AVR::R1R0, 0U },
  { AVR::R3R2, 2U },
  { AVR::R5R4, 4U },
  { AVR::R7R6, 6U },
  { AVR::R9R8, 8U },
  { AVR::R10R9, 9U },
  { AVR::R11R10, 10U },
  { AVR::R12R11, 11U },
  { AVR::R13R12, 12U },
  { AVR::R14R13, 13U },
  { AVR::R15R14, 14U },
  { AVR::R16R15, 15U },
  { AVR::R17R16, 16U },
  { AVR::R18R17, 17U },
  { AVR::R19R18, 18U },
  { AVR::R20R19, 19U },
  { AVR::R21R20, 20U },
  { AVR::R22R21, 21U },
  { AVR::R23R22, 22U },
  { AVR::R24R23, 23U },
  { AVR::R25R24, 24U },
  { AVR::R26R25, 25U },
  { AVR::R27R26, 26U },
  { AVR::R29R28, 28U },
  { AVR::R31R30, 30U },
};
extern const unsigned AVREHFlavour0L2DwarfSize = std::size(AVREHFlavour0L2Dwarf);

extern const uint16_t AVRRegEncodingTable[] = {
  0,
  16,
  33,
  32,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  9,
  5,
  11,
  6,
  13,
  7,
  15,
  8,
  17,
  9,
  19,
  10,
  21,
  11,
  23,
  12,
  25,
  13,
  14,
  15,
};
static inline void InitAVRMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(AVRRegDesc, 62, RA, PC, AVRMCRegisterClasses, 33, AVRRegUnitRoots, 35, AVRRegDiffLists, AVRLaneMaskLists, AVRRegStrings, AVRRegClassStrings, AVRSubRegIdxLists, 3,
AVRRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AVRDwarfFlavour0Dwarf2L, AVRDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AVREHFlavour0Dwarf2L, AVREHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AVRDwarfFlavour0L2Dwarf, AVRDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AVREHFlavour0L2Dwarf, AVREHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

